Apparatus for detecting cracks in semiconductor chips

Abstract

Disclosed is an apparatus for detecting a crack of a semiconductor chip, which can include a crack sensor including a charging pattern disposed on a first surface of a target layer in which a crack to be detected, a charge absorption pattern disposed on a second surface of the target layer, and a connection pattern electrically connecting the charging pattern to the charge absorption pattern. The apparatus for detecting a crack can further include a charger for charging the charging pattern with an electric charge, an image detector for obtaining an image of the charging pattern, and a determination unit for detecting a discolored charging pattern from the image of the charging pattern and determining that a crack has occurred in a portion in which the discolored charging pattern of the target layer is located.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0110535, filed on August 20, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to semiconductor technology, and more specifically to an apparatus for detecting cracks in a semiconductor chip. Background Technology

[0004] Integrated circuits (ICs) can be repeatedly formed on a wafer, and the wafer can be separated into individual semiconductor chips. A wafer can be diced or cut into multiple semiconductor chips. The semiconductor chips separated from the wafer can be packaged into semiconductor packages. Cracks may occur within the semiconductor chips during the processes of separating the wafer into semiconductor chips or packaging semiconductor chips. It is necessary to detect these cracks within the semiconductor chips. Summary of the Invention

[0005] An apparatus for detecting cracks according to an embodiment of the present disclosure includes: a target layer; a charging pattern disposed on a first surface of the target layer; a charge absorption pattern disposed on a second surface of the target layer opposite to the first surface; a connecting pattern electrically connecting the charging pattern to the charge absorption pattern; a charger for charging the charging pattern; an image detector for acquiring an image of the charging pattern wherein the charge is applied; and a determining unit for detecting a color change in at least one of the charging patterns from the image of the charging pattern, and determining that a crack has appeared in the portion of the target layer where the detected color change of the charging pattern is located.

[0006] An apparatus for detecting cracks according to another embodiment of the present disclosure includes: a semiconductor substrate including a chip region and a scribe region; a target layer disposed on the semiconductor substrate; a charging pattern disposed on a first surface of the target layer; a connection pattern electrically connecting the charging pattern to the scribe region of the semiconductor substrate; a charger for charging the charging pattern; an image detector for acquiring an image of the charging pattern in which the charge is applied; and a determination unit for detecting a color change of at least one of the charging patterns from the image of the charging pattern, and determining that a crack has appeared in the portion of the target layer where the charging pattern with the color change is located.

[0007] An apparatus for detecting cracks according to another embodiment of the present disclosure includes: a semiconductor substrate including a chip region and a scribe region; an insulating layer disposed on the semiconductor substrate; a target layer disposed on the insulating layer; a charging pattern disposed on a first surface of the target layer and located above the scribe region; a charge absorption pattern disposed on a second surface of the target layer opposite to the first surface; a connection pattern electrically connecting the charging pattern to the charge absorption pattern; a charger for charging the charging pattern; an image detector for acquiring an image of the charging pattern in which the charge has been charged; and a determining unit for detecting a color change of at least one of the charging patterns from the image of the charging pattern, and determining that a crack has appeared in the portion of the target layer where the charging pattern with the color change is located. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating an apparatus for detecting cracks according to an embodiment of the present disclosure.

[0009] Figure 2 It is shown Figure 1 A planar schematic diagram of the planar shape of the crack sensor group of the device used to detect cracks.

[0010] Figure 3 It is shown Figure 1 A planar schematic diagram of the XY plane shape of the crack sensor of the device used for crack detection.

[0011] Figures 4 to 7 It is shown by Figure 1 A schematic diagram of a crack detection device.

[0012] Figure 8 This is a cross-sectional schematic diagram of a crack sensor for a crack detection apparatus according to another embodiment of the present disclosure.

[0013] Figure 9 This is a cross-sectional schematic diagram of a crack sensor for a crack detection apparatus according to another embodiment of the present disclosure.

[0014] Figure 10 This is a plan view of a crack sensor illustrating an apparatus for detecting cracks according to another embodiment of the present disclosure.

[0015] Figure 11 This is a cross-sectional schematic diagram of a crack sensor for a crack detection apparatus according to another embodiment of the present disclosure.

[0016] Figure 12 This is a block diagram illustrating an electronic system employing a memory card including a package according to an embodiment of the present disclosure.

[0017] Figure 13 This is a block diagram illustrating an electronic system including a package according to an embodiment of the present disclosure. Detailed Implementation

[0018] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain.

[0019] It should be understood that although the terms “first” and “second”, “side”, “top” and “bottom or lower” may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another, and not to indicate a particular order or number of elements.

[0020] Semiconductor devices can include semiconductor substrates or structures in which multiple semiconductor substrates are stacked. A semiconductor device can refer to a semiconductor package structure in which a structure of stacked semiconductor substrates is encapsulated. A semiconductor substrate can refer to a semiconductor wafer, semiconductor die, or semiconductor chip in which electronic components and devices are integrated. A semiconductor chip can refer to: a memory chip in which memory integrated circuits such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), NAND flash memory, NOR flash memory, Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (ReRAM), Ferroelectric Random Access Memory (FeRAM), or Phase Change Random Access Memory (PCRAM) are integrated; a logic die or ASIC chip in which logic circuitry is integrated in a semiconductor substrate; or a processor such as an application processor (AP), graphics processing unit (GPU), central processing unit (CPU), or system-on-a-chip (SoC). Semiconductor devices can be used in information and communication systems, such as mobile phones, electronic systems related to biotechnology or healthcare, or wearable electronic systems. Semiconductor devices can be used in the Internet of Things (IoT).

[0021] The same reference numerals refer to the same elements throughout the specification. Although a reference numeral may not be mentioned or described with reference to one drawing, it may be mentioned or described with reference to another drawing. Furthermore, even if a reference numeral may not be shown in one drawing, it may be shown in another drawing.

[0022] Figure 1 This is a schematic diagram of a crack detection device 10 according to an embodiment of the present disclosure. Furthermore, Figure 1 The XZ cross-sectional shape of the semiconductor chip 20 of the device 10 for detecting cracks is shown.

[0023] refer to Figure 1 A crack detection device 10 can be configured to detect cracks that may occur in a semiconductor chip 20. The device 10 may include the semiconductor chip 20, a charger 30, an image detector 40, and a determination unit 50. The semiconductor chip 20 may include a target layer 200 and a crack sensor 60. The charger 30 may include an electron gun. The charger 30 may radiate electrons or an electron beam 31 onto the surface of the crack sensor 60 to substantially charge the crack sensor 60. The image detector 40 may acquire an image of the surface shape of the crack sensor 60. The image detector 40 may include a scanning electron microscope (SEM). The image detector 40 may acquire an SEM image of the surface of the crack sensor 60. The determination unit 50 may control the electron beam radiating operation of the charger 30, control the image detection operation of the image detector 40, and determine whether a crack has occurred based on the acquired image.

[0024] When a crack forms in the semiconductor chip 20, the crack may damage the crack sensor 60. When the charger 30 charges the crack sensor 60 while it is damaged by the crack, the charging state of the crack sensor 60 may change relative to its normal, undamaged charging state. The image detector 40 can detect the change in the charging state of the crack sensor 60 as an image, and the determination unit 50 can use the detected image to determine whether a crack has occurred.

[0025] Semiconductor chip 20 may include semiconductor substrate 100, target layer 200, and crack sensor 60. Semiconductor substrate 100 may include chip region 101 and scribing region 102. Chip region 101 may be a portion of semiconductor substrate 100 in which an integrated circuit is integrated. Scribing region 102 may be another region of semiconductor substrate 100 adjacent to one side of scribing surface 21, which serves as a dividing surface of semiconductor chip 20. Scribing region 102 may include the region between chip region 101 and the dividing surface 21 of semiconductor chip 20. Semiconductor substrate 100 may include a semiconductor material such as silicon (Si). Semiconductor substrate 100 may be a substrate doped with a p-type dopant such as boron (B).

[0026] The semiconductor chip 20 may also include a target layer 200 stacked on the semiconductor substrate 100. The target layer 200 may include a structure with multiple dielectric layers stacked on it. The target layer 200 may include a first dielectric layer 201, a second dielectric layer 202, and a third dielectric layer 203. The target layer 200 may include a greater number of dielectric layers or a lesser number of dielectric layers.

[0027] The semiconductor chip may also include a crack sensor 60. The crack sensor 60 may be positioned on a scribing region 102 of the semiconductor substrate 100. Because the crack sensor 60 is positioned on the scribing region 102 rather than on the chip region 101, the crack sensor 60 can detect cracks appearing in the scribing region 102. The crack sensor 60 may be configured to substantially penetrate the target layer 200, thereby detecting cracks generated in the target layer 200. The crack sensor 60 may be configured to be substantially connected or electrically contacted with the semiconductor substrate 100. The crack sensor 60 can detect cracks generated at the interface between the target layer 200 and the semiconductor substrate 100. In this disclosure, a crack may refer to a fracture portion appearing within the target layer 200 or may refer to a peeling of the target layer 200 relative to the semiconductor substrate 100. A crack may refer to the peeling of a sublayer of the target layer 200.

[0028] Each crack sensor 60 may include a charging pattern 310, a charge sinking pattern 110, and a connection pattern 320. Multiple crack sensors 60 may be aggregated to form a crack sensor group 60G, and may be disposed in a semiconductor chip 20.

[0029] The charging pattern 310 can be disposed on the first surface 211 of the target layer 200. The charging pattern 310 can be disposed on the first surface 211 of the target layer 200, thus located above the scribe region 102 of the semiconductor substrate 100. The first surface 211 of the target layer 200 can be the upper surface of the semiconductor chip 20, exposing the charging pattern 310 to the external environment of the semiconductor chip 20. Therefore, an image of the charging pattern 310 can be detected by the image detector 40. An SEM image of the charging pattern 310 can be obtained by the SEM of the image detector 40. The charging pattern 310 can include a metal pattern. In the obtained SEM image, the metal pattern may have changed color when charged with a charge such as electrons. When the charging pattern 310 is charged with electrons or charge, the charging pattern 310 in the SEM image can change color to a color different from its color in the uncharged or discharged state. The charging pattern 310 can be a metal pattern including metals such as aluminum (Al) or copper (Cu).

[0030] In the SEM image, the charging pattern 310 in which electrons are charged can exhibit a different color than other charging patterns 310 in which electrons are discharged. The image detector 40 uses SEM to detect secondary electrons generated when primary electrons collide with the charging pattern 310 and captures a magnified image of the charging pattern 310. The number of secondary electrons emitted or generated from the charging pattern 310 can vary depending on the charging state of the charging pattern 310. The charging pattern 310 in which electrons are charged can emit a relatively smaller number of secondary electrons than other charging patterns 310 in which electrons are not charged. Therefore, the charging pattern 310 in which electrons are charged can exhibit a darker color than other charging patterns 310 in which electrons are not charged and are discharged.

[0031] The charge absorption pattern 110 may be disposed on the second surface 212 of the target layer 200. The second surface 212 of the target layer 200 may be the surface opposite to the first surface 211. The second surface 212 of the target layer 200 may be the lower surface of the target layer 200 that is interfaced with the semiconductor substrate 100. The charge absorption pattern 110 may include a metal pattern. The charge absorption pattern 110 may include a conductive material such as polysilicon. The charge absorption pattern 110 may be a part of the semiconductor substrate 100. The charge absorption pattern 110 may be formed as a region in the semiconductor substrate 100 doped with a dopant. The charge absorption pattern 110 may include a region in the semiconductor substrate 100 doped with an n-type dopant. The charge absorption pattern 110 may include a conductive well formed by doping the semiconductor substrate 100 with a dopant. The upper portion of the semiconductor substrate 100 may be doped with an n-type dopant such as arsenic (As) or phosphorus (P) to form an N-well, and this N-well may be configured as the charge absorption pattern 110.

[0032] The connecting pattern 320 can be formed as a conductive structure that substantially penetrates the target layer 200. The connecting pattern 320 can electrically connect the charging pattern 310 and the charge absorption pattern 110 to each other. Electrons or charges injected into the charging pattern 310 can move to the charge absorption pattern 110 through the connecting pattern 320. Electrons or charges injected into the charging pattern 310 can escape to the charge absorption pattern 110 through the connecting pattern 320. Therefore, electrons or charges injected into the charging pattern 310 can be erased or discharged by the connecting pattern 320 and the charge absorption pattern 110.

[0033] The connection pattern 320 can be disposed in the target layer 200, thereby located above the scribe region 102 of the semiconductor substrate 100. The connection pattern 320 can be disposed between the scribe surface 21 of the semiconductor chip 20 and the chip region 101. The connection pattern 320 can be disposed between the edge 21E of the semiconductor substrate 100, which is part of the scribe surface 21 of the semiconductor chip 20, and the chip region 101. The charging pattern 310 connected to the connection pattern 320 can be disposed between the edge 21E of the semiconductor substrate 100 and the chip region 101.

[0034] Each connection pattern 320 can be formed of various conductive materials. Connection patterns 320 may include metal patterns or conductive polysilicon patterns. Connection patterns 320 may include conductive contacts 321 that substantially penetrate the target layer 200. Conductive contacts 321 may be formed to penetrate the dielectric layers 201, 202, and 203 constituting the target layer 200. Connection patterns 320 may also include: conductive landing pads 322 located at the interfaces of dielectric layers 201, 202, and 203; and conductive contacts 321 that can be connected to conductive landing pads 322. Conductive landing pads 322 may include metal patterns or conductive polysilicon patterns. Some conductive landing pads 322 may be formed of metal patterns, while others may be formed of conductive polysilicon patterns. Each conductive contact 321 may extend in the stacking direction (i.e., the Z direction) of the first dielectric layer, the second dielectric layer and the third dielectric layer of the target layer 200, while the conductive landing pad 322 may extend in a direction parallel to the upper surface of the semiconductor substrate 100 (i.e., the X direction).

[0035] Figure 2 It is shown Figure 1 A planar schematic diagram of the XY plane shape of the crack sensor group 60G of the device 10 for detecting cracks.

[0036] refer to Figure 2 A crack sensor group 60G, comprising multiple crack sensors 60, can be disposed on a scribing region 102 of a semiconductor substrate 100. The semiconductor substrate 100 may include multiple repeatedly arranged chip regions 101, and the scribing region 102 may be disposed between the chip regions 101. By removing portions of the scribing region 102, the semiconductor substrate 100 can be divided into... Figure 1 Each of the semiconductor chips 20 includes a chip region 101. The semiconductor substrate 100 can be divided along a dividing line 21L provided in the scribe region 102. The process of dividing the semiconductor substrate 100 can be performed by a sawing process using a blade, a laser cutting process using a laser, or a stealth dicing process.

[0037] In the process of dividing the semiconductor substrate 100 along the dividing line 21L, cracks may occur in the scribe region 102 of the semiconductor chip 20 or the semiconductor substrate 100. In order to detect cracks, a crack sensor 60 or a crack sensor group 60G can be distributed throughout the scribe region 102 along the boundary of the chip region 101.

[0038] Figure 3 It is shown Figure 1 A planar schematic diagram of the XY plane shape of the crack sensor 60 of the device 10 for detecting cracks.

[0039] refer to Figure 3 The crack sensor group 60G may include multiple crack sensors 60. The charging pattern 310 may be arranged in multiple matrices on the first surface 211 of the target layer 200 corresponding to the scribe region 102. The charging pattern 310 or crack sensors 60 may be arranged in multiple columns between the chip region 101 and the scribe surface 21 of the semiconductor chip 20. The multiple charging patterns 310 or crack sensors 60 may be arranged in the X-axis direction, and the multiple charging patterns 310 or crack sensors 60 may be arranged in the Y-axis direction.

[0040] A sealing element 250 can be formed to prevent moisture from penetrating into the circuitry integrated into the chip region 101 of the semiconductor chip 20. The sealing element 250 can be formed as a pattern extending along the boundary of the chip region 101 to form a ring shape. Multiple charging patterns 310 or crack sensors 60 can be disposed between the sealing element 250 and the dividing surface 21 of the semiconductor chip 20.

[0041] In the process of dividing the semiconductor substrate 100 along the dividing line 21L, cracks may occur in the semiconductor chip 20 or the scribe region 102 of the semiconductor substrate 100. Cracks may occur in the various layers constituting the semiconductor chip 20. Moisture may be introduced into the semiconductor chip 20 through the cracks. When moisture flows into the semiconductor chip 20, the circuitry integrated in the semiconductor chip 20 may malfunction due to the moisture. Therefore, cracks may become a factor that reduces the yield of the semiconductor chip 20. Therefore, it may be necessary to check the extent to which the crack extends from the dividing line 21L or the dividing surface 21 along the dividing line 21L into the chip region 101. Multiple charging patterns 310 or crack sensors 60 are disposed between the chip region 101 and the dividing surface 21 of the semiconductor chip 20, thereby allowing the extent to which the crack extends from the dividing surface 21 into the chip region 101 to be checked.

[0042] Figures 4 to 7 It is shown by Figure 1 A schematic diagram of crack detection performed by the device 10 for detecting cracks.

[0043] and Figure 1 Let's refer to each other. Figure 4 The charger 30 can radiate electrons (e) or an electron beam 31 to the charging pattern 310 of the crack sensor 60 to charge the charging pattern 310 with electrons or charge. As electrons or charge are charged into the charging pattern 310, the charging pattern 310 can change color to a second color in the SEM image, which is different from the first color in the uncharged state.

[0044] The first connection pattern 321 of the first crack sensor 61 can electrically connect the first charging pattern 311 to the charge absorption pattern 110. Due to cracks that may occur during the division of the dividing surface 21, the second connection pattern 322 of the second crack sensor 62 may be damaged. The second connection pattern 322 may be damaged by cracks and may be unable to connect the second charging pattern 312 to the charge absorption pattern 110. Therefore, the behavior of electrons or charges charged into the first charging pattern 311 and the second charging pattern 312 may differ.

[0045] refer to Figure 5 and Figure 6 Electrons or charges injected into the first charging pattern 311 can escape through the first connection pattern 321 to the charge absorption pattern 110 and be erased. Therefore, the first charging pattern 311 can escape from... Figure 5 The charging state shown is converted to as follows Figure 6 The image shows a state where the injected charge or electrons have been erased. Therefore, as... Figure 6 As shown, the first charging pattern 311 can be obtained from, for example Figure 5 The second color change shown in the charging state is as follows: Figure 6 The first color shown is in the uncharged state.

[0046] refer to Figure 5 and Figure 6 Because the second connecting pattern 322 is disconnected from the charge absorption pattern 110 due to the crack, the electrons or charges introduced into the second charging pattern 312 may not escape to the charge absorption pattern 110. Therefore, the second charging pattern 312 can remain in a state where it is filled with electrons or charges. Therefore, as Figure 5 and Figure 6 As shown, the second charging pattern 312 can remain in the charging state. The second charging pattern 312 can remain as shown... Figure 5 and Figure 6 The second color indicates the charging state.

[0047] After electrons or charges are introduced into the first charging pattern 311 and the second charging pattern 312, it can be achieved through... Figure 1 The image detector 40 in the image detector obtains images of the first charging pattern 311 and the second charging pattern 312 that have been charged. For example... Figure 7 As shown, the images of the first charging pattern 311 and the second charging pattern 312 can indicate that the second charging pattern 312 has a second color that is different from the color of the first charging pattern 311 or other charging patterns 310. The color-changing second charging pattern 312 can be detected from the image of the charging pattern 310, and it can be determined that a color-changing second charging pattern 312 was generated in the portion of the target layer 200 where the color-changing second charging pattern 312 is located. Figure 6 Cracks.

[0048] As described above, the crack detection apparatus according to embodiments of the present disclosure detects whether the charging pattern 310 of the crack sensor 60 remains in a charging state or whether the charged electrons are erased by the charge absorption pattern 110 and the charging pattern 310 is in an erased state, thereby enabling image recognition to determine whether a crack has occurred. Furthermore, by providing multiple crack sensors 60, the location of a crack can be detected.

[0049] Figure 8 This is a schematic cross-sectional view showing a crack sensor 60-1 according to another embodiment of the present disclosure. Figure 8 In the middle, by and Figure 1 Elements represented by the same reference numerals or depicted in the same shape may be understood as substantially the same elements.

[0050] refer to Figure 8 and Figure 1 The device 10 for detecting cracks may include a crack sensor 60-1 according to another embodiment of the present disclosure. The crack sensor 60-1 may include a charging pattern 310, a charge absorption pattern 110, and a connection pattern 320. The target layer 200 may include a first dielectric layer 201, a second dielectric layer 202, and a third dielectric layer 203.

[0051] The connection pattern 320 may include a conductive contact 321. The conductive contact 321 may be formed to penetrate the dielectric layers 201, 202, and 203 constituting the target layer 200. The connection pattern 320 may also include a first conductive landing pad 322-1 and a second conductive landing pad 322-2 located at the interface between the dielectric layers 201, 202, and 203, and the conductive contact 321 may be connected to the first conductive landing pad 322-1 and the second conductive landing pad 322-2. The first conductive landing pad 322-1 may be located at the interface between the second dielectric layer 202 and the third dielectric layer 203, and may be connected to the charging pattern 310 via the conductive contact 321. The first conductive landing pad 322-1 may include a metallic pattern having a wider width or larger area and a larger volume than the charging pattern 310. Therefore, electrons or charges charged into the charging pattern 310 may escape to the first conductive landing pad 322-1 at a higher velocity.

[0052] Figure 9 This is a schematic cross-sectional view showing a crack sensor 60-2 according to another embodiment of the present disclosure. Figure 9 In the middle, by and Figure 1 Elements represented by the same reference numerals or depicted in the same shape may be understood as substantially the same elements.

[0053] refer to Figure 9 and Figure 1 The device 10 for detecting cracks may include a crack sensor 60-2 according to another embodiment of the present disclosure. The crack sensor 60-2 may include a charging pattern 310-2, a charge absorption pattern 110-2, and a connection pattern 320. The charge absorption pattern 110-2 may include conductive wells separated from each other, and the connection patterns 320 are respectively connected to the conductive wells. The semiconductor substrate 100 and the conductive wells may be doped with dopants of opposite conductivity types. The semiconductor substrate 100 may be doped with a p-type dopant, and the conductive wells may be N-wells. Each charging pattern 310-2 may be formed as a pattern having a wider width or a larger area than the conductive landing pad 322 of the connection pattern 320. Because the charging pattern 310-2 is formed as a pattern with a large area, a greater number of electrons or charges can be charged into it. Therefore, the color change of the charging pattern 310-2 can be more easily identified.

[0054] Figure 10 This is a plan view illustrating a crack sensor 60-3 according to another embodiment of the present disclosure. Figure 10 In the middle, by and Figure 1 Elements represented by the same reference numerals or depicted in the same shape may be understood as substantially the same elements.

[0055] refer to Figure 10 and Figure 1 The device 10 for detecting cracks may include a crack sensor 60-3 according to another embodiment of the present disclosure. The crack sensor 60-3 may include a charging pattern 310-3 and a connection pattern 320-3. Each connection pattern 320-3 may include a conductive landing pad 322-3 and a conductive contact 321-3. When viewed in the vertical direction, the conductive landing pad 322-3 may include a metallic pattern orthogonal to the charging pattern 310-3. The conductive landing pad 322-3 and the charging pattern 310-3 are formed from mutually orthogonal metallic patterns, and the conductive landing pad 322-3 and the charging pattern 310-3 may be formed as patterns having a larger area within a finite area.

[0056] Figure 11 This is a schematic cross-sectional view showing a crack sensor 60-4 according to another embodiment of the present disclosure. Figure 11 In the middle, by and Figure 1Elements represented by the same reference numerals or depicted in the same shape may be understood as substantially the same elements.

[0057] refer to Figure 11 and Figure 1 The device 10 for detecting cracks may include a crack sensor 60-4 according to another embodiment of the present disclosure. The crack sensor 60-4 may include a charging pattern 310-4, a connection pattern 320-4, and a charge absorption pattern 110-4. The charging pattern 310-4 may be configured as a metal pattern on a first surface 211-4 of the target layer 200-4. The charge absorption pattern 110-4 may be disposed on a second surface 212-4 of the target layer 200-4. The charge absorption pattern 110-4 may be electrically isolated from the semiconductor substrate 100 by an underlying insulating layer 250. The charge absorption pattern 110-4 may be electrically insulated from the target layer 200-4 by the insulating layer 250 and electrically connected to the charging pattern 310-4 by the connection pattern 320-4. The connection pattern 320-4 may include conductive contacts.

[0058] Electrons or charges charged into the charging pattern 310-4 can move through the connecting pattern 320-4 to the charge absorbing pattern 110-4 and accumulate in the charge absorbing pattern 110-4. Therefore, the charging pattern 310-4 can transition from a charging state to a state in which electrons or charges are erased. The charging pattern 310-4 can remain in a charging state even when the connecting pattern 320-4 is damaged due to a crack and the connection between the charging pattern 310-4 and the charge absorbing pattern 110-4 is severed. The charge absorbing pattern 110-4 may include a metallic pattern with a wider width or larger area and a larger volume than the charging pattern 310-4. Therefore, the amount of electrons or charges that can accumulate in the charge absorbing pattern 110-4 can be increased, allowing electrons or charges to discharge more smoothly into the charge absorbing pattern 110-4. Similar to... Figure 10 The conductive landing pad 322-3, the charge absorption pattern 110-4 can be formed as a metallic pattern orthogonal to the charging pattern 310-4.

[0059] Figure 12 This is a block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to an embodiment.

[0060] The memory 7810 may include a non-volatile storage device to which the technology of the embodiments of this disclosure is applied. The memory controller 7820 may control the memory 7810 in response to a read / write request from the host 7830, such that stored data is read out or stored.

[0061] Figure 13 This is a block diagram illustrating an electronic system 8710 including at least one of a semiconductor package according to an embodiment. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be coupled to each other via a bus 8715 providing a path for data movement.

[0062] In one embodiment, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include at least one semiconductor package according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from keypad, keyboard, display device, and touchscreen. Memory 8713 is a device for storing data. Memory 8713 may store data and / or commands to be executed by controller 8711.

[0063] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory may be installed in an information processing system such as a mobile terminal or a desktop computer. Flash memory may be configured as a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0064] The electronic system 8710 may also include an interface 8714 configured to send data to and receive data from a communication network. The interface 8714 may be of wired or wireless type. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0065] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0066] If the electronic system 8710 is a device capable of performing wireless communication, then the electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0067] The inventive concept has been disclosed in conjunction with the embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should be considered illustrative rather than restrictive. The scope of the inventive concept is not limited to the foregoing description but is defined by the appended claims, and all significant features within the equivalent scope should be interpreted as included in the inventive concept.

Claims

1. An apparatus for detecting cracks, comprising: Target layer; A charging pattern is disposed on the first surface of the target layer; A charge absorption pattern is disposed on a second surface of the target layer opposite to the first surface; A connecting pattern that electrically connects the charging pattern to the charge absorbing pattern; A charger for charging the charging pattern; An image detector for obtaining an image of the charging pattern in which the charge is applied; as well as A determining unit detects a color change in at least one of the charging patterns from an image of the charging pattern, and determines that a crack has appeared in the portion of the target layer where the charging pattern with the detected color change is located. The charging pattern and the connection pattern are disposed between the edge of the semiconductor substrate and the chip area.

2. The apparatus of claim 1, wherein, Each of the charging patterns includes a metallic pattern that changes color as the charge is applied.

3. The apparatus of claim 1, wherein, The image detector includes a scanning electron microscope to obtain an image of the charging pattern.

4. The apparatus of claim 1, wherein, The charge that is incorporated into the charging pattern moves through the connecting pattern to the charge absorption pattern.

5. The apparatus of claim 4, wherein, The charge absorption pattern includes: a region of the semiconductor substrate doped with a dopant.

6. The apparatus of claim 4, wherein, The charge absorption pattern includes a plurality of conductive wells formed by doping a semiconductor substrate with a dopant, which are connected to the connection pattern and separated from each other.

7. The apparatus as claimed in claim 1, in, The target layer is formed by stacking multiple dielectric layers, and The connection pattern includes: Conductive contacts that pass through the dielectric layer; and A conductive landing pad is located at the interface of the dielectric layer, and the conductive contact is connected to the conductive landing pad.

8. The apparatus of claim 7, wherein, Each of the conductive landing pads includes a metal pattern having a larger area and volume than each of the charging patterns.

9. The apparatus of claim 7, wherein, Each of the conductive landing pads includes a metallic pattern orthogonal to the charging pattern.

10. The apparatus of claim 1, wherein, The charger includes an electron gun that radiates electrons to the charging pattern.

11. An apparatus for detecting cracks, comprising: Semiconductor substrate, which includes chip region and scribe region; A target layer disposed on the semiconductor substrate; A charging pattern is disposed on the first surface of the target layer; A connection pattern that electrically connects the charging pattern to the scribe area of ​​the semiconductor substrate; A charger for charging the charging pattern; An image detector for obtaining an image of the charging pattern in which the charge is applied; as well as The determining unit detects a color change in at least one of the charging patterns from an image of the charging pattern, and determines that a crack has appeared in the portion of the target layer where the charging pattern with the color change is located.

12. The apparatus of claim 11, wherein, The charging pattern is located above the scribe area on the semiconductor substrate.

13. The apparatus of claim 11, wherein, The charging pattern is disposed between the edge of the semiconductor substrate and the chip region.

14. The apparatus of claim 11, wherein, The image detector includes a scanning electron microscope to obtain an image of the charging pattern.

15. The apparatus of claim 11, wherein, The charge that is incorporated into the charging pattern moves toward the semiconductor substrate through the connection pattern.

16. The apparatus of claim 15, wherein, The semiconductor substrate includes conductive wells that are separated from each other, and the connection pattern is connected to the conductive wells respectively.

17. The apparatus of claim 16, wherein, The semiconductor substrate and the conductive well are doped with dopants of opposite conductivity types.

18. An apparatus for detecting cracks, comprising: Semiconductor substrate, which includes chip region and scribe region; An insulating layer disposed on the semiconductor substrate; The target layer is disposed on the insulating layer; A charging pattern is disposed on the first surface of the target layer and located above the scribbling area; A charge absorption pattern is disposed on a second surface of the target layer opposite to the first surface; A connecting pattern that electrically connects the charging pattern to the charge absorbing pattern; A charger for charging the charging pattern; An image detector for obtaining an image of the charging pattern in which the charge is applied; as well as The determining unit detects a color change in at least one of the charging patterns from an image of the charging pattern, and determines that a crack has appeared in the portion of the target layer where the charging pattern with the color change is located.

19. The apparatus of claim 18, wherein, Each of the charging patterns includes a metallic pattern that changes color as it is charged with the charge.

20. The apparatus of claim 18, wherein, The charge absorption pattern receives the charge, has a larger area and volume than each of the charging patterns, and includes a metal pattern orthogonal to the charging pattern.

Images