A method for realizing parallel simulation of power electronic system based on loop current method

Abstract

The application provides a loop current method-based parallel simulation implementation method of a power electronic system, and belongs to the application of computer simulation technology in the field of power electronics. The application comprises a processor and memory allocation method and a parallel simulation calculation control process. The processor and memory allocation method utilizes the decoupling characteristics of the simulation algorithm data structure based on the loop current method, preferentially realizes the matching of the processor and the local memory, and improves the access efficiency between the processor and the memory in the calculation process. The parallel simulation calculation process control utilizes the parallelizable characteristics of the simulation algorithm calculation process based on the loop current method, preferentially realizes the parallel calculation of the unit circuit, and improves the calculation efficiency of the power electronic model in the calculation process. The application is suitable for the simulation of a power electronic model comprising a large number of repetitive power electronic modules, can utilize the advantages of the multi-processor and multi-core of a high-performance computer, and significantly improves the simulation efficiency of a large-scale power electronic system.

Description

Technical Field

[0001] This invention pertains to the application of computer simulation technology in the field of power electronics, specifically relating to a parallel simulation implementation method for power electronic systems based on the loop current method. Background Technology

[0002] With the maturation of power electronics simulation technology and the expansion of power electronics applications, traditional circuit simulation algorithms are struggling to meet the simulation needs of large-scale power electronic models, resulting in slow simulation speeds. To improve the simulation efficiency of large-scale power electronic models, various modeling and simulation methods have been proposed and validated by scholars. Among them, the power electronic system simulation method based on the loop current method has the advantages of simple modeling, strong decoupling capability, and high parallelism.

[0003] Most mainstream high-performance computers are based on non-uniform memory access architecture, which has the advantages of a large number of processor cores and a large memory space. However, unreasonable core scheduling methods and memory allocation methods will significantly reduce the efficiency of large-scale power electronic model simulation. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a parallel simulation implementation method for power electronic systems based on the loop current method, thereby solving the problems mentioned in the background art.

[0005] The parallel simulation implementation method for power electronic systems based on the loop current method proposed in this invention includes at least the following steps:

[0006] 1) In the simulation implementation algorithm of this invention, before allocating memory during the simulation initialization phase, it is necessary to calculate the memory capacity m required by region i. i Memory capacity m i Including the region admittance matrix A j k Set, region impedance matrix Z j k Set, the mixed vector X of voltages of all unit circuits within the region. j Current Mixed Vector H j Variable, loop current selection matrix P j Loop voltage E j Loop impedance Z j State space of each device and control system components.

[0007] 2) Considering the actual installation capacity under each NUMA node, allocate the memory space required for simulation calculations in each region, forming a mapping relationship between region number and node number. The allocation principle follows that the matrix set and variable set on the same region i should be allocated to the same memory region under the same node as much as possible. If the remaining memory space cannot meet this principle, allocate the memory space m. i Small regions are divided and placed across nodes.

[0008] 3) The computational flow scheduling method follows the flow of ① parallel computation → ② serial computation → ③ row computation within each simulation step. Specifically, ① parallel computation calculates the voltage E of each unit circuit loop. j and impedance Z j This process can be parallelized because the individual unit circuits are uncoupled from each other. Specifically, step ② involves the serial calculation and accumulation of the loop voltages in all unit circuits, resulting in E = ΣE. j Loop impedance and Z = ΣZ j And solve for the loop admittance A = Z -1 Finally, the loop current R is obtained. In step ③, the parallel calculation process incorporates the loop current R to calculate the node voltage and current values ​​within each unit circuit.

[0009] 4) The parallel scheduling of simulation computation follows these principles: all computational unit regions in the simulation model are sequentially grouped into a matrix queue according to their unit numbers j. All cores on each of the N nodes are then grouped into N independent computation queues. During multi-threaded parallel scheduling, each computation queue first selects its local region unit circuits according to the matrix queue order and assigns them to idle cores on its local node for computation. After completing computation in all local region matrix queues, it selects matrices from other nodes according to the queue order for computation, continuing until all unit circuits in all matrix queues have completed their computations. If a matrix queue is empty, a cross-node core synchronization is performed to ensure all cores have completed their computations before proceeding to the next stage.

[0010] The parallel simulation implementation method for power electronic systems based on the loop current method proposed in this invention is applicable to high-performance computers with NUMA architecture. It matches the power electronic model after the loop current method is divided with the NUMA architecture model, which significantly improves the access efficiency between the computer core and local memory and improves the parallel computing efficiency in multi-core computing.

[0011] The beneficial effects of this invention are:

[0012] This invention fully utilizes the commonalities between the loop current decoupling method structure and the non-uniform memory access architecture computer architecture, placing variables and matrix sets in the same region of the circuit within the same node's memory region, thereby improving memory access efficiency and simulation computation efficiency. This invention binds cores and memory within the same node, ensuring processor affinity during simulation computation and improving simulation computation efficiency. This invention fully utilizes the processor and memory expansion characteristics under the non-uniform memory access architecture to achieve the expansion of the power electronics simulation scale. This invention fully utilizes the parallelizability of the power electronics model based on loop current decoupling to achieve multi-core scheduling during model simulation computation, realizing parallelization of simulation computation. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This invention is based on the fundamental principle and main process of the loop current method.

[0015] Figure 2 This is the main implementation process of parallelizing the simulation calculation process in this invention;

[0016] Figure 3 This is the core parallel computing multi-core scheduling process of the present invention;

[0017] Figure 4 This is a schematic diagram of the processor and memory distribution within the parallel simulation system of this invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention relates to a parallel simulation implementation method for power electronic systems based on the loop current method. This implementation method is applicable to NUMA architecture computers, such as... Figure 4 As shown, this invention corresponds the power electronics simulation model decoupled from the loop current method to the node model in the NUMA structure. All matrix sets and variables located in the same region within the loop current method are allocated to the local memory of the same node, and the core within the node is called for calculation to improve simulation efficiency. A feasible specific implementation method is provided below.

[0020] Before allocating memory space, calculate the memory size m required for the circuit simulation of each region. i The formula for calculating memory usage is as follows:

[0021]

[0022] Where m i The size of the memory space is measured in bytes, d i It is the number of devices in the i-th unit circuit, s k It is the number of states of the k-th device in the regional unit circuit (k = 1, 2, ..., d). i ), b i n is the number of unit circuits in region i. i Where i is the number of circuit nodes in region i, r is the dimension of the loop current R, and e is the number of nodes in the circuit i. k It is the number of electrical quantities of the k-th device in the regional power supply circuit (k = 1, 2, ..., d). i ), such as voltage values, current values, historical current values, secondary current values, etc., sizeof(double) is the number of bytes occupied by a double-precision floating-point number on the operating system platform. This describes the space occupied by the admittance matrix and the impedance matrix; 2b i n i It describes u1-u n Voltage Mixed Vector X j and i1-i n Current Mixing Vector H j Memory space occupied; b i r describes the loop voltage vector E j Memory space occupied; b i r 2 This describes the loop impedance Z. j Memory space occupied; b i n i r describes the loop current selection matrix P. j Memory space occupied; b i Σe k This describes the memory space occupied by each device to store its own voltage and current states; sizeof(double) describes the number of bytes occupied by a double-precision floating-point number in different platforms and compilers. It occupies 8 bytes in mainstream high-performance computers, but may have different values ​​on some specific high-performance computing platforms. i This refers to the memory space occupied by the control system in a single circuit unit, defined by the specific implementation method. i c iThe memory space occupied by all control systems within a region is defined. Generally, the memory space used in circuit simulation is much larger than the memory space occupied by the control system.

[0023] The total memory required for the simulation is Σm i And the total memory installed on all nodes under the NUMA architecture; if the installed memory cannot meet the simulation memory requirements Σm i If an error occurs, the simulation process will stop. If the installed memory can meet the simulation memory requirements, an optimal allocation method will be used to distribute the region memory based on the loop current method to each node on the NUMA architecture. One feasible optimal allocation method is shown in the following formula.

[0024] min(m p ≥m i p∈[1,N]

[0025] Where m p This represents the remaining unallocated memory capacity of the p-th NUMA node, and the memory capacity m required for the i-th region. i Select the remaining capacity m from all nodes. p ≥m i And m p The smallest node is allocated, and the remaining areas that cannot be allocated to a single node are split into different memory parts and allocated across nodes.

[0026] The memory allocation based on the loop current method is shown in the simplified diagram. The set U of all admittance and impedance matrices within the same region... j All variable matrices within the region should be allocated to the same NUMA node as much as possible. When calculating the loop voltage and node voltage within the cell, the processor core reads the matrix constants from the local memory and writes them to the local variables. This results in high processor affinity and high processor cache utilization. Since power electronics simulation is a high-performance computing process, local memory allocation and access on the NUMA node can significantly improve the processor's memory access efficiency and computational efficiency.

[0027] After completing the mapping and allocation relationship between the region memory and the node memory, the admittance matrix is ​​calculated by enumerating the impedance states of all devices in the unit circuit within the region. and its inverse matrix impedance matrix Initialization phase complete.

[0028] Appendix Figure 1 This document outlines the power electronics simulation process based on the loop current method, explaining the fundamental mathematical principles and steps involved in simulation calculations using this method. Figure 2 It is attached Figure 1The simulation algorithm is implemented in parallel by merging the parallelizable stages of the unit circuits, reducing the frequency of parallel computation switching during the simulation calculation stage, increasing the parallel ratio during the simulation calculation process, and guiding the multi-threaded / multi-process implementation of the simulation program to determine the core synchronization node of the NUMA system.

[0029] As attached Figure 1 and attached Figure 2 As shown, in the simulation calculation stage, the large-scale power electronics simulation algorithm based on the loop current method follows the process of ① calculating the loop voltage and loop impedance of the unit circuit → ② calculating the overall loop admittance and loop current of the model → ③ calculating the node voltage and device of the unit circuit. In processes ① and ③, according to the basic principle of decoupling of the loop current method, the calculation process between each unit circuit is independent and has the characteristic of parallelization. At the end of the parallelization stage, a synchronization node is set. In process ②, the calculation of the overall loop current of the model has a coupling relationship and is implemented by serial calculation.

[0030] Appendix Figure 3 This is the core scheduling process for parallel computing nodes. During the simulation calculation phase, due to the characteristics of the NUMA architecture, the efficiency of a processor core accessing the memory under its own node is significantly higher than accessing the memory under other processor nodes via the QPI bus. Therefore, the core scheduling process in this invention prioritizes calculating the unit circuits bound to the current node, and then calculates the unit circuits under other nodes. Specifically, in stages ① and ③, the matrices to be calculated in all unit circuits are arranged into matrix queues according to the unit circuit number j. All cores on each of the N NUMA nodes are arranged into N independent calculation queues. When allocating parallel computing tasks, each calculation queue retrieves the calculation tasks belonging to the local node from the matrix queue and allocates them to the idle cores on the local core. Due to the inherent characteristics of the power electronics simulation model, the number of unit circuits in different regions is unbalanced. After a local node completes the calculation of the matrix queue under its own node, it sequentially reads the calculation tasks under other nodes from the matrix queue for calculation, ensuring that there are no idle cores in any calculation queue when the matrix queue is not empty. The core scheduling process for parallel computing nodes achieves load balancing during parallel computing, improves the utilization rate of all cores in the processor, and increases the simulation speed.

[0031] The following is in conjunction with the appendix Figure 1 Appendix Figure 2 and attached Figure 3 The implementation method of parallel simulation based on the loop current method is explained step by step. The parallel simulation described in this invention involves a multi-core calculation process at least in the simulation calculation stage.

[0032] Step S4 is completed in the main thread / main process, recording the current simulation step size. Step S4 can be recorded at either the beginning or end of the simulation step size.

[0033] Steps S5, S6, and S7 only require internal information from the unit circuit during the calculation process and do not exchange information with external circuits. Therefore, they can be combined and placed into the same parallel scheduling process. A process as shown in the attached diagram is initiated at the beginning of stage S5. Figure 3 The parallel core scheduling process shown here completes the current H of unit S5 in this scheduling process. j Calculate and complete the state index k of unit S6. j Calculate and complete the S7 loop voltage. and loop impedance The calculations are performed, where steps S5 and S6 can be interchanged. After step S7 in this parallel scheduling process, there is a synchronization node. When the program reaches this synchronization node, it must ensure that all computational cores have completed the S7 calculation and are idle, guaranteeing the loop voltage E. j and loop impedance Z j It is consistent with the current device state.

[0034] Steps S8, S9, S10, and S11 calculate the loop current. Because the loop current calculation process is highly coupled with the various unit circuits, it is processed serially. However, steps S9 are independent of S8 and S10 and can be performed in two different cores. Step S9 specifically calculates the sum of the loop voltages, E = ΣE. j In processes S8 and S10, the sum of the loop impedances Z = ΣZ is first calculated. j Then calculate the loop admittance A = Z -1 After completing steps S8, S9, and S10, the loop current R = AE is calculated in the main thread / process. The power electronics simulation method based on the loop current method equates all interactions between a unit circuit and external circuits to a loop current R. Each unit circuit calculates the voltage value of each node within the unit based on the loop current R, and further calculates the current value in each device.

[0035] During the calculation in step S12, each unit module needs to simulate the loop current vector R. The R vector itself is stored in the remote memory of the main thread / main process. Once the loop current vector R is calculated in S11 within a simulation step, it will not be modified. Due to the characteristics of the NUMA structure and cache consistency, the loop current vector R is repeatedly used by each unit circuit in S12. There is a high probability that the local processor cache will save it to the processor's L1 or L2 cache after the first access to the main thread / main process. On processors with low cache, if the loop current vector R is cache-missed, the simulation software can manually copy it to the local memory space to improve access efficiency. Step S12 is a parallel computation step, calling the attached... Figure 3In the core scheduling process, the processor core sequentially calculates the voltage of each unit circuit node. The current within the device is calculated based on the current node voltage. After each core completes the calculation of the device voltage and current within its unit, it determines whether a state change has occurred based on the device state characteristics. In large-scale power electronic systems, this type of change may occur in every unit circuit. Therefore, the calculation core first checks whether a state change exists in each unit circuit, sets the unit circuit device state bits, and then the main thread / main process reads the state bits within each unit to comprehensively determine whether a state change has occurred in the entire simulation model. If a state change is detected in step S12 of the entire power electronic model, it is considered that a device state change has occurred in the simulation result after step S13, and state change event processing is required, calling the state change processing algorithm S14 for processing. One feasible state change processing algorithm is to use the latest obtained device state and jump to step S5 to recalculate the loop current and unit voltage and current values. After the multi-core calculation in step S12 is completed, a synchronization node needs to be set to ensure that all cores have completed their core calculation tasks and are in an idle state when they reach the synchronization node, ensuring the consistency of unit circuit node voltages and device states, and ensuring the synchronization of voltage and current values ​​at various points in the simulation model.

[0036] The global state detection algorithm S13 collects the state detection results from each node and obtains a comprehensive global state detection result. If the global device state has not changed, the system proceeds to the control system execution stage. The unit control signal S15 and the global control signal S16 can be placed either before or after the circuit simulation calculations S5-S14, as shown in the appendix. Figure 2 and attached Figure 3 As shown, their order does not affect the accuracy of the control system and simulation results.

[0037] Step S14 executes the control system within each unit circuit. The feedback detection and control system execution scope is limited to the unit circuit itself, with no coupling relationship with other circuits. Since the computational load of the control system is smaller than that of circuit simulation, the simulation efficiency will not differ significantly. This part can be executed in the main thread / process or in a multi-threaded / multi-process environment. Step S15 executes the global control system, realizing cross-regional and cross-unit circuit control, and exchanging measurement and control information between unit circuits, achieving interaction and coordinated control between multiple control systems. If no control system is set up, S14 and S15 can be skipped.

[0038] After completing the simulation calculation for one step from step S5 to step S16, the voltage and current values ​​in all cells are updated to the latest simulation time t. In step S17, it is determined whether the current simulation time t has reached the set simulation duration T. If the simulation has not been completed, the program jumps to step S5 to continue the simulation calculation for the next step. If the simulation is completed, the program exits the simulation calculation stage and performs the next stage of data export and other tasks.

[0039] The parallel simulation implementation method for power electronic models based on the loop current method described above can achieve the protection content of the claims in this patent application. The protection content of this patent application is implemented in a NUMA architecture computer system, and its implementation method and efficiency are architecture-dependent.

[0040] The implementation method based on the present invention has the following significant features: (1) Power electronic model modeling or decoupling is realized based on the loop current method; (2) The circuit and control system in the multi-core parallel computing model are called during the simulation calculation stage; (3) There is a mixed process of parallel computing and serial computing during the simulation calculation stage, and multi-core synchronization is required at the end of the parallel stage; (4) Under the same computing conditions, the multi-core simulation efficiency is significantly higher than the single-core simulation efficiency, and the multi-processor simulation efficiency is significantly higher than the single-processor simulation efficiency.

[0041] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0042] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A parallel simulation implementation method for power electronic systems based on the loop current method, characterized in that, The implementation method is applicable to power electronic simulation models based on loop current method modeling or decoupling. The implementation method is based on a computer with a Non-Uniform Memory Access (NUMA) architecture. The implementation method involves multiple cores participating in the simulation calculation process. The implementation method includes two parts: a processor and memory allocation method and a parallel scheduling method for simulation calculations. The simulation implementation method includes the following steps: Simulation initialization phase: Admittance matrix A within the computational region j k Impedance matrix Z j k Voltage variable U n Current variable i n memory usage m i ; Based on the space occupied by each area (m) i Traverse the nodes and find the remaining capacity m p ≥m i In the node, m p It is the remaining unallocated memory capacity of the p-th NUMA node. Select the node with the smallest remaining capacity to allocate memory space. Calculate the impedance matrix Z for all state combinations. j k and the region admittance matrix A j k ; Simulation calculation stage: Parallel computation of the voltage E of the loop current in each unit circuit. j and impedance Z j ; Serial calculation and summation of loop voltages in all unit circuits: E = ΣE j Loop impedance and Z = ΣZ j And solve for the loop admittance A = Z -1 The loop current R is obtained; The parallel computing process incorporates the loop current R to calculate the node voltage and current values ​​in each unit circuit; All the unit regions that need to be calculated in the simulation model are arranged into a matrix queue according to the unit number j, and all the cores on each of the N nodes are arranged into N independent calculation queues. During multi-threaded parallel scheduling, each computation queue selects local area unit circuits according to the matrix queue order and allocates them to idle cores on local nodes for computation. After completing the computation of all local area matrix queues, it selects matrices on other nodes from the matrix queues according to the queue order for computation, until all unit circuits in all matrix queues have completed the computation. If the matrix queue is empty, perform a cross-node core synchronization. After all cores have completed their calculations, proceed to the next stage.

2. The parallel simulation implementation method for power electronic systems based on the loop current method according to claim 1, characterized in that, The processor and memory allocation method uses the set of impedance and admittance matrices U generated based on different device states within the same simulation model region. j Place them on the same NUMA node, or place them across nodes when the memory under the node cannot meet the region's memory requirements or when the model is complex and scheduling design is difficult.

3. The parallel simulation implementation method for power electronic systems based on the loop current method according to claim 1, characterized in that, The processor and memory allocation method will use the node voltage vector X of different unit circuits in the same model region. j The value u1-u n and node current vector H j value i1-i n Placed in matrix set U j On the same NUMA node, if the memory under the node cannot meet the voltage and current requirements or the model is complex and the scheduling design is difficult, it can be placed across nodes.

4. The parallel simulation implementation method for power electronic systems based on the loop current method according to claim 1, characterized in that, The simulation computing parallel scheduling method is based on the loop current method for decoupling, which distributes the unit circuit calculation stage in the simulation model calculation process to multiple cores in multiple processors for parallel computing.

5. The parallel simulation implementation method for power electronic systems based on the loop current method according to claim 1, characterized in that, The simulation computing parallel scheduling method, when the number of circuit units in the model is greater than the total number of cores on the computer, queues the circuit units to be computed and assigns them to idle computing cores in turn to complete the unit computation.

6. The parallel simulation implementation method for power electronic systems based on the loop current method according to claim 1, characterized in that, The simulation computing parallel scheduling method states that serial computing and parallel computing phases coexist within a simulation computing step, and the computing progress in different cores is synchronized during the switching between different phases.

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