Integrated circuit chip design method, design device, and storage medium

Abstract

A design method, design device, and storage medium for an integrated circuit chip include: determining an active region injection point location in a design model of the integrated circuit chip; establishing an active region injection point identification region corresponding to the active region injection point location; determining at least one module requiring latch-up verification based on the active region injection point identification region, and performing latch-up verification on the at least one module; in response to successful latch-up verification of the at least one module, assembling the modules in the design model of the integrated circuit chip; and performing latch-up verification on the entire integrated circuit chip. This method can improve integrated circuit chip design efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a design method and device for an integrated circuit chip, and a storage medium. Background Art

[0002] With the rapid development of integrated circuits, the scale of chip designs has increased, and processes have continued to evolve, leading to an increasing risk of latch-up. This is especially true for advanced process technologies like central processing units (CPUs), graphics processing units (GPUs), and network processors. Due to their massive design scale, the physical design involves numerous modules, making it impossible to verify latch-up violations across all related modules within a single module. Full-chip latch-up verification is performed only after all modules are completed. If a latch-up violation occurs, the entire chip design must be modified, posing significant challenges to both the overall chip layout and the development cycle. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a design method for an integrated circuit chip, the design method comprising: determining an active area injection point location in a design model of the integrated circuit chip; establishing an active area injection point identification area corresponding to the active area injection point location; determining at least one module that requires latch verification based on the active area injection point identification area, and performing latch verification on the at least one module; in response to the latch verification being performed on the at least one module and all being successfully verified, splicing the modules in the design model of the integrated circuit chip; and performing latch verification on the entire integrated circuit chip.

[0004] For example, in at least one example, the design method further includes: in response to performing latch verification on at least one module and a first module in the at least one module failing to be verified, adjusting a setting of the first module and performing latch verification on the first module again until the verification succeeds.

[0005] For example, in at least one example, determining the location of an active area injection point in a design model of an integrated circuit chip includes: determining the location of the active area injection point based on bumps in the design model of the integrated circuit chip.

[0006] For example, in at least one example, the bump and the active area injection point location are connected by a trace.

[0007] For example, in at least one example, establishing an active area injection point identification region corresponding to the location of the active area injection point includes: establishing the active area injection point identification region according to voltage information of the active area injection point.

[0008] For example, in at least one example, determining at least one module that needs to be latch-up verified based on the active area injection point identification area includes: creating an active area injection point identification layer corresponding to the active area injection point identification area in the design model of the integrated circuit chip, and superimposing the active area injection point identification layer with each module in the design model of the integrated circuit chip to determine at least one module that needs to be latch-up verified.

[0009] For example, in at least one example, the active area injection point identification layer is located at an upper layer in the design model of the integrated circuit chip, and the active area injection point identification layer is moved downward in the design model of the integrated circuit chip to overlap with various modules in the design model of the integrated circuit chip.

[0010] For example, in at least one example, verifying the modules determined to require latch-up verification includes: performing latch-up verification based on an overlapping area between at least one module and an active region injection point identification layer.

[0011] For example, in at least one example, determining at least one module that requires latch verification based on the active area injection point identification area also includes: completing the self-design and corresponding wiring design of each module in the layer where each module is located in the design model of the integrated circuit chip.

[0012] For example, in at least one example, the design method further includes: in response to an unsuccessful latch-up verification of the entire integrated circuit chip, adjusting the design model of the integrated circuit chip, redetermining the location of the active area injection point, and re-performing the design method.

[0013] At least one embodiment of the present disclosure provides a design device for an integrated circuit chip, the design device comprising:

[0014] A first module is configured to determine an active area injection point location in a design model of an integrated circuit chip;

[0015] A second module is configured to establish an active area injection point identification region corresponding to the location of the active area injection point;

[0016] A third module is configured to determine at least one module that needs to be latch-up verified based on the active area injection point identification area, and perform latch-up verification on the at least one module;

[0017] a fourth module configured to, in response to performing latch verification on at least one module and all the verifications being successful, stitch together the modules in the design model of the integrated circuit chip;

[0018] The fifth module is configured to perform latch verification on the entire integrated circuit chip.

[0019] At least one embodiment of the present disclosure provides an integrated circuit chip design device, including a processor and a memory, wherein the memory stores executable instructions, and when the executable instructions are executed by the processor, the design method of any of the above embodiments is implemented.

[0020] At least one embodiment of the present disclosure provides a non-transitory storage medium, wherein the non-transitory storage medium stores executable instructions, and when the executable instructions are executed by a processor, the design method of any of the above embodiments is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0022] Figure 1 A method for designing an integrated circuit chip according to at least one embodiment of the present disclosure is shown.

[0023] Figure 2 A schematic diagram of a layout design of a design model of an integrated circuit chip according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A flowchart of a design method according to an example of the present disclosure is shown.

[0025] Figure 4 A schematic diagram of an electronic device provided according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0028] Latch-up is a significant issue in CMOS integrated circuits. Latch-up occurs when parasitic bipolar transistors (also known as parasitic silicon-controlled rectifiers, SCRs) inherent in CMOS devices are triggered to conduct, creating a low-impedance, high-current path between the power supply and ground, causing the device to malfunction or even burn out. Latch-up primarily occurs near the active-diode (OD) injector (ODI) connecting the input / output bumps (or pads), targeting the source or drain (S / D) regions of the MOS device.

[0029] For example, during the system-on-chip (SOC) design process, after the overall layout is completed and all modules are complete—that is, after all modules in the overall design have completed their own designs and are placed in their predetermined positions within the overall layout—the modules are then spliced ​​together and subjected to layout netlist consistency (LVS) verification to verify that the layout and logic diagram match. If the LVS result is incorrect, the process returns to the module design and setup phase, repeating the aforementioned steps until LVS verification is performed again. After the LVS result is correct, a full-chip latch verification is performed. If the full-chip latch verification result is correct, verification concludes. If the verification result is incorrect, the overall layout is readjusted, and the aforementioned steps are repeated until the full-chip latch verification result is correct.

[0030] The above design and verification process is performed after the overall layout is completed. The latch verification results cannot be guaranteed. Latch violations can only be discovered after the LVS verification results are correct, which takes a long time. All related latch violations cannot be seen in a single module, and only the full-chip verification results can be waited for. If a latch violation occurs, the overall SOC layout needs to be readjusted, which brings development cycle risks and increases costs.

[0031] At least one embodiment of the present disclosure provides a design method for an integrated circuit chip, the design method comprising: determining an active area injection point position in a design model of the integrated circuit chip; establishing an active area injection point identification area corresponding to the active area injection point position; determining at least one module that requires latch verification based on the active area injection point identification area, and performing latch verification on the at least one module; in response to the latch verification being performed on the at least one module and all being successfully verified, splicing the modules in the design model of the integrated circuit chip; and performing latch verification on the entire integrated circuit chip.

[0032] At least one embodiment of the present disclosure further provides a design device corresponding to the above-mentioned design method and a non-transitory medium storing computer executable codes / instructions for the above-mentioned design method.

[0033] The above-disclosed embodiments can proactively prevent latch-ups in large-scale integrated circuit (IC) chip designs and are applicable to the physical design of various chips. This design method utilizes a top-down design approach, enabling lower-level modules to proactively identify and resolve latch-up violations, rather than a one-step approach. This significantly reduces the need for overall redesign and extended development cycles associated with latch-up violations, thereby reducing costs and improving product competitiveness.

[0034] The embodiments of the present disclosure are described below with reference to specific examples.

[0035] Figure 1 A design method for an integrated circuit chip according to at least one embodiment of the present disclosure is shown, and the design method includes steps 101 to 105:

[0036] Step 101: Determine the location of the active area injection point (ODI) in the design model of the integrated circuit chip.

[0037] Step 102: Create an active area injection point identification region corresponding to the active area injection point position. The source of the latch-up effect is the active area injection point, and the influence range of the latch-up effect can be represented by the active area injection point identification region.

[0038] Step 103: Determine at least one module that needs to be subjected to latch-up verification based on the active region injection point identification area, and perform latch-up verification on the at least one module.

[0039] Step 104 : In response to performing latch verification on at least one module and all the verifications being successful, stitching together the modules in the design model of the integrated circuit chip.

[0040] Step 105: Perform latch verification on the entire integrated circuit chip.

[0041] In the above embodiment, the design model of the integrated circuit chip can be presented in a layout format file. The present disclosure does not limit the specific form of the layout format file. For example, subsequent design and verification steps are performed based on the layout format file.

[0042] Figure 2 FIG. 1 shows a schematic diagram of a layout design of a design model of an integrated circuit chip according to an embodiment of the present disclosure. Figure 2 As shown, the integrated circuit chip under design is, for example, a system-on-chip (SOC), which has an outer frame 201, at least one bump 202 for electrical connection, and multiple modules 203. Each module 203 can be used to implement different functions or the same function in the chip. These modules 203 include module A, module B, and module C. These modules are located at the bottom layer in the design model of the integrated circuit chip, while the part used to implement electrical signal transmission between modules is located at the upper layer (e.g., the top layer). An active area injection point location 204 is provided near the bump 202. The embodiments of the present disclosure do not limit the functions and roles of the modules 203 (e.g., module A, module B, and module C).

[0043] For example, in at least one example, the above-mentioned design method further includes: in response to performing latch verification on at least one module and the verification of the first module in at least one module is unsuccessful, adjusting the settings of the first module and performing latch verification on the first module again until the verification is successful. That is, only after the at least one module that needs to be latch-verified according to the active area injection point identification area is successfully verified, will the subsequent module splicing be entered to obtain the full-chip model and perform latch verification on the full chip. When returning to adjust the settings of the first module, for example, the placement position, border, etc. of the first module can be modified, for example, so that the first module is located outside the active area injection point identification area so as not to be affected by latch violations.

[0044] For step 101, the location of the active area injection point (ODI) can be determined in the design model of the integrated circuit chip by analyzing the design information of the integrated circuit. For example, in at least one example, determining the location of the active area injection point in the design model of the integrated circuit chip includes: determining the location of the active area injection point according to the bump in the design model of the integrated circuit chip. Figure 2 As shown, the active area injection point position 204 is determined according to the bump 202 ; the bump 202 and the active area injection point position 204 are connected via a wiring 206 .

[0045] For example, in at least one example, establishing an active area injection point identification region corresponding to an active area injection point location includes establishing the active area injection point identification region based on voltage information of the active area injection point. The voltage information of the active area injection point can be used to determine the influence range of the latch-up effect, thereby being used to establish the active area injection point identification region.

[0046] For example, in at least one example, determining at least one module requiring latch-up verification based on an active area injection point identification region includes: creating an active area injection point identification layer corresponding to the active area injection point identification region in a design model of an integrated circuit chip, and overlaying the active area injection point identification layer with each module in the design model of the integrated circuit chip to determine at least one module requiring latch-up verification. The active area injection point identification layer is a virtual layer created for operation in the design model of the integrated circuit chip and is not part of the integrated circuit chip. After completing the design and verification of the present disclosure, it can be deleted from the model.

[0047] For example, in at least one example, the active area injection point identification layer is located at an upper layer in the design model of the integrated circuit chip, and the active area injection point identification layer is moved downward in the design model of the integrated circuit chip to overlap with various modules in the design model of the integrated circuit chip. When the active area injection point identification layer is created, it is usually located at the top layer in the model, and various modules in the model are located at a layer below the top layer, usually at the bottom layer.

[0048] For example, in at least one example, verifying the modules that need to be latch-up verified includes: performing latch-up verification based on the overlapping area of ​​at least one module and the active area injection point identification layer. After the active area injection point identification layer is moved downward in the design model of the integrated circuit chip to overlap with each module in the design model of the integrated circuit chip, the modules overlapping with the active area injection point identification layer can be considered to be within the influence range of the latch-up effect and need to be latch-up verified. Figure 2 As shown, among the multiple modules in the bottom layer, modules A, B and C overlap with the active region injection point identification layer 205 , and thus modules A, B and C are determined as modules requiring latch-up verification.

[0049] For example, in at least one example, determining at least one module requiring latch-up verification based on the active area injection point identification region further includes: completing a self-design and a corresponding routing design for each module in a layer where each module is located in a design model of the integrated circuit chip. By completing a self-design and a corresponding routing design for each module (Place & Route).

[0050] For example, in at least one example, in response to the latch-up verification failure of the entire integrated circuit chip, the design model of the integrated circuit chip is adjusted, the active area injection point position is re-determined and the design method is re-performed, that is, returning to the previous initial step and re-performing the previous design method.

[0051] Figure 3 FIG. 1 shows a flow chart of a design method according to an example of the present disclosure; FIG. Figure 3 As shown, the design method in this example includes the following steps 301 to 308:

[0052] Step 301: Find the corresponding active area injection point position according to the bump in the design model of the integrated circuit chip;

[0053] Step 302: establishing an active area injection point identification layer corresponding to the position of the active area injection point in the design model of the integrated circuit chip;

[0054] Step 303: Decentralize the active area injection point identification layer to the module layer in the design model of the integrated circuit chip;

[0055] Step 304: The active area injection point identification layer determines the module that needs to be latched up and verified at the module layer;

[0056] Step 305: Verify the modules that need to be latch-verified. If all modules are successfully verified, proceed to step 306. Otherwise, return to step 304, adjust the settings of the modules in the module layer, and then determine the modules that need to be latch-verified again in the module layer.

[0057] Step 306: Assembling all modules in the design model of the integrated circuit chip;

[0058] Step 307: Perform latch verification on the entire chip. If the verification passes, proceed to step 308. Otherwise, return to step 301 and adjust the design model of the integrated circuit chip.

[0059] Step 308: End.

[0060] At least one embodiment of the present disclosure also provides a design device for an integrated circuit chip, which includes a first module to a fifth module, wherein the first module is configured to determine the active area injection point position in the design model of the integrated circuit chip; the second module is configured to establish an active area injection point identification area corresponding to the active area injection point position; the third module is configured to determine at least one module that needs to be latch-verified based on the active area injection point identification area, and perform latch-verification on at least one module; the fourth module is configured to splice the modules in the design model of the integrated circuit chip in response to the latch-verification of at least one module and all the verifications are successful; the fifth module is configured to perform latch-verification on the entire integrated circuit chip.

[0061] In at least one example, in the above-mentioned design device, the third module is further configured to: in response to performing latch verification on at least one module and failing to verify a first module in the at least one module, adjust the settings of the first module and perform latch verification on the first module again until the verification is successful.

[0062] In at least one example, in the above-mentioned design device, the first module is further configured to: determine the location of the active area injection point based on the bump in the design model of the integrated circuit chip. For example, the bump and the active area injection point are connected by a trace.

[0063] In at least one example, in the above-mentioned design device, the second module is further configured to: establish an active area injection point identification area according to voltage information of the active area injection point.

[0064] In at least one example, in the above-mentioned design device, the third module is further configured to: create an active area injection point identification layer corresponding to the active area injection point identification area in the design model of the integrated circuit chip, and superimpose the active area injection point identification layer with each module in the design model of the integrated circuit chip to determine at least one module that needs to be latched.

[0065] In at least one example, in the above-mentioned design device, for the third module, the active area injection point identification layer is located at the upper layer in the design model of the integrated circuit chip, and the active area injection point identification layer is moved downward in the design model of the integrated circuit chip to overlap with each module in the design model of the integrated circuit chip.

[0066] In at least one example, in the above-mentioned design device, the third module is further configured to: perform latch verification based on the overlapping area of ​​each of the at least one module and the active area injection point identification layer.

[0067] In at least one example, in the above-mentioned design device, the third module is further configured to: complete the self-design and corresponding wiring design for each module in the layer where each module is located in the design model of the integrated circuit chip.

[0068] In at least one example, in the above-mentioned design device, the first module is further configured to: in response to unsuccessful latch verification of the entire integrated circuit chip, adjust the design model of the integrated circuit chip, redetermine the active area injection point position and re-perform the design method.

[0069] At least one embodiment of the present disclosure further provides a design device for an integrated circuit chip, the design device comprising a processor and a memory, wherein the memory stores executable instructions, and when the executable instructions are executed by the processor, the design method of any of the above embodiments is implemented.

[0070] At least one embodiment of the present disclosure further provides a non-transitory storage medium having executable instructions stored thereon. When the executable instructions are executed by a processor, the design method of any of the above embodiments is implemented.

[0071] Some embodiments of the present disclosure further provide an electronic device, which can execute the design method of any of the above embodiments.

[0072] Figure 4 A schematic diagram of an electronic device provided in at least one embodiment of the present disclosure. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as laptop computers, PDAs (personal digital assistants), and tablet computers, as well as fixed terminals such as desktop computers.

[0073] Figure 4 The electronic device 1000 shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 4 As shown, in some examples, the electronic device 1000 includes a processor that can perform various appropriate actions and processes, such as the design method of the embodiment of the present disclosure, according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 into a random access memory (RAM) 1003. Various programs and data required for the operation of the processor are also stored in the RAM 1003. The processor 1001, the ROM 1002, and the RAM 1003 are connected to each other via a bus 1004. An input / output (I / O) interface 1005 is also connected to the bus 1004.

[0074] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, hard disk, etc.; and a communication device 1009, which may also include, for example, a network interface card such as a LAN card or modem. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable storage medium 1011, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in the drive 1010 as needed, so that a computer program read therefrom can be installed into the storage device 1008 as needed.

[0075] Although Figure 4The electronic device 1000 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0076] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0077] The integrated circuit chip design method and design device of at least one embodiment of the present disclosure can, for example, detect latch violations during the overall layout stage of the integrated circuit chip, avoid readjusting the overall chip layout, reduce project progress risks, optimize the latch-up verification process, eliminate the need to wait for LVS verification results, and improve verification efficiency.

[0078] Regarding this disclosure, the following points need to be explained:

[0079] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0080] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0081] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A method for designing an integrated circuit chip, comprising: Determining an active area injection point position in a design model of the integrated circuit chip, wherein the active area injection point position corresponds to an active area injection point, and the active area injection point includes a source of latch-up effect; Establishing an active area injection point identification region corresponding to the position of the active area injection point; Determining at least one module requiring latch-up verification based on the active area injection point identification region, and performing latch-up verification on the at least one module; In response to performing latch verification on the at least one module and all the verifications are successful, stitching together the modules in the design model of the integrated circuit chip; The entire integrated circuit chip is verified for latch-up violations.

2. The design method according to claim 1, further comprising: In response to performing latch verification on the at least one module and a first module in the at least one module failing to be verified, adjusting settings of the first module and performing latch verification on the first module again until the verification succeeds.

3. The design method according to claim 1, wherein: Determining the location of an injection point in an active area in a design model of the integrated circuit chip includes: The active area injection point position is determined according to the bump in the design model of the integrated circuit chip, wherein the bump and the active area injection point position are connected by a wiring.

4. The design method according to claim 1, wherein: Establishing an active area injection point identification region corresponding to the active area injection point position includes: The active area injection point identification region is established according to voltage information of the active area injection point.

5. The design method according to claim 1 or 4, wherein: Determining at least one module requiring latch-up verification based on the active region injection point identification area includes: An active area injection point identification layer corresponding to the active area injection point identification area is created in the design model of the integrated circuit chip, and the active area injection point identification layer is superimposed on each module in the design model of the integrated circuit chip to determine the at least one module that requires latch verification.

6. The design method according to claim 5, wherein: The active area injection point identification layer is located at an upper layer in the design model of the integrated circuit chip. The active area injection point identification layer is moved downward in the design model of the integrated circuit chip to overlap with various modules in the design model of the integrated circuit chip.

7. The design method according to claim 5, wherein: Verify the modules that require latch-up verification, including: The latch-up verification is performed according to an overlapping area between each of the at least one module and the active region injection point identification layer.

8. The design method according to claim 5, wherein: Determining at least one module requiring latch-up verification based on the active area injection point identification area, further comprising: In the layer where each module is located in the design model of the integrated circuit chip, self-design and corresponding wiring design are completed for each module.

9. The design method according to claim 1, further comprising: In response to the latch-up verification of the entire integrated circuit chip being unsuccessful, the design model of the integrated circuit chip is adjusted, the injection point position of the active region is re-determined, and the design method is re-performed.

10. A device for designing an integrated circuit chip, comprising: A first module is configured to determine an active area injection point location in a design model of the integrated circuit chip, wherein the active area injection point location corresponds to an active area injection point, and the active area injection point includes a source of latch-up effect; A second module is configured to establish an active area injection point identification area corresponding to the position of the active area injection point; A third module is configured to determine at least one module that needs to be latch-up verified based on the active area injection point identification area, and perform latch-up verification on the at least one module; a fourth module configured to, in response to performing latch verification on the at least one module and all verifications being successful, stitch together the modules in the design model of the integrated circuit chip; The fifth module is configured to perform latch verification on the entire integrated circuit chip.

11. A device for designing an integrated circuit chip, comprising: processor; A memory, wherein executable instructions are stored on the memory, and when the executable instructions are executed by the processor, the method according to any one of claims 1 to 9 is implemented.

12. A non-transitory storage medium, wherein: The non-transitory storage medium stores executable instructions, and when the executable instructions are executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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