Methods, apparatus, devices, storage media, and systems for processing wafers

Abstract

Embodiments of the present disclosure provide a method, device, equipment, storage medium and system for processing wafers, wherein the method comprises: obtaining a scheduling path of a current batch of wafers; wherein the scheduling path comprises at least one scheduling site for processing the current batch of wafers and a scheduling sequence between the scheduling sites; determining a process recipe corresponding to each scheduling site, respectively; wherein the process recipes corresponding to at least two scheduling sites with the same process condition are the same; and based on the scheduling sequence, sequentially scheduling each scheduling site to execute the process recipe corresponding to the scheduling site, so as to process the current batch of wafers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and relates to but is not limited to a method, device, equipment, storage medium and system for processing a wafer. BACKGROUND

[0002] In semiconductor manufacturing, a wafer is subjected to various processes such as photolithography, etching, ion implantation, thin film deposition, and chemical mechanical polishing. Each batch of wafer processing can have up to thousands of steps. Before the wafer is processed, a process recipe is configured in advance according to product requirements. In practical applications, the process recipe can be configured as a flow recipe to be processed on the wafer, and sub-recipes corresponding to each step of processing the wafer are configured in the flow recipe. The flow recipe can define each scheduling site that the wafer is scheduled to pass through, and the sub-recipes can define the process recipes, detection recipes, and the like that the wafer is scheduled to execute at each scheduling site.

[0003] However, when configuring the flow recipe, the number of scheduling sites that the wafer is scheduled to pass through is large, and the conditions of the sub-recipes executed at each scheduling site are complex. This makes the cost of configuring the process recipe relatively high, and the number of configured process recipes is large, resulting in a large amount of storage memory being occupied. SUMMARY

[0004] Therefore, embodiments of the present disclosure provide a method, device, equipment, storage medium and system for processing a wafer, at least for reducing the storage memory occupied by the process recipe.

[0005] Embodiments of the present disclosure provide a method for processing a wafer, the method comprising:

[0006] obtaining a scheduling path of a current batch of wafers; wherein the scheduling path comprises at least one scheduling site for processing the current batch of wafers and a scheduling order between each of the scheduling sites;

[0007] determining a process recipe corresponding to each of the scheduling sites, respectively; wherein the process recipes corresponding to at least two scheduling sites having the same process condition are the same;

[0008] sequentially scheduling each of the scheduling sites to execute the process recipe corresponding to the scheduling site based on the scheduling order, to process the current batch of wafers.

[0009] Embodiments of the present disclosure provide a device for processing a wafer, the device comprising:

[0010] an obtaining module configured to obtain a scheduling path of a current batch of wafers; wherein the scheduling path comprises at least one scheduling site for processing the current batch of wafers and a scheduling order between each of the scheduling sites;

[0011] a first determining module configured to determine a process recipe corresponding to each of the scheduling stations respectively, wherein the process recipes corresponding to at least two scheduling stations having the same process condition are the same;

[0012] a first scheduling module configured to sequentially schedule each of the scheduling stations to perform the process recipe corresponding to the scheduling station based on the scheduling sequence, so as to process the current batch of wafers.

[0013] The embodiment of the present disclosure provides a device for processing wafers, the device comprising a processor and a memory for storing a computer program capable of running on the processor, wherein the processor is configured to run the computer program to perform the steps of the method as described above.

[0014] The embodiment of the present disclosure provides a computer storage medium having a computer program stored thereon, wherein the computer program is configured to implement the steps of the method as described above when executed by a processor.

[0015] The embodiment of the present disclosure provides a system for processing wafers, the system comprising:

[0016] The device for processing wafers as described above;

[0017] a processing machine configured to perform the process recipe corresponding to the scheduling station according to the scheduling instruction of the device for processing wafers, so as to process the current batch of wafers.

[0018] In the embodiment of the present disclosure, a scheduling path of a current batch of wafers is obtained, the scheduling path comprising at least one scheduling station for processing the current batch of wafers and a scheduling sequence between the scheduling stations; a process recipe corresponding to each of the scheduling stations is determined respectively, wherein the process recipes corresponding to at least two scheduling stations having the same process condition are the same; each of the scheduling stations is sequentially scheduled to perform the process recipe corresponding to the scheduling station based on the scheduling sequence, so as to process the current batch of wafers. In this way, the scheduling stations having the same process condition can be preset with one process recipe, and the process recipe can be directly called in the scheduling station. In this way, the same process recipe in the flow recipe of wafer configuration can be reduced, thereby reducing the storage memory occupied by the process recipe configuration. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 An implementation flowchart of a method for processing wafers provided by the embodiment of the present disclosure is provided;

[0020] Figure 2 An implementation flowchart of another method for processing wafers provided by the embodiment of the present disclosure is provided;

[0021] Figure 3 An implementation flowchart of another method for processing a wafer provided by an embodiment of the present disclosure is shown in FIG. 6;

[0022] Figure 4 An implementation flowchart of another method for processing a wafer provided by an embodiment of the present disclosure is shown in FIG. 6;

[0023] Figure 5 An implementation flowchart of another method for processing a wafer provided by an embodiment of the present disclosure is shown in FIG. 6;

[0024] Figure 6a A structure diagram of a wafer processing device provided by an embodiment of the present disclosure is shown in FIG. 7;

[0025] Figure 6b A structure diagram of another wafer processing device provided by an embodiment of the present disclosure is shown in FIG. 7;

[0026] Figure 6c A structure diagram of another wafer processing device provided by an embodiment of the present disclosure is shown in FIG. 7;

[0027] Figure 7 A structure diagram of a wafer processing device provided by an embodiment of the present disclosure is shown in FIG. 7;

[0028] Figure 8 A structure diagram of a wafer processing system provided by an embodiment of the present disclosure is shown in FIG. 7. DETAILED DESCRIPTION

[0029] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0030] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosure. As such, not all of the features of the actual implementation can be described in detail herein; the actual implementation may, and often does, contain additional features that are not specifically described herein but are within the scope of the present disclosure.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] In the related art, when configuring a flow program, a wafer passes through a large number of scheduling sites, and the conditions of the subprograms executed by the scheduling sites are complex. This makes the cost of configuring the process program higher, and the number of configured process programs larger, resulting in a large amount of storage memory being occupied. In the process of implementing the embodiments of the disclosure, the inventors have found that, when configuring a flow program, there are cases where multiple scheduling sites correspond to the same machine, and the process conditions of multiple scheduling sites are the same, which makes the process programs corresponding to the multiple scheduling sites the same. The same process programs cause the repetition of subprograms in the process program, which occupies a large amount of storage memory.

[0033] On this basis, the embodiments of the disclosure provide a method for processing a wafer, by presetting a process program for scheduling sites with the same process condition, and directly calling the process program in the scheduling site. In this way, the repetition of the same process program in the wafer configuration flow program can be reduced, thereby reducing the storage memory occupied by the process program configuration.

[0034] Figure 1 For the implementation flowchart of the method for processing a wafer provided by the embodiments of the disclosure, reference is made to Figure 1 The embodiments of the disclosure provide a method for processing a wafer, which comprises the following steps S11 to S13:

[0035] Step S11: acquiring a scheduling path of a current batch of wafers; wherein the scheduling path comprises at least one scheduling site for processing the current batch of wafers and a scheduling order between the scheduling sites;

[0036] Step S12: determining a process program corresponding to each of the scheduling sites; wherein the process programs corresponding to at least two scheduling sites with the same process condition are the same;

[0037] Step S13: based on the scheduling order, sequentially scheduling each of the scheduling sites to execute the process program corresponding to the scheduling site, so as to process the current batch of wafers.

[0038] Here, the current batch of wafers refers to wafers scheduled to the machine. At this time, the wafers have not been processed by any process. The scheduling path includes at least one scheduling site for processing the current batch of wafers and a scheduling order between the scheduling sites. It can be understood that the scheduling path is a path of the wafers in the process according to product requirements. The scheduling path includes the scheduling sites that the wafers are scheduled to pass through and the scheduling order of the wafers scheduled to pass through the scheduling sites. For example, the scheduling path Rout1 has N scheduling sites, which can be numbered in sequence as 100, 200,..., and N00. Alternatively, a scheduling site can be understood as a machine that can complete a process corresponding to a film layer of the wafers. For example, a scheduling site can complete any one of photolithography, etching, ion implantation, thin film deposition, chemical mechanical polishing, and the like corresponding to a film layer of the wafers. For another example, the photolithography can include processes such as glue coating, baking, developing, hardening, or exposure. It can be understood that in the entire scheduling path, the multiple scheduling sites corresponding to the multiple sub-programs can correspond to the same machine. For example, the multiple scheduling sites (for example, scheduling sites numbered 300, 700, and 1500) corresponding to the multiple photolithography process programs can correspond to the same photolithography machine.

[0039] The process program includes process parameters for processing the wafers. It can be understood that for the current batch of wafers, the process conditions used by each scheduled scheduling site and each scheduling site for process processing are determined in advance according to product requirements. Therefore, the process program to be executed by the scheduling site and each scheduling site scheduled to pass through by the current batch of wafers has a corresponding relationship.

[0040] In some embodiments, the above step S12 can include the following step S121:

[0041] Step S121: querying a first matching relationship to determine the process program corresponding to each scheduling site; wherein the first matching relationship represents the corresponding relationship between the scheduling site and the process program.

[0042] Here, the first matching relationship includes the relationship between each scheduling site scheduled to pass through by the wafers and the process program to be executed by each scheduling site. For example, the first matching relationship can be a corresponding relationship between scheduling site identification information and process program identification information, wherein the corresponding scheduling site can be determined according to the scheduling site identification information, and the corresponding process program can be determined according to the process program identification information.

[0043] In some embodiments, the first matching relationship can be a correspondence between the scheduling station number and the process recipe number. For example, the scheduling station 300 corresponding to the current batch of wafers corresponds to a process recipe number of recipe 1, the scheduling station 700 corresponds to a process recipe number of recipe 2, and the scheduling station 1500 corresponds to a process recipe number of recipe 1. Accordingly, querying the first matching relationship to determine the process recipe corresponding to each scheduling station can include: determining the process recipe identification information corresponding to each scheduling station according to the correspondence between the scheduling station identification information and the process recipe identification information, and calling the process recipe corresponding to each scheduling station according to the process recipe identification information.

[0044] It should also be noted that the process recipe corresponding to each scheduling station can be determined when the current batch of wafers is shipped, that is, when the wafers are reserved to the machine and have not yet undergone any process. In addition, the process recipe corresponding to each scheduling station can also be determined when the current batch of wafers reaches each corresponding scheduling station.

[0045] In addition, the process recipes corresponding to at least two scheduling stations with the same process conditions are the same. It can be understood that when multiple scheduling stations correspond to the same machine, the process conditions of multiple scheduling stations are the same, and the process recipes corresponding to the scheduling stations with the same process conditions are the same. In this case, a process recipe is pre-configured for the scheduling stations with the same process recipe. When each scheduling station processes the current batch, the process recipe can be directly called without setting a process recipe for each scheduling station. In this way, the repetition of the same process recipe in the configured process recipe can be reduced, thereby reducing the storage memory occupied by the process recipe configuration. For example, the process recipe corresponding to the scheduling station 300 is recipe 1, and the process recipe corresponding to the scheduling station 1500 is also recipe 1. Only one process recipe of recipe 1 needs to be pre-configured, and recipe 1 can be directly called in the scheduling station 300 and the scheduling station 1500.

[0046] In addition, based on the scheduling sequence, each scheduling station is sequentially scheduled to execute the process recipe corresponding to the scheduling station to process the current batch of wafers. Here, each scheduling station is scheduled according to the scheduling sequence, and each scheduling station executes the process recipe corresponding to the scheduling station. Each scheduling station executes the process recipe corresponding to the scheduling station until all the processes scheduled for the current batch of wafers are completed.

[0047] In the embodiments of the present disclosure, a scheduling path of a current batch of wafers is acquired, the scheduling path including at least one scheduling site for processing the current batch of wafers and a scheduling sequence between the scheduling sites; a process program corresponding to each scheduling site is determined, and the process programs corresponding to at least two scheduling sites with the same process condition are the same; and based on the scheduling sequence, each scheduling site is sequentially scheduled to execute the process program corresponding to the scheduling site, so as to process the current batch of wafers. In this way, the scheduling sites with the same process condition can be preset with a process program, and the process program can be directly called at the scheduling site. In this way, the same process program in the wafer configuration flow can be reduced, thereby reducing the storage memory occupation of the process program configuration.

[0048] Figure 2 An implementation flowchart of another method for processing wafers provided by the embodiments of the present disclosure is shown in FIG. 13. Figure 2 In some embodiments, the method includes steps S11 to S15.

[0049] Step S11: A scheduling path of a current batch of wafers is acquired, the scheduling path including at least one scheduling site for processing the current batch of wafers and a scheduling sequence between the scheduling sites.

[0050] Step S12: A process program corresponding to each scheduling site is determined, and the process programs corresponding to at least two scheduling sites with the same process condition are the same.

[0051] Step S13: Based on the scheduling sequence, each scheduling site is sequentially scheduled to execute the process program corresponding to the scheduling site, so as to process the current batch of wafers.

[0052] Step S14: A detection program corresponding to each scheduling site is determined.

[0053] Step S15: For each scheduling site, after the scheduling site is scheduled to execute the process program corresponding to the scheduling site, the scheduling site is scheduled to execute the detection program corresponding to the scheduling site, so as to detect the current batch of wafers after the process.

[0054] Here, the detection program includes a detection parameter for detecting the wafer after the process treatment. For example, the detection program can be the pattern shape, size, position, test point number, and the like of the corresponding product. Determining the detection program corresponding to each scheduling site, it can be understood that for each scheduling site, after the wafer is processed by the process program, the wafer will also be detected to detect whether the process treatment of the current batch of wafers meets the requirements of the corresponding film layer. For example, after the wafer is coated and developed by the coating and developing machine, the wafer can also be detected by the detection unit. For example, the detection unit can be a WIS (Wafer Inspection System, wafer detection system). When determining the subprogram of the scheduling site, in addition to including the process program corresponding to each scheduling site, the detection program of the scheduling site can also be included. In actual application, for different scheduling sites of the same machine, there are often the same process conditions and different detection programs. That is, for different scheduling sites of the same machine, there are often the same corresponding process programs and different detection programs. For example, the coating and developing machine for photolithography processing, the wafer has the same film layer processing conditions, such as photoresist, film thickness, cold and hot plate temperature, rotation speed, etc. The detection conditions are different. It should be noted that determining the detection program corresponding to each scheduling site can be determined in sequence when the current batch of wafers is shipped, or the detection program corresponding to each scheduling site can be determined when the current batch of wafers reaches each corresponding scheduling site.

[0055] In the embodiments of the present disclosure, by respectively determining the detection program corresponding to each scheduling site and the process program corresponding to each scheduling site, the same process program and different detection program of multiple scheduling sites can be provided to reduce the memory occupation of the machine by the process program configuration. For example, the process program and the detection program are separated, one process program and multiple detection programs are pre-configured, and the corresponding process program and detection program are determined for each scheduling site. Therefore, multiple repeated process programs and corresponding detection programs do not need to be configured in the flow program of each batch of wafers. In this way, the repetition of the same process program of different scheduling sites can be reduced, and the storage memory occupied by the process program can be further reduced.

[0056] For how to determine the detection program corresponding to each scheduling site, in some embodiments, the above step S14 includes the following step S141:

[0057] Step S141: querying a second matching relationship to determine the detection program corresponding to each scheduling site; wherein the second matching relationship represents the corresponding relationship between the scheduling site and the detection program.

[0058] Here, the second matching relationship includes a relationship between each scheduling station that the wafer is scheduled to pass through and a detection program to be executed at each scheduling station. For example, the second matching relationship can be a correspondence relationship including scheduling station identification information and detection program identification information.

[0059] In some embodiments, the second matching relationship can be a correspondence relationship between scheduling station numbers and detection program numbers. For example, the scheduling station 300 through which the current batch of wafers passes corresponds to a detection program number WIS recipe 1 and a process program number recipe 1, and the scheduling station 1500 corresponds to a detection program number WIS recipe 3 and a process program number recipe 1. Accordingly, by querying the second matching relationship, the detection program corresponding to each scheduling station can be determined, for example, according to the correspondence relationship between the scheduling station identification information and the detection program identification information, the detection program identification information corresponding to each scheduling station is determined, and the detection program corresponding to the detection program identification information is called according to the detection program identification information.

[0060] In the embodiments of the present disclosure, by querying the second matching relationship, the detection program corresponding to each scheduling station can be directly determined. The correspondence relationship between the detection program and the scheduling station is determined through the second matching relationship, so that the detection program corresponding to the same scheduling station is determined separately from the process program corresponding to the same scheduling station, and it is not necessary to configure multiple repeated process programs and corresponding detection programs in the flow program of each batch of wafers. In this way, the repetition of the same process program in different scheduling stations can be reduced, and the storage memory occupied by the process program can be further reduced.

[0061] In addition, for each scheduling station, after scheduling the scheduling station to execute the process program corresponding to the scheduling station, the scheduling station is scheduled to execute the detection program corresponding to the scheduling station to perform detection processing on the current batch of wafers after the process processing. Scheduling the scheduling station to execute the detection program corresponding to the scheduling station is performed after scheduling the scheduling station to execute the process program corresponding to the scheduling station to determine whether the process performed by the current batch of wafers at the scheduling station meets the requirements for preparing the corresponding product.

[0062] Figure 3 An implementation flowchart of another wafer processing method provided by the embodiments of the present disclosure is shown in FIG. 6. Figure 3 In some embodiments, the method includes steps S11 to S151.

[0063] Step S11: Obtain a scheduling path of a current batch of wafers; wherein the scheduling path includes at least one scheduling station for processing the current batch of wafers and a scheduling order between each scheduling station.

[0064] Step S12: determining a process program corresponding to each of the scheduling stations; wherein the process programs corresponding to at least two scheduling stations having the same process condition are the same;

[0065] Step S13: based on the scheduling sequence, sequentially scheduling each of the scheduling stations to execute the process program corresponding to the scheduling station to process the current batch of wafers.

[0066] Step S14: determining a detection program corresponding to each of the scheduling stations;

[0067] Step S16: determining a target detection ratio corresponding to each of the scheduling stations;

[0068] Step S151: based on the target detection ratio corresponding to the scheduling station, scheduling the scheduling station to execute the detection program corresponding to the scheduling station.

[0069] Here, determining the target detection ratio corresponding to each of the scheduling stations can be understood as that each of the scheduling stations will perform detection processing on the wafers after processing the wafers. In actual application, different batches of wafers flowing through the same scheduling station will be sampled and detected. It can be understood that the target detection ratio is a preset ratio of different batches of wafers being detected after being processed by the same scheduling station.

[0070] For how to determine the target detection ratio corresponding to the scheduling station, in some embodiments, the above step S16 includes step S161:

[0071] Step S161: querying a third matching relationship to determine the target detection ratio corresponding to each of the scheduling stations; wherein the third matching relationship represents a corresponding relationship between the scheduling station and the target detection ratio.

[0072] Here, the third matching relationship includes the relationship between the target detection ratio of each scheduling station and each scheduling station that the wafer is scheduled to pass through.

[0073] In some embodiments, the third matching relationship can be a corresponding relationship between the scheduling station identification information and the target detection ratio. For example, the detection ratio corresponding to the scheduling station 300 is 50%, the detection ratio corresponding to the scheduling station 700 is 100%, and the detection ratio corresponding to the scheduling station 1500 is 50%.

[0074] The above step S15 includes step S151:

[0075] Step S151: based on the target detection ratio corresponding to the scheduling station, scheduling the scheduling station to execute the detection program corresponding to the scheduling station.

[0076] Here, after determining the target detection ratio corresponding to each scheduling site, whether detection processing is performed at a scheduling site is determined according to the target detection ratio of the scheduling site after the current wafer flows to the scheduling site. In sequence of the scheduling sites, whether detection processing is performed on the current batch of wafers at each scheduling site is determined in sequence until the wafer flows out of the last scheduling site, the processing of each film layer of the current batch of wafers is completed, and each film layer meeting the product requirements is formed.

[0077] Figure 4 An implementation flowchart of another method for processing wafers provided by an embodiment of the present disclosure is shown in FIG. 13. Referring to FIG. 13, the method includes steps S11 to S18. Figure 4 In some embodiments, the method further includes steps S11 to S18.

[0078] Step S11: Obtain a scheduling path of a current batch of wafers; wherein the scheduling path includes at least one scheduling site for processing the current batch of wafers and a scheduling sequence between the scheduling sites.

[0079] Step S12: Determine a process recipe corresponding to each scheduling site, respectively; wherein the process recipes corresponding to at least two scheduling sites with the same process conditions are the same.

[0080] Step S13: In sequence of the scheduling sequence, schedule each scheduling site to execute the process recipe corresponding to the scheduling site to process the current batch of wafers.

[0081] Step S14: Determine a detection recipe corresponding to each scheduling site.

[0082] Step S16: Determine a target detection ratio corresponding to each scheduling site.

[0083] Step S151: Schedule each scheduling site to execute the detection recipe corresponding to the scheduling site based on the target detection ratio corresponding to the scheduling site.

[0084] Step S17: For each scheduling site, obtain a first waiting time consumed for detection processing of at least one batch of historical batch of wafers at the scheduling site, and update the target detection ratio corresponding to the scheduling site based on the first waiting time.

[0085] Step S18: Update the third matching relationship based on the updated target detection ratio corresponding to at least one scheduling site.

[0086] Here, the first waiting duration is a waiting duration of the historical batch of wafers at a dispatch station for detection processing. For example, the first waiting duration can be a waiting duration of the historical batch of wafers after a process unit in a dispatch station completes process processing to a detection unit in the dispatch station. The first waiting duration can be used to represent whether the detection unit is a bottleneck unit of the throughput. For example, when the first waiting duration is greater than a preset threshold, it represents that the detection unit is a bottleneck unit of the throughput. When the first waiting duration is less than the preset threshold, it represents that the detection unit does not affect the wafer processing throughput. It can be understood that when the first waiting duration is less than the preset threshold, it can reflect that the detection unit and the process unit have similar or the same processing time, and it can also reflect that the detection unit has much less detection processing time than the process unit.

[0087] In some other embodiments, the parameter representing that the detection unit is a bottleneck of the throughput can also be: for each of the dispatch stations, a first number of wafers waiting between the process unit and the detection unit of the historical batch of wafers. For example, when the first number of wafers is greater than a preset number, it represents that the detection unit is a bottleneck unit of the throughput. Therefore, the target detection ratio corresponding to the dispatch station can be reduced when the first number of wafers corresponding to the dispatch station is greater than the preset number, and the target detection ratio corresponding to the dispatch station can be increased when the first number of wafers corresponding to the dispatch station is less than or equal to the preset number.

[0088] Based on the first waiting duration, the target detection ratio corresponding to the dispatch station is updated. According to the first waiting duration, the target detection ratio corresponding to the dispatch station for the current batch of wafers is adjusted. In this way, the duration of the current batch of wafers passing through the dispatch station can be optimized.

[0089] For how to update the target detection ratio corresponding to the dispatch station based on the first waiting duration, in some embodiments, the above step S17 includes steps S171 to S172:

[0090] Step S171: When the first waiting duration is greater than a first duration threshold, the target detection ratio corresponding to the dispatch station is reduced.

[0091] Step S172: When the first waiting duration is less than or equal to a second duration threshold, the target detection ratio corresponding to the dispatch station is increased, and the second duration threshold is not more than the first duration threshold.

[0092] Here, the first waiting time greater than the first time threshold indicates that the detection unit in the scheduling site is a capacity bottleneck unit. When the first waiting time is greater than the first time threshold, the target detection ratio corresponding to the scheduling site is reduced. For example, the first time threshold is 15s, and when the first waiting time consumed from the end of wafer process to the entry into the detection unit is greater than 15s, the target detection ratio corresponding to the scheduling site is reduced. The first waiting time less than or greater than the second time threshold indicates that the detection unit in the scheduling site has sufficient machine hours for detection processing, and the process unit is a capacity bottleneck unit. Reducing the target detection ratio can reduce the machine hours of the detection unit for detection processing. Thus, when the detection unit is a bottleneck of wafer processing capacity, the total wafer processing capacity is improved.

[0093] In some other embodiments, the capacity of the detection unit as a capacity bottleneck unit can also be improved by optimizing the detection program to reduce the time of the detection unit in the scheduling site for detection processing. For example, the number of detection points in the detection program can be reduced, and the whole wafer detection is adjusted to spot detection; or the number of detection points of spot detection is reduced.

[0094] When the first waiting time is less than or greater than the second time threshold, the target detection ratio corresponding to the scheduling site is increased. For example, the second time threshold is 10s, and when the second waiting time consumed from the end of wafer process to the entry into the detection unit is less than 10s, the target detection ratio corresponding to the scheduling site is increased. Increasing the target detection ratio can reduce the machine hour difference between the detection unit and the process unit, thereby increasing the number of wafers for detection processing by the detection unit in a period of time and improving the utilization rate of the detection unit.

[0095] It should be noted that the first waiting time is between the second time threshold and the first time threshold, indicating that the machine hour difference between the detection unit in the scheduling site for detection processing and the process unit for process processing is reasonable. The original target detection ratio can be used for the current batch of wafers, and the target detection ratio does not need to be adjusted. Here, the second time threshold and the first time threshold can be the same or the second time threshold can be less than the first time threshold.

[0096] In the embodiments of the present disclosure, the first waiting time is compared with the first time threshold and the second time threshold respectively, and the target detection ratio corresponding to the scheduling site is updated. In this way, the machine hour difference between the detection unit and the process unit in each scheduling site can be optimized. On the one hand, optimizing the machine hour difference between the detection unit and the process unit can improve the total wafer processing capacity when the detection unit is a bottleneck of wafer processing capacity. On the one hand, optimizing the machine hour difference between the detection unit and the process unit can improve the utilization rate of the detection unit and ensure that the wafers are detected at the maximum ratio to ensure the performance requirements of each film layer of the wafers.

[0097] Further, the third matching relationship is updated based on the updated target detection ratio corresponding to at least one of the scheduling stations. Here, the third matching relationship contains the relationship between the wafer scheduled to pass through each scheduling station and the target detection ratio of each scheduling station. When the target detection ratio corresponding to a scheduling station changes, the changed target detection ratio is correspondingly updated in the third matching relationship.

[0098] The embodiments of the present disclosure can provide support for directly calling the target detection ratio considering the throughput and sampling rate for subsequent wafer processing by judging whether the detection unit throughput is a throughput bottleneck and adjusting the target detection ratio based on the judgment result and updating the third matching relationship.

[0099] Figure 5 For another implementation flowchart of the method for processing wafers provided by the embodiments of the present disclosure, refer to Figure 5 In some embodiments, the method includes steps S11 to S1512:

[0100] Step S11: Obtain a scheduling path of a current batch of wafers; wherein the scheduling path includes at least one scheduling station for processing the current batch of wafers and a scheduling order between each of the scheduling stations;

[0101] Step S12: Determine a process program corresponding to each of the scheduling stations respectively; wherein the process programs corresponding to at least two scheduling stations with the same process condition are the same;

[0102] Step S13: Based on the scheduling order, sequentially schedule each of the scheduling stations to execute the process program corresponding to the scheduling station to process the current batch of wafers.

[0103] Step S14: Determine a detection program corresponding to each of the scheduling stations;

[0104] Step S16: Determine a target detection ratio corresponding to each of the scheduling stations;

[0105] Step S1511: Obtain a current detection ratio of the scheduling stations for detecting and processing a historical batch of wafers;

[0106] Step S1512: Based on the target detection ratio and the current detection ratio, schedule the scheduling stations to execute the detection program corresponding to the scheduling station.

[0107] For how to determine the current detection ratio, in some embodiments, the above step S1511 includes steps S15111 to S15112:

[0108] Step S15111: determining a first calling number of a process program corresponding to the scheduling site and a second calling number of a detection program corresponding to the scheduling site;

[0109] Step S15112: determining the current detection ratio based on the first calling number and the second calling number.

[0110] Step S1512: scheduling the scheduling site to execute the detection program corresponding to the scheduling site based on the target detection ratio and the current detection ratio.

[0111] Here, the current detection ratio is a ratio of the historical batch wafers to be detected after being processed by a scheduling site. The current detection ratio of any scheduling site can be determined according to the number of times the process program is called and the number of times the detection program is called.

[0112] Based on the target detection ratio and the current detection ratio, the detection program corresponding to the scheduling site is called to detect the current batch wafers after being processed. For example, according to the size of the target detection ratio and the current detection ratio, it is determined whether the current batch wafers after being processed are detected according to the detection program. Exemplarily, when the current batch wafers are the first batch wafers, the current detection ratio of any scheduling site is zero, and any scheduling site performs detection according to the detection program. When the current batch wafers are the second batch wafers, the size relationship between the current detection ratio and the target detection ratio is compared to determine whether each scheduling site performs detection. If the detection ratio of the current batch wafers is less than or equal to the target detection ratio, the current batch wafers after being processed are detected according to the detection program.

[0113] In some embodiments, the above step S1512 includes step S15121:

[0114] Step S15121: scheduling the scheduling site to execute the detection program corresponding to the scheduling site in the case that the current detection ratio is less than or equal to the target detection ratio.

[0115] Here, in a case that the current detection ratio is less than or equal to the target detection ratio, the current batch of wafers is detected according to the detection program after the process treatment. In some other embodiments, in a case that the current detection ratio of the current batch of wafers is greater than the target detection ratio, the current batch of wafers skips the detection. For example, the target detection ratio of the scheduling site numbered 300 is 50%. When the first batch of wafers is processed, the current detection ratio of the scheduling site is 0, which is less than the target detection ratio 50%, so the first batch of wafers is detected. When the second batch of wafers is processed, the current detection ratio of the scheduling site is 100%, which is greater than the target detection ratio 50%, so the second batch of wafers skips the detection. When the third batch of wafers is processed, the current detection ratio of the scheduling site is 50%, which is equal to the target detection ratio 50%, so the third batch of wafers is detected according to the detection program after the process treatment.

[0116] In the embodiments of the present disclosure, by comparing the current detection ratio and the target detection ratio, it is determined whether the current batch of wafers is detected, so as to ensure the sampling detection of the wafers after the process treatment in each scheduling site, and further determine whether the process treatment in each scheduling site meets the product requirements.

[0117] Figure 6a A schematic structural diagram of a device for processing wafers is provided in the embodiments of the present disclosure, referring to Figure 6a The embodiments of the present disclosure provide a device for processing wafers, which comprises:

[0118] The acquisition module 61 is configured to acquire a scheduling path of a current batch of wafers, wherein the scheduling path comprises at least one scheduling site for processing the current batch of wafers and a scheduling sequence between the scheduling sites.

[0119] The first determination module 62 is configured to determine a process program corresponding to each scheduling site, wherein the process programs corresponding to at least two scheduling sites with the same process condition are the same.

[0120] The first scheduling module 63 is configured to sequentially schedule each scheduling site to execute the process program corresponding to the scheduling site based on the scheduling sequence, so as to process the current batch of wafers.

[0121] Here, in actual application, the acquisition module 61, the first determination module 62 and the first scheduling module 63 can be configured in an EAP (Equipment Automation Program). For example, the EAP acquires a scheduling path sent by MM (Material Management). The EDP determines a process corresponding to each scheduling site respectively, and based on a scheduling sequence, sequentially schedules each scheduling site to execute a process program corresponding to the scheduling site, so as to process the current batch of wafers.

[0122] In some embodiments, the first determination module 62 is further configured to query a first matching relationship to determine the process program corresponding to each scheduling site; wherein the first matching relationship represents a corresponding relationship between the scheduling site and the process program.

[0123] Figure 6b Another device structure schematic diagram for processing wafers is provided for the embodiments of the present disclosure, referring to Figure 6b In some embodiments, the device further comprises:

[0124] The second determination module 64 is configured to determine a detection program corresponding to each scheduling site.

[0125] The second scheduling module 65 is configured to, for each scheduling site, after scheduling the scheduling site to execute the process program corresponding to the scheduling site, schedule the scheduling site to execute a detection program corresponding to the scheduling site, so as to detect the current batch of wafers after process processing.

[0126] In some embodiments, the second determination module 65 is further configured to query a second matching relationship to determine the detection program corresponding to each scheduling site; wherein the second matching relationship represents a corresponding relationship between the scheduling site and the detection program.

[0127] Figure 6c Another device structure schematic diagram for processing wafers is provided for the embodiments of the present disclosure, referring to Figure 6c In some embodiments, the device further comprises:

[0128] The third determination module 66 is configured to determine a target detection ratio corresponding to each scheduling site.

[0129] The second scheduling module 65 is further configured to, based on the target detection ratio corresponding to the scheduling site, schedule the scheduling site to execute the detection program corresponding to the scheduling site, so as to detect the current batch of wafers after process processing.

[0130] In some embodiments, the third determining module 66 is further configured to query a third matching relationship to determine a target detection ratio corresponding to each of the scheduling stations; wherein the third matching relationship represents a corresponding relationship between a scheduling station and a target detection ratio.

[0131] For example, the second determining module and the third determining module can be arranged in a big data system, and the big data system is configured to determine a target detection ratio corresponding to each of the scheduling stations, a detection program, and send the determined target detection ratio corresponding to each of the scheduling stations and the detection program to the second scheduling module. The second scheduling module is configured to schedule each of the scheduling stations to execute the detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station, so as to perform detection processing on the current batch of wafers after process processing.

[0132] In some embodiments, the apparatus further comprises:

[0133] The updating module 67 is configured to, for each of the scheduling stations, acquire a first waiting time consumed by at least one batch of historical batch wafers for detection processing at the scheduling station, and update a target detection ratio corresponding to the scheduling station based on the first waiting time; and update the third matching relationship based on the updated target detection ratio corresponding to at least one of the scheduling stations.

[0134] In some embodiments, the updating module 67 is further configured to, in a case that the first waiting time is greater than a first time threshold, decrease the target detection ratio corresponding to the scheduling station; and in a case that the first waiting time is less than or equal to a second time threshold, increase the target detection ratio corresponding to the scheduling station, wherein the second time threshold is not more than the first time threshold.

[0135] In some embodiments, the second scheduling module 65 is further configured to acquire a current detection ratio of the scheduling station for detection processing on the historical batch wafers; and schedule the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio and the current detection ratio, so as to perform detection processing on the current batch of wafers after process processing.

[0136] In some embodiments, the second scheduling module 65 is further configured to, in a case that the current detection ratio is less than or equal to the target detection ratio, schedule the scheduling station to execute the detection program corresponding to the scheduling station, so as to perform detection processing on the current batch of wafers after process processing.

[0137] In some embodiments, the second scheduling module 65 is further configured to determine a first number of invocations of a process program corresponding to the scheduling site and a second number of invocations of a detection program corresponding to the scheduling site; and determine the current detection rate based on the first number of invocations and the second number of invocations.

[0138] The wafer processing apparatus and the wafer processing method have similar advantages. For technical details not disclosed in the wafer processing apparatus embodiments of the present disclosure, please refer to the descriptions of the wafer processing method embodiments for understanding.

[0139] The wafer processing apparatus provided by the embodiments of the present disclosure includes a processor and a memory for storing a computer program capable of running on the processor,

[0140] When the processor runs the computer program, the processor performs the steps of the method described above.

[0141] The computer storage medium provided by the embodiments of the present disclosure stores a computer program, and the computer program is executed by a processor to implement the steps of the method described above. The computer readable storage medium can be transitory or non-transitory.

[0142] It should be noted that, Figure 7 A structural schematic diagram of a wafer processing apparatus provided by the embodiments of the present disclosure is shown in FIG. 7. Figure 7 As shown in FIG. 7, the wafer processing apparatus 70 includes a processor 71, a communication interface 72 and a memory 73, wherein:

[0143] The processor 71 generally controls the overall operation of the wafer processing apparatus 70.

[0144] The communication interface 72 can enable the wafer processing apparatus 70 to communicate with other terminals or servers through a network.

[0145] The memory 73 is configured to store instructions and applications executable by the processor 71, and can also cache data (for example, image data, audio data, voice communication data and video communication data) to be processed by the processor 71 and modules in the wafer processing apparatus 70. The memory 73 can be implemented by a FLASH or a RAM. The processor 71, the communication interface 72 and the memory 73 can perform data transmission through a bus 74.

[0146] Figure 8 A structural schematic diagram of a wafer processing system provided by the embodiments of the present disclosure is shown in FIG. 8. Figure 8 As shown in FIG. 8, the wafer processing system 800 includes:

[0147] a wafer processing apparatus 70 as described above;

[0148] a processing machine 80, configured to perform a process recipe corresponding to the scheduling station according to the scheduling instruction of the wafer processing apparatus, and process the current batch of wafers.

[0149] It should be noted that the above description of the storage medium, apparatus and system embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and apparatus embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0150] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of the above processes does not mean the order of execution, and the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence number of the above embodiments of the present disclosure is only for description, not representing the advantages and disadvantages of the embodiments.

[0151] It should be noted that in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the process, method, article or device including the element.

[0152] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0153] The units described as separate components above can or can not be physically separate, and the components displayed as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0154] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program executes the steps of the above-mentioned method embodiments when executed; and the foregoing storage medium includes a mobile storage device, a read-only memory (ROM), a magnetic disc or an optical disc, and various storage medium that can store program codes.

[0155] Alternatively, the integrated units of the present disclosure can be stored in a computer readable storage medium if they are implemented in the form of software function modules and sold or used as independent products. Based on this understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for making an electronic device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods described in the embodiments of the present disclosure. The foregoing storage medium includes a mobile storage device, a ROM, a magnetic disc or an optical disc, and various storage medium that can store program codes.

[0156] The above is only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A method of processing a wafer, characterized by, The method comprises: obtaining a scheduling path of a current batch of wafers; wherein the scheduling path comprises at least one scheduling station for processing the current batch of wafers and a scheduling sequence between the scheduling stations; determining a process program corresponding to each of the scheduling stations respectively; wherein the process programs corresponding to at least two scheduling stations with the same process condition are the same, and the scheduling stations with the same process program are pre-configured with one process program; based on the scheduling sequence, sequentially scheduling each of the scheduling stations to execute the process program corresponding to the scheduling station, so as to process the current batch of wafers.

2. The method of claim 1, wherein, The determination of the process program corresponding to each of the scheduling stations respectively comprises: inquiring a first matching relationship to determine the process program corresponding to each of the scheduling stations; wherein the first matching relationship represents the corresponding relationship between the scheduling stations and the process programs.

3. The method of claim 1, wherein, The method further comprises: determining a detection program corresponding to each of the scheduling stations respectively; for each of the scheduling stations, after scheduling the scheduling station to execute the process program corresponding to the scheduling station, scheduling the scheduling station to execute the detection program corresponding to the scheduling station, so as to detect the current batch of wafers after the process.

4. The method of claim 3, wherein, The determination of the detection program corresponding to each of the scheduling stations respectively comprises: inquiring a second matching relationship to determine the detection program corresponding to each of the scheduling stations; wherein the second matching relationship represents the corresponding relationship between the scheduling stations and the detection programs.

5. The method of claim 4, wherein, The method further comprises: determining a target detection ratio corresponding to each of the scheduling stations respectively; The scheduling of the scheduling station to execute the detection program corresponding to the scheduling station to detect the current batch of wafers after the process comprises: based on the target detection ratio corresponding to the scheduling station, scheduling the scheduling station to execute the detection program corresponding to the scheduling station.

6. The method of claim 5, wherein, The determination of the target detection ratio corresponding to each of the scheduling stations respectively comprises: inquiring a third matching relationship to determine the target detection ratio corresponding to each of the scheduling stations; wherein the third matching relationship represents the corresponding relationship between the scheduling stations and the target detection ratios.

7. The method of claim 6, wherein, The method further comprises: for each of the scheduling stations, obtaining a first waiting time consumed by at least one batch of historical batch of wafers in the detection processing at the scheduling station, and updating the target detection ratio corresponding to the scheduling station based on the first waiting time; based on the updated target detection ratio corresponding to at least one of the scheduling stations, updating the third matching relationship.

8. The method of claim 7, wherein, The updating of the target detection ratio corresponding to the scheduling station based on the first waiting time comprises: in the case that the first waiting time is greater than a first time threshold, reducing the target detection ratio corresponding to the scheduling station; in the case that the first waiting time is less than or equal to a second time threshold, increasing the target detection ratio corresponding to the scheduling station, and the second time threshold is not more than the first time threshold.

9. The method of claim 5, wherein, The scheduling the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio corresponding to the scheduling station comprises: obtaining a current detection ratio of the scheduling station in detection processing of historical batches of wafers; scheduling the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio and the current detection ratio.

10. The method of claim 9, wherein, The scheduling the scheduling station to execute the detection program corresponding to the scheduling station based on the target detection ratio and the current detection ratio comprises: scheduling the scheduling station to execute the detection program corresponding to the scheduling station in a case where the current detection ratio is less than or equal to the target detection ratio.

11. The method of claim 9, wherein, The obtaining the current detection ratio of the scheduling station in detection processing of historical batches of wafers comprises: determining a first calling number of a process program corresponding to the scheduling station and a second calling number of a detection program corresponding to the scheduling station; determining the current detection ratio based on the first calling number and the second calling number.

12. An apparatus for processing a wafer, the apparatus comprising: The apparatus comprises: an obtaining module, configured to obtain a scheduling path of a current batch of wafers; wherein the scheduling path comprises at least one scheduling station for processing the current batch of wafers and a scheduling sequence between the scheduling stations; a first determining module, configured to determine a process program corresponding to each of the scheduling stations; wherein process programs corresponding to at least two scheduling stations with the same process condition are the same, and the multiple scheduling stations with the same process program are pre-configured with one process program; a first scheduling module, configured to sequentially schedule each of the scheduling stations to execute the process program corresponding to the scheduling station based on the scheduling sequence, so as to process the current batch of wafers.

13. The apparatus of claim 12, wherein, The apparatus further comprises: a second determining module, configured to determine a detection program corresponding to each of the scheduling stations; a second scheduling module, configured to, for each of the scheduling stations, schedule the scheduling station to execute the detection program corresponding to the scheduling station after scheduling the scheduling station to execute the process program corresponding to the scheduling station, so as to detect the current batch of wafers after process processing.

14. An apparatus for processing a wafer, the apparatus comprising: The device comprises a processor and a memory for storing a computer program capable of running on the processor, wherein the processor is configured to execute the steps of the method of any one of claims 1 to 11 when running the computer program.

15. A computer storage medium having stored thereon a computer program, characterized in that The computer program is executed by the processor to implement the steps of the method of any one of claims 1 to 11.

16. A system for processing a wafer, the system comprising: The system comprises: the device for processing wafers according to claim 14; a processing machine, configured to execute the process program corresponding to the scheduling station according to the scheduling instruction of the device for processing wafers, so as to process the current batch of wafers.

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