Sensitive amplifier and memory chip

Abstract

The application discloses a sensitive amplifier and a storage chip, the sensitive amplifier comprising a pre-charge transistor, a first clamping transistor, a detection unit and a feedback unit, the current flowing through the pre-charge transistor is detected by the detection unit and converted into a corresponding voltage, then the feedback unit outputs a lower voltage according to the voltage, and the current flowing through the first clamping transistor is controlled, so that the peak value of the current flowing through the first clamping transistor can be weakened, and the technical problem that the peak value of the current charging the total bit line or the bit line is large is solved; moreover, the detection unit also plays a voltage dividing role, and a larger power supply voltage can be borne during the pre-charge process, so that the allowable use range of the power supply voltage is expanded.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a sensitive amplifier and a storage chip. Background Technology

[0002] In memory chips or memories, sensitive amplifiers are used to read stored data from memory cells. However, traditional sensitive amplifiers cannot effectively control the peak current of the total bit line or bit line charging in accordance with the power supply voltage, resulting in a narrow range of usable power supply voltages; at the same time, it also leads to a large peak current when charging the total bit line or bit line. Summary of the Invention

[0003] This application provides a sensitive amplifier and a memory chip to alleviate the technical problems of a small allowable range of power supply voltage and a large peak current for charging the total bit line or bit line.

[0004] In a first aspect, this application provides a sensitive amplifier, which includes a pre-charge transistor, a first clamping transistor, a detection unit, and a feedback unit. The first terminal of the pre-charge transistor is electrically connected to a power supply terminal, and the control terminal of the pre-charge transistor is electrically connected to a pre-charge control terminal. The first terminal of the first clamping transistor is electrically connected to the second terminal of the pre-charge transistor, and the second terminal of the first clamping transistor is electrically connected to a bit line. The detection unit is coupled between the power supply terminal and the first terminal of the pre-charge transistor, and is used to detect the current flowing through the pre-charge transistor and convert it into a corresponding voltage. The input terminal of the feedback unit is electrically connected to the first terminal of the pre-charge transistor, and the output terminal of the feedback unit is electrically connected to the control terminal of the first clamping transistor, and is used to reduce the peak current flowing through the first clamping transistor.

[0005] In some embodiments, the detection unit includes a detection resistor, one end of which is electrically connected to a power supply terminal, and the other end of which is electrically connected to the first terminal of the precharge transistor and the input terminal of the feedback unit.

[0006] In some embodiments, the detection unit includes a detection transistor, the first terminal of which is electrically connected to a power supply terminal, the control terminal of which is electrically connected to the second terminal of which is connected to the first terminal of which is a precharge transistor, and the detection transistor is a P-channel transistor.

[0007] In some embodiments, the feedback unit includes a first transistor, a second transistor, and a third transistor. The first terminal of the first transistor is electrically connected to a power supply terminal, and the control terminal of the first transistor is electrically connected to the other end of a detection resistor or the second terminal of a detection transistor. The first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the control terminal of the second transistor, and the second terminal of the second transistor is electrically connected to a ground terminal. The first terminal of the third transistor is electrically connected to the control terminal of the first clamping transistor, the second terminal of the third transistor is electrically connected to a ground terminal, and the control terminal of the third transistor is electrically connected to the second terminal of the first transistor.

[0008] In some embodiments, the first transistor is a P-channel transistor; the second transistor and the third transistor are both N-channel transistors.

[0009] In some embodiments, the ratio of the current flowing through the first transistor to the current flowing through the third transistor is 1:M, where M is a positive number.

[0010] In some embodiments, the sensitive amplifier further includes a fourth transistor and a second clamping transistor. The first terminal of the fourth transistor is electrically connected to a power supply terminal, and the control terminal of the fourth transistor is electrically connected to a first bias voltage terminal. The fourth transistor is a P-channel transistor. The first terminal of the second clamping transistor is electrically connected to the second terminal of the fourth transistor and the control terminal of the first clamping transistor. The second terminal of the second clamping transistor is electrically connected to a ground terminal, and the control terminal of the second clamping transistor is electrically connected to the second terminal of the first clamping transistor.

[0011] In some embodiments, the sensitive amplifier further includes a fifth transistor, a sixth transistor, a seventh transistor, and a buffer. The first terminal of the fifth transistor is electrically connected to the power supply terminal, the control terminal of the fifth transistor is electrically connected to the second bias voltage terminal, and the second terminal of the fifth transistor is electrically connected to the second terminal of the pre-charge transistor. The first terminal of the sixth transistor is electrically connected to the power supply terminal, the control terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor, and the sixth transistor is a P-channel transistor. The first terminal of the seventh transistor is electrically connected to the second terminal of the sixth transistor, the control terminal of the seventh transistor is electrically connected to the third bias voltage terminal, and the second terminal of the seventh transistor is electrically connected to the ground terminal. The input terminal of the buffer is electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor, and the output terminal of the buffer is used to output readout data.

[0012] Secondly, this application provides a memory chip that includes the sensitive amplifier described in at least one of the above embodiments, and the memory chip is an XOR flash memory.

[0013] In some embodiments, the memory chip further includes a decoding transistor and a storage transistor. The first terminal of the decoding transistor is electrically connected to the total bit line, the control terminal of the decoding transistor is electrically connected to the decoding select terminal, and the second terminal of the decoding transistor is electrically connected to the bit line. The first terminal of the storage transistor is electrically connected to the bit line, the control terminal of the storage transistor is electrically connected to the word line, and the second terminal of the storage transistor is electrically connected to the ground terminal.

[0014] The sensitive amplifier and memory chip provided in this application detect the current flowing through the pre-charge transistor through the detection unit and convert it into a corresponding voltage. Then, the feedback unit outputs a lower voltage based on this voltage, thereby controlling the current flowing through the first clamping transistor. This not only reduces the peak current flowing through the first clamping transistor and alleviates the technical problem of a large peak current for charging the total bit line or bit line, but the detection unit also acts as a voltage divider, allowing it to withstand a larger power supply voltage during the pre-charge process, thus expanding the permissible range of the power supply voltage. Attached Figure Description

[0015] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0016] Figure 1 A circuit diagram of a sensitive amplifier provided in an embodiment of this application.

[0017] Figure 2 Another circuit diagram of the sensitive amplifier provided in the embodiments of this application.

[0018] Figure 3 for Figure 1 , Figure 2 The diagram shows how some parameters of the sensitive amplifier change over time. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] In view of the aforementioned technical problems of the limited allowable range of power supply voltage and the large peak current for charging the total bit line DBL or bit line BL in the sensitive amplifier, this embodiment provides a sensitive amplifier. Please refer to [link to relevant documentation]. Figures 1 to 3 ,like Figure 1 , Figure 2As shown, the sensitive amplifier includes a precharge transistor M1, a first clamping transistor M2, a detection unit 10, and a feedback unit 20. The first terminal of the precharge transistor M1 is electrically connected to the power supply terminal VCC, and the control terminal of the precharge transistor M1 is electrically connected to the precharge control terminal PREb. The first terminal of the first clamping transistor M2 is electrically connected to the second terminal of the precharge transistor M1, and the second terminal of the first clamping transistor M2 is electrically connected to the total bit line DBL. The detection unit 10 is coupled between the power supply terminal VCC and the first terminal of the precharge transistor M1, and is used to detect the current flowing through the precharge transistor M1 and convert it into a corresponding voltage. The input terminal of the feedback unit 20 is electrically connected to the first terminal of the precharge transistor M1, and the output terminal of the feedback unit 20 is electrically connected to the control terminal of the first clamping transistor M2, and is used to reduce the peak current flowing through the first clamping transistor M2.

[0021] It is understood that the sensitive amplifier provided in this embodiment detects the current flowing through the pre-charge transistor M1 through the detection unit 10 and converts it into a corresponding voltage. Then, the feedback unit 20 outputs a lower voltage based on this voltage, thereby controlling the current flowing through the first clamping transistor M2. This not only reduces the peak current flowing through the first clamping transistor M2, alleviating the technical problem of a large peak current when charging the total bit line DBL or bit line BL, but also the detection unit 10 also acts as a voltage divider, allowing it to withstand a larger power supply voltage during the pre-charge process, thereby expanding the allowable range of the power supply voltage.

[0022] It should be noted that before the addition of the detection unit 10, the voltage at the first terminal of the precharge transistor M1 is almost equal to the voltage at the power supply terminal VCC, ignoring the voltage drop of the connecting wire between them. However, after the addition of the detection unit 10, due to the resistance of the detection unit 10 itself, the voltage at the first terminal of the precharge transistor M1 is equal to the voltage at the power supply terminal VCC minus the voltage drop of the detection unit 10. When the voltage at the power supply terminal VCC increases, the resistance of the detection unit 10 remains basically unchanged, while the current flowing through the detection unit 10 increases accordingly, and the voltage drop of the detection unit 10 also increases accordingly, which expands the usable range of the power supply voltage. At the same time, as the power supply voltage increases, the potential at point A increases accordingly, the potential at the output terminal of the feedback unit 20, i.e., point B, decreases, and the conduction angle of the first clamping transistor M2 becomes smaller. This weakens the current or current peak flowing through the first clamping transistor M2, allowing the precharge process to withstand a larger power supply voltage, which further expands the usable range of the power supply voltage.

[0023] In one embodiment, such as Figure 1 As shown, the detection unit 10 includes a detection resistor R1. One end of the detection resistor R1 is electrically connected to the power supply terminal VCC, and the other end of the detection resistor R1 is electrically connected to the first terminal of the precharge transistor M1 and the input terminal of the feedback unit 20.

[0024] It should be noted that in this embodiment, the detection unit 10 is constructed as a detection resistor R1, which not only simplifies the structure of the detection unit 10 but also facilitates its implementation in an integrated circuit. Simultaneously, this detection resistor R1 also increases the voltage drop across the detection unit 10 as the voltage at the power supply terminal VCC increases, thus expanding the usable range of the power supply voltage. Furthermore, the feedback unit 20 can reduce the current or current peak flowing through the first clamping transistor M2 during the increase of the power supply voltage, allowing the pre-charging process to withstand a higher power supply voltage, further expanding the usable range of the power supply voltage.

[0025] In one embodiment, such as Figure 2 As shown, the detection unit 10 includes a detection transistor T1. The first terminal of the detection transistor T1 is electrically connected to the power supply terminal VCC. The control terminal of the detection transistor T1 is electrically connected to the second terminal of the detection transistor T1 and the first terminal of the precharge transistor M1. The detection transistor T1 is a P-channel transistor.

[0026] Specifically, the source of the detection transistor T1 is electrically connected to the power supply terminal VCC, and the drain of the detection transistor T1 is electrically connected to the gate of the detection transistor T1 and the first terminal of the precharge transistor M1.

[0027] It should be noted that in this embodiment, the detection unit 10 is constructed as a P-channel detection transistor T1, which also simplifies the structure of the detection unit 10 and facilitates its implementation in an integrated circuit. Simultaneously, when the voltage at the power supply terminal VCC increases, the resistance of the detection transistor T1 remains essentially unchanged, while the current flowing through it increases, and the voltage drop across it also increases, thus expanding the usable range of the power supply voltage. Furthermore, the feedback unit 20 can reduce the current or current peak flowing through the first clamping transistor M2 during the increase in power supply voltage, allowing the pre-charging process to withstand a higher power supply voltage, further expanding the usable range of the power supply voltage.

[0028] In one embodiment, the feedback unit 20 includes a first transistor M3, a second transistor M4, and a third transistor M5. The first terminal of the first transistor M3 is electrically connected to the power supply terminal VCC, and the control terminal of the first transistor M3 is electrically connected to the other end of the detection resistor R1 or the second terminal of the detection transistor T1. The first terminal of the second transistor M4 is electrically connected to the second terminal of the first transistor M3 and the control terminal of the second transistor M4, and the second terminal of the second transistor M4 is electrically connected to the ground terminal GND. The first terminal of the third transistor M5 is electrically connected to the control terminal of the first clamping transistor M2, the second terminal of the third transistor M5 is electrically connected to the ground terminal GND, and the control terminal of the third transistor M5 is electrically connected to the second terminal of the first transistor M3.

[0029] Among them, the first transistor M3 is a P-channel transistor; the second transistor M4 and the third transistor M5 are both N-channel transistors.

[0030] The ratio of the current Ifb1 flowing through the first transistor M3 to the current Ifb2 flowing through the third transistor M5 is 1:M, where M is a positive number. Preferably, M is a positive number greater than 1, which results in a larger current Ifb2 flowing through the third transistor M5. This allows for faster discharge of charge at point B, increasing the rate of potential decrease at point B, and thus more effectively reducing the current or peak current flowing through the first clamping transistor M2.

[0031] It should be noted that after adding the detection unit 10, the voltage drop across the power supply VCC terminal, compared to the power supply voltage, will cause the potential at point A to decrease. This will increase the current Ifb1 flowing through the first transistor M3. Due to the proportional relationship between the current Ifb1 flowing through the first transistor M3 and the current Ifb2 flowing through the third transistor M5, the current Ifb2 flowing through the third transistor M5 will also increase. With the current Ibias flowing through the fourth transistor M6 remaining constant, more charge flows out from point B, causing the potential at point B to decrease. This will decrease the current flowing through the first clamping transistor M2. Due to the limited conduction angle of the first clamping transistor M2, the peak current flowing through it will be reduced or weakened before it can pass through. This alleviates the technical problem of large peak currents when charging the total bit line DBL or bit line BL.

[0032] Moreover, when the power supply voltage is low, the node where the second electrode of the pre-charge transistor M1 is located can still be charged through the pre-charge transistor M1, thereby meeting the charging speed requirements at low voltage.

[0033] Among them, the control electrode of the first transistor M3 can be used as the input terminal of the feedback unit 20, and the first electrode of the third transistor M5 can be used as the output terminal of the feedback unit 20, i.e., point B.

[0034] In one embodiment, the sensitive amplifier further includes a fourth transistor M6 and a second clamping transistor M7. The first terminal of the fourth transistor M6 is electrically connected to the power supply terminal VCC, and the control terminal of the fourth transistor M6 is electrically connected to the first bias voltage terminal BIASP. The fourth transistor M6 is a P-channel transistor. The first terminal of the second clamping transistor M7 is electrically connected to the second terminal of the fourth transistor M6 and the control terminal of the first clamping transistor M2. The second terminal of the second clamping transistor M7 is electrically connected to the ground terminal GND, and the control terminal of the second clamping transistor M7 is electrically connected to the second terminal of the first clamping transistor M2.

[0035] It should be noted that the second clamping transistor M7 can be an N-channel transistor. The conduction of the fourth transistor M6 can raise the potential at point B to the potential of the power supply terminal VCC. The fourth transistor M6 can also be an N-channel transistor, by adjusting the potential of the first bias voltage terminal BIASP accordingly. The fourth transistor M6, the second clamping transistor M7, and the first clamping transistor M2 can clamp the potential at point B. For example, if the potential of the total bit line DBL increases, the current flowing through the second clamping transistor M7 increases, and the potential at point B decreases. Conversely, if the potential flowing through the first clamping transistor M2 decreases, the potential of the total bit line DBL decreases, the current flowing through the second clamping transistor M7 decreases, and the potential at point B increases. This closed-loop feedback can stabilize the potential at point B.

[0036] In one embodiment, the sensitive amplifier further includes a fifth transistor M8, a sixth transistor M9, a seventh transistor M10, and a buffer 30. The first terminal of the fifth transistor M8 is electrically connected to the power supply terminal VCC, the control terminal of the fifth transistor M8 is electrically connected to the second bias voltage terminal BIAS_REF, and the second terminal of the fifth transistor M8 is electrically connected to the second terminal of the precharge transistor M1. The first terminal of the sixth transistor M9 is electrically connected to the power supply terminal VCC, the control terminal of the sixth transistor M9 is electrically connected to the second terminal of the fifth transistor M8, and the sixth transistor M9 is a P-channel transistor. The first terminal of the seventh transistor M10 is electrically connected to the second terminal of the sixth transistor M9, the control terminal of the seventh transistor M10 is electrically connected to the third bias voltage terminal BIASN, and the second terminal of the seventh transistor M10 is electrically connected to the ground terminal GND. The input terminal of the buffer 30 is electrically connected to the second terminal of the sixth transistor M9 and the first terminal of the seventh transistor M10, and the output terminal of the buffer 30 is used to output readout data DOUT.

[0037] It should be noted that the fifth transistor M8 can be, but is not limited to, a P-channel transistor or an N-channel transistor, used to provide the reference current Iref for the sensitive amplifier. During sensitive amplification, when the reference current Iref is greater than the current Icell of the storage cell, the control voltage of the sixth transistor M9 remains high, thus preventing the sixth transistor M9 from conducting, and the output DOUT is "0". During sensitive amplification, when the reference current Iref is less than the current Icell of the storage cell, the control voltage of the sixth transistor M9 will gradually decrease over time, thus gradually turning on the sixth transistor M9, at which point the output DOUT is "1".

[0038] In this embodiment, the sixth transistor M9 and the seventh transistor M10 can be used to construct a single-phase amplifier. The control terminal of the sixth transistor M9 can serve as the input terminal of the single-phase amplifier, and the connection node between the second terminal of the sixth transistor M9 and the first terminal of the seventh transistor M10 can serve as the output terminal of the single-phase amplifier. The buffer 30 is used to further amplify and shape the output readout data DOUT as needed, thereby facilitating the logic output and control of subsequent circuits.

[0039] In one embodiment, this embodiment provides a memory chip that includes the sensitive amplifier described in at least one of the above embodiments, and the memory chip is an XOR flash memory.

[0040] It is understood that the memory chip provided in this embodiment detects the current flowing through the pre-charge transistor M1 through the detection unit 10 and converts it into a corresponding voltage. Then, the feedback unit 20 outputs a lower voltage based on this voltage, thereby controlling the current flowing through the first clamping transistor M2. This not only reduces the peak current flowing through the first clamping transistor M2, alleviating the technical problem of a large peak current when charging the total bit line DBL or bit line BL, but also the detection unit 10 also acts as a voltage divider, allowing it to withstand a larger power supply voltage during the pre-charge process, thereby expanding the allowable range of the power supply voltage.

[0041] In one embodiment, the memory chip further includes a decoding transistor M11 and a storage transistor Mst. The first terminal of the decoding transistor M11 is electrically connected to the total bit line DBL, the control terminal of the decoding transistor M11 is electrically connected to the decoding selection terminal Y_MUX, and the second terminal of the decoding transistor M11 is electrically connected to the bit line BL. The first terminal of the storage transistor Mst is electrically connected to the bit line BL, the control terminal of the storage transistor Mst is electrically connected to the word line WL, and the second terminal of the storage transistor Mst is electrically connected to the ground terminal GND.

[0042] It should be noted that the decoding transistor M11 can be, but is not limited to, an N-channel transistor or a P-channel transistor, used to selectively connect the total bit line DBL to the corresponding bit line BL.

[0043] It should be noted that the current flowing through the storage transistor Mst is Icell. During the process of reading data stored in the storage transistor Mst, firstly, the precharge transistor M1 is turned on, precharging the potential of its second electrode to a specified potential (this specified potential is the potential of the power supply terminal VCC minus the voltage drop of the detection unit 10). Simultaneously, the total bit line DBL and the corresponding bit line BL are also precharged to the clamping voltage of the specified point. After precharging is complete, the precharge transistor M1 is turned off. During sensitive amplification, when the reference current Iref is greater than the current Icell of the storage transistor Mst, the control electrode voltage of the sixth transistor M9 will remain at a high potential. This high potential is insufficient to turn on the sixth transistor M9, at which point the seventh transistor M10 is turned on, and the read data DOUT output through the buffer 30 is "0". When the reference current Iref is less than the storage cell Icell, the control voltage of the sixth transistor M9 will decrease over time. When the voltage drops to a level that allows the sixth transistor M9 to conduct, as the current of the sixth transistor M9 increases to a level greater than the current of the seventh transistor M10, the read data DOUT output by the buffer 30 will be "1".

[0044] One of the storage transistors, Mst, can serve as a storage unit.

[0045] In one embodiment, at least one of the transistors described above may be, but is not limited to, a P-channel transistor or an N-channel thin-film transistor.

[0046] It should be noted that in the above embodiments, the first electrode can be either the source or the drain, the second electrode can be either the source or the drain, and the control electrode can be the gate; or, the first electrode can be either the collector or the emitter, the second electrode can be either the collector or the emitter, and the control electrode can be the base.

[0047] In the above embodiments, each transistor may also be a bipolar junction transistor or a field-effect transistor.

[0048] In summary, before adding the detection unit 10, the higher the power supply voltage, the larger the peak current flowing through the pre-charge transistor M1. After adding the detection unit 10, the larger the charging current Ipre flowing through the pre-charge transistor M1, the lower the voltage at point A, resulting in larger currents in Ifb1 and Ifb2, and a decrease in the voltage at point B. This, in turn, limits the charging current Ipre flowing through the total bit line DBL or bit line BL through the first clamping transistor M2. In other words, by adjusting the detection resistor R1 and the ratio of Ifb1 and Ifb2, the charging current Ipre is controlled within a certain range, while still meeting certain speed requirements at low voltage.

[0049] Specifically, such as Figure 3 As shown, VPREb represents the potential change curve of the pre-charge control terminal PREb. VA represents the potential change curve at point A. VB represents the potential change curve at point B. IM2 represents the change curve of the charging current Ipre flowing through the first clamping transistor M2. Figure 3 As shown in the dashed box, when the potential of the precharge control terminal PREb is low, the precharge transistor M1 is in the on state. Due to the instantaneous increase in the charging current flowing through the precharge transistor M1, the potential VA at point A will decrease in a short time (see the first trough of VA), causing the potential VB at point B to have the first trough, thereby weakening or eliminating the peak value of IM2. It can be seen that as time goes on, the peak value of IM2 will be continuously weakened or eliminated, thereby reducing the fluctuation range of IM2.

[0050] After adding the detection unit 10, the peak value of the charging current Ipre can be controlled at high voltage or FF corner (Fast nmos Fast pmos, where the threshold voltages of nmos and pmos are relatively low), while maintaining a certain charging current Ipre at low voltage or SS corner (Slow nmos Slow pmos, where the threshold voltages of nmos and pmos are relatively high), thereby meeting the charging speed requirements under low voltage.

[0051] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0052] The above provides a detailed description of the sensitive amplifier and memory chip provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A sensitive amplifier, characterized in that, The sensitive amplifier includes: A precharge transistor, wherein the first terminal of the precharge transistor is electrically connected to the power supply terminal, and the control terminal of the precharge transistor is electrically connected to the precharge control terminal; A first clamping transistor, wherein the first terminal of the first clamping transistor is electrically connected to the second terminal of the precharge transistor, and the second terminal of the first clamping transistor is electrically connected to the total bit line; A detection unit, coupled between the power supply terminal and the first terminal of the pre-charge transistor, is used to detect the current flowing through the pre-charge transistor and convert it into a corresponding voltage; and The feedback unit has its input terminal electrically connected to the first electrode of the precharge transistor and its output terminal electrically connected to the control electrode of the first clamp transistor, for reducing the peak current flowing through the first clamp transistor.

2. The sensitive amplifier according to claim 1, characterized in that, The detection unit includes a detection resistor, one end of which is electrically connected to the power supply terminal, and the other end of which is electrically connected to the first terminal of the precharge transistor and the input terminal of the feedback unit.

3. The sensitive amplifier according to claim 1, characterized in that, The detection unit includes a detection transistor, the first terminal of which is electrically connected to the power supply terminal, and the control terminal of which is electrically connected to the second terminal of which is also electrically connected to the first terminal of which is the precharge transistor. The detection transistor is a P-channel transistor.

4. The sensitive amplifier according to claim 2 or 3, characterized in that, The feedback unit includes: A first transistor, wherein the first terminal of the first transistor is electrically connected to the power supply terminal, and the control terminal of the first transistor is electrically connected to the other end of the detection resistor or the second terminal of the detection transistor; A second transistor, wherein the first terminal of the second transistor is electrically connected to the second terminal of the first transistor and the control terminal of the second transistor, and the second terminal of the second transistor is electrically connected to ground; and The third transistor has its first terminal electrically connected to the control terminal of the first clamping transistor, its second terminal electrically connected to the ground terminal, and its control terminal electrically connected to the second terminal of the first transistor.

5. The sensitive amplifier according to claim 4, characterized in that, The first transistor is a P-channel transistor; the second transistor and the third transistor are both N-channel transistors.

6. The sensitive amplifier according to claim 4, characterized in that, The ratio of the current flowing through the first transistor to the current flowing through the third transistor is 1:M, where M is a positive number.

7. The sensitive amplifier according to claim 4, characterized in that, The sensitive amplifier also includes: The fourth transistor has its first terminal electrically connected to the power supply terminal and its control terminal electrically connected to the first bias voltage terminal. The fourth transistor is a P-channel transistor. The second clamping transistor has its first terminal electrically connected to the second terminal of the fourth transistor and the control terminal of the first clamping transistor. The second terminal of the second clamping transistor is electrically connected to the ground terminal, and the control terminal of the second clamping transistor is electrically connected to the second terminal of the first clamping transistor.

8. The sensitive amplifier according to claim 7, characterized in that, The sensitive amplifier also includes: The fifth transistor has its first terminal electrically connected to the power supply terminal, its control terminal electrically connected to the second bias voltage terminal, and its second terminal electrically connected to the second terminal of the precharge transistor. The sixth transistor has its first terminal electrically connected to the power supply terminal and its control terminal electrically connected to the second terminal of the fifth transistor. The sixth transistor is a P-channel transistor. A seventh transistor, wherein the first terminal of the seventh transistor is electrically connected to the second terminal of the sixth transistor, the control terminal of the seventh transistor is electrically connected to the third bias voltage terminal, and the second terminal of the seventh transistor is electrically connected to the ground terminal; and The buffer has its input terminal electrically connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor, and its output terminal is used to output read data.

9. A memory chip, characterized in that, Includes the sensitive amplifier as described in any one of claims 1 to 8, wherein the memory chip is an XOR flash memory.

10. The memory chip according to claim 9, characterized in that, The memory chip also includes: A decoding transistor, wherein the first terminal of the decoding transistor is electrically connected to the total bit line, the control terminal of the decoding transistor is electrically connected to the decoding selection terminal, and the second terminal of the decoding transistor is electrically connected to the bit line; A storage transistor, wherein the first terminal of the storage transistor is electrically connected to the bit line, the control terminal of the storage transistor is electrically connected to the word line, and the second terminal of the storage transistor is electrically connected to the ground terminal.

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