A branch current-based in-memory multiplication calculation circuit

Abstract

The present invention relates to an in-memory accumulative multiplication calculation circuit based on branch current. The in-memory accumulative multiplication calculation circuit based on branch current includes a storage array for storing weight data, the storage array being composed of a plurality of identical SRAM cells, and each column of SRAM cells sharing bit lines BL and BLB. The bit lines BL and BLB are connected to a cascode current mirror unit for replicating a constant current source current. Each column of SRAM cells is connected to an operational amplifier unit for outputting the accumulative multiplication result via the bit line BL. The present invention provides a stable current for the bit lines BL and BLB through the cascode current mirror unit, and replaces the bit line voltage supply with the bit line current supply, thereby further reducing the operation power consumption; the operational amplifier unit can generate a stable output voltage, thereby ensuring the operation speed, stably outputting the operation result, and achieving high parallelism, thereby realizing high-speed and low-power multiplication and accumulation calculation.

Description

Technical Field

[0001] The present invention relates to an in-memory calculation circuit, and in particular to an in-memory cumulative multiplication calculation circuit based on branch current. Background Art

[0002] With the rapid development of artificial intelligence (AI) algorithms in recent years, the scale of neural networks has continued to expand, model parameters have increased, and the amount of data being processed has also grown. This data-intensive computing has placed tremendous pressure on computers using the traditional von Neumann architecture. In the traditional von Neumann architecture, computation and storage are separated, and data transmission between storage and computation becomes a significant factor affecting performance. To overcome the bottlenecks of the traditional von Neumann architecture, an in-memory computing approach has been proposed that integrates computational units with storage units. This reduces the frequency of memory access by computational units, improves speed, and reduces power consumption.

[0003] Conventional methods for performing in-memory multiplication operations compare the output voltage of the memory array with a reference voltage and derive the corresponding multiplication result based on the comparison result, or determine the corresponding multiplication result based on the difference in the discharge amount of the bit line. Although these methods can obtain the desired multiplication result, they all rely on applying a bit line voltage and then determining the desired multiplication result based on the change in the bit line voltage. Although the operation speed is improved, the operation power consumption is still unsatisfactory. Summary of the Invention

[0004] Based on this, it is necessary to provide an in-memory cumulative multiplication calculation circuit based on branch current to address the problem that the power consumption of existing in-memory multiplication operations is still relatively high.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A branch current-based in-memory multiplication circuit includes a memory array for storing weight data. The memory array is composed of multiple identical SRAM cells, with each column of SRAM cells sharing bit lines BL and BLB. The bit lines BL and BLB are connected to a cascode current mirror unit for replicating a constant current source. Each column of SRAM cells is connected to an operational amplifier unit via the bit line BL for outputting the multiplication result.

[0007] The operational amplifier unit consists of four PMOS transistors P7 through P10, two NMOS transistors N1 and N2, and an operational amplifier (OP). OP's negative input is connected to the bit line BL, its positive input is connected to the drains of N1 and P8, and its output is connected to the gates of P7 and P9. The sources of P7, P9, and N2 are connected to VDD. The drain of P7 is connected to the source of P8, the source of N1 is connected to the drain of N2, and the drain of P9 is connected to the source of P10. The gates of P8 and P10 are controlled by the control signal Vca, while the gate of N1 is controlled by the control signal Vwl. The drain of P10 serves as the output of the operational amplifier unit.

[0008] When any column of SRAM cells performs a cumulative multiplication calculation, the operational amplifier OP is connected to the bit line BL, P9 replicates the current transmitted from OP to P7, and outputs a current signal representing the cumulative multiplication result through P10.

[0009] Furthermore, the cascode current mirror unit includes six PMOS transistors P1 through P6. The sources of P1, P3, and P5 are connected to VDD. The drain of P1 is connected to the source of P2, the drain of P3 is connected to the source of P4, and the drain of P5 is connected to the source of P6. The gate and drain of P1 are connected. The gate and drain of P2 are connected and connected to a constant current source. The gates of P1, P3, and P5 are connected, and the gates of P2, P4, and P6 are connected. The drain of P4 is connected to bit line BL, and the drain of P6 is connected to bit line BLB.

[0010] Furthermore, the branch current-based in-memory accumulation calculation circuit further includes a quantization unit connected to the drain of P10 for quantizing the current signal outputted by P10 representing the accumulation result into a corresponding binary number.

[0011] Furthermore, the SRAM cell adopts a 6T memory cell including 6 transistors.

[0012] Furthermore, the 6T memory cell includes two PMOS transistors, P01 and P02, and four NMOS transistors, N01, N02, N03, and N04. P01 and N01 form an inverter structure, P02 and N02 form another inverter structure, and N03 and N04 serve as transmission transistors. The sources of P01 and P02 are both connected to VDD, while the sources of N01 and N02 are both connected to VSS. The drain of P01, the drain of N01, the gate of P02, and the gate of N02 are connected and serve as storage node Q and are connected to the drain of N03. The source of N03 is connected to bit line BL. The drain of P02, the drain of N02, the gate of P01, and the gate of N01 are connected and serve as storage node QB and are connected to the drain of N04. The gates of N03 and N04 are connected to word line WL, and the source of N04 is connected to bit line BLB.

[0013] Furthermore, when the storage node Q is at a high level and QB is at a low level, the weight data stored in the 6T storage unit is 0. When the storage node Q is at a low level and QB is at a high level, the weight data stored in the 6T storage unit is 1.

[0014] Furthermore, when the 6T memory cell operates in SRAM mode, it is disconnected from the operational amplifier unit and the cascode current mirror unit. The 6T memory cell implements SRAM mode through a hold operation, a write operation, and a read operation. The hold operation is used to retain data stored in the 6T memory cell. The write operation is used to write the desired data to the 6T memory cell. The read operation is used to read the data stored in the 6T memory cell.

[0015] Furthermore, when the 6T memory cell performs a hold operation, the word line WL maintains a low level, N03 and N04 are turned off, and the latch structure composed of N01, N02, P01, and P02 latches the storage data of the storage nodes Q and QB.

[0016] Furthermore, when the 6T memory cell performs a write operation, the word line WL remains at a high level, N03 and N04 are turned on, and the data to be written is loaded onto the bit lines BL and BLB. The feedback mechanism of the latch structure is broken, and the data is written into the storage nodes Q and QB.

[0017] Furthermore, when the 6T memory cell performs a read operation, the bit lines BL and BLB are precharged to a high level, the word line WL remains high, N03 and N04 are turned on, and the bit lines BL and BLB output electrical signals representing the results of the read operation.

[0018] The technical solution provided by the present invention has the following beneficial effects:

[0019] 1. The present invention provides stable current for the bit lines BL and BLB through the cascode current mirror unit, replacing the bit line voltage supply method with the bit line current supply method, thereby further reducing the operation power consumption; the operational amplifier unit can generate a stable output voltage, ensure the operation speed, stably output the operation results, and achieve high parallelism, thereby realizing high-speed and low-power multiplication and accumulation calculations.

[0020] 2. The operational amplifier unit designed in the present invention can return the output voltage of the operational amplifier OP to a normal potential through feedback control after the input voltage difference of the operational amplifier OP increases to a certain value, thereby facilitating the next cumulative multiplication calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is an overall schematic diagram of an in-memory cumulative multiplication calculation circuit based on branch current provided by the present invention.

[0022] Figure 2 Based on Figure 1 Circuit structure diagram of the operational amplifier unit.

[0023] Figure 3 Based on Figure 1 Circuit structure diagram of the cascode current mirror unit.

[0024] Figure 4 Based on Figure 1 Circuit structure diagram of the 6T memory cell.

[0025] Figure 5 Based on Figure 1 Comparison chart of theoretical and actual output current at an input current of 1μA.

[0026] Figure 6 Based on Figure 1 Comparison chart of theoretical and actual output current at an input current of 0.8μA. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] See also Figure 1 The present invention introduces an in-memory cumulative multiplication calculation circuit based on branch current, including a storage array for storing weight data. The storage array is composed of multiple identical SRAM cells, and each column of SRAM cells shares bit lines BL and BLB. The bit lines BL and BLB are connected to a cascode current mirror unit for replicating a constant current source current. Each column of SRAM cells is connected to an operational amplifier unit for outputting the cumulative multiplication result through the bit line BL. The output end of the operational amplifier unit is connected to a quantization unit, which is used to quantize the current signal representing the cumulative multiplication result output by the operational amplifier unit into a corresponding binary number.

[0029] First, the operational amplifier unit is described in detail. The operational amplifier unit includes four PMOS transistors P7-P10, two NMOS transistors N1-N2, and an operational amplifier OP.

[0030] See also Figure 2 , Figure 2The circuit structure of the operational amplifier unit is shown below. The operational amplifier OP's negative input is connected to bit line BL, its positive input is connected to the drains of N1 and P8, and its output is connected to the gates of P7 and P9. The sources of P7, P9, and N2 are connected to VDD. The drain of P7 is connected to the source of P8, the source of N1 is connected to the drain of N2, and the drain of P9 is connected to the source of P10. The gates of P8 and P10 are controlled by control signal Vca, and the gate of N1 is controlled by control signal Vwl. The drain of P10 serves as the output of the operational amplifier unit.

[0031] When the output voltage Vout of the operational amplifier OP drops due to other factors, the gate potential of P7 decreases, while the source voltage Vs remains unchanged. This increases the gate-source voltage difference, leading to an increase in the output current Ids, which in turn increases the drain potential of P8. The operational amplifier's negative input voltage Vin_n is compared with its positive input voltage Vin_p, causing the operational amplifier to increase its output, completing a feedback control operation that returns the output voltage Vout to its normal level.

[0032] Next, the cascode current mirror unit is described. The cascode current mirror unit includes six PMOS transistors P1 to P6.

[0033] See also Figure 3 , Figure 3 The circuit structure of the cascode current mirror unit is shown below. The specific connections are as follows: The sources of P1, P3, and P5 are connected to VDD. The drain of P1 is connected to the source of P2, the drain of P3 is connected to the source of P4, and the drain of P5 is connected to the source of P6. The gate and drain of P1 are connected. The gate and drain of P2 are connected and connected to a constant current source. The gates of P1, P3, and P5 are connected, and the gates of P2, P4, and P6 are connected. The drain of P4 is connected to bit line BL, and the drain of P6 is connected to bit line BLB.

[0034] The ideal constant current source is injected from the drain of P2, accurately copied to P4 and P6 through the cascode structure and passed to BL and BLB.

[0035] Next, the memory array is described. The memory array can be formed by multiple SRAM cells in an N×M array format. N is the number of rows, and M is the number of columns. One column of SRAM cells is connected to a corresponding operational amplifier unit via a bit line BL, so the number of operational amplifier units is also M. The external input weight is input into the SRAM cell via the word line WL. When the external input weight is 0, the word line WL is low. When the external input weight is 1, the word line WL is high. Since the final result of the cumulative multiplication calculation is a 1×1 result, it is necessary to obtain a cumulative multiplication result in which WL is high and the data stored in the SRAM cell is 1.

[0036] The foregoing defines the functions of the basic units of the present invention. Therefore, as long as a circuit with the corresponding functions is designed, connected, and used, the aforementioned circuit functions can be realized. In other words, the SRAM unit and quantization unit of the present invention are the basic functional units of the branch current-based in-memory multiplication and accumulation calculation circuit. However, the components and circuit connections of each basic functional unit are not limited to a specific form.

[0037] Specifically, the SRAM cell in the present invention can employ conventional memory cell circuits with varying numbers of transistors, such as 6T, 8T, 10T, and 12T. For example, the present invention employs a 6T memory cell comprising six transistors as an example, and designs a corresponding SRAM cell. The 6T memory cell includes two PMOS transistors, P01 and P02, and four NMOS transistors, N01, N02, N03, and N04.

[0038] See also Figure 4 , Figure 4 The circuit structure of a 6T memory cell is shown below. The specific connections are as follows: P01 and N01 form an inverter structure, P02 and N02 form another inverter structure, and N03 and N04 serve as transmission transistors. The sources of P01 and P02 are both connected to VDD, and the sources of N01 and N02 are both connected to VSS. The drain of P01, the drain of N01, the gate of P02, and the gate of N02 are connected together and serve as storage node Q and are connected to the drain of N03. The source of N03 is connected to bit line BL. The drain of P02, the drain of N02, the gate of P01, and the gate of N01 are connected together and serve as storage node QB and are connected to the drain of N04. The gates of N03 and N04 are connected to word line WL, and the source of N04 is connected to bit line BLB.

[0039] Based on the above structure, the cumulative multiplication calculation process of the present invention is described in detail using a column of SRAM cells as an example. At the beginning of the calculation, if the storage node Q is high and QB is low, the weight data stored in the 6T storage cell is 0. If the storage node Q is low and QB is high, the weight data stored in the 6T storage cell is 1.

[0040] Based on the external input weight data, the word line WL of the corresponding row of 6T memory cells is set to a high level. If the storage node Q in the conductive 6T memory cell is at a low level, node QB is high, forming a path between the bit line BL and ground, reducing the current on the bit line BL and the voltage on the bit line BL. Because the voltage on the bit line BL serves as the input of the operational amplifier OP, the output voltage of the operational amplifier OP also decreases. Because the output voltage of the operational amplifier OP serves as the gate input of P7, the current on P7 also changes accordingly. This current is then copied to P9. At this time, the current on P10, output by the quantization unit, is the number of cells in the corresponding turned-on 6T memory cell with internal storage data of 1, thus realizing the multiplication and accumulation function.

[0041] The memory array of the present invention can also operate in SRAM mode normally, and the normal SRAM mode can be operated by disconnecting the operational amplifier unit and the cascode current mirror unit. The operation of the SRAM mode is described in detail below.

[0042] 1. Maintain Operation

[0043] While the 6T memory cell is holding data, the word line WL remains at a low level, N03 and N04 are turned off, and the latch structure composed of N01, N02, P01, and P02 latches the storage data of the storage nodes Q and QB. Changes in the bit lines BL and BLB will not affect the storage nodes Q and QB.

[0044] 2. Write Operation

[0045] During a write operation on a 6T memory cell, word line WL remains high, and N03 and N04 are conductive. Assume that before the write operation, storage node Q is high and QB is low, meaning the stored data is "0." For example, to write data "1," the data "1" is loaded onto the write bit line, meaning BL is low and BLB is high. BL pulls down storage node Q via N03, and BLB pulls up storage node QB via N04. This breaks the feedback mechanism of the latch structure, and data "1" is written into the memory cell.

[0046] Similarly, assuming that before a write operation, storage node Q is low and QB is high, meaning the stored data is "1," then, for example, to write data "0," the data "0" is loaded onto the write bit line, meaning BL is high and BLB is low. BL pulls up storage node Q via N03, and BLB pulls down storage node QB via N04. This breaks the feedback mechanism of the latch structure, and data "0" is written into the memory cell.

[0047] 3. Read Operation

[0048] During a read operation on a 6T memory cell, bit lines BL and BLB are precharged to a high level, word line WL remains high, and N03 and N04 are turned on. Assuming that before the read operation, storage node Q is high and QB is low, meaning the stored data is "0," at the start of the read operation, bit lines BL and BLB are precharged to a high level. Bit line BLB then discharges to a low level, completing the "0" read operation via sense amplifier SA. Similarly, assuming the stored data Q is "1," at the start of the read operation, bit line BLB is also precharged to a high level. Storage node QB remains high, preventing bit line BLB from discharging and remaining high, completing the "1" read operation via sense amplifier SA.

[0049] In summary, the branch current-based in-memory multiplication-accumulation circuit of the present invention reduces computational power consumption by supplying bit line current to a satisfactory level. This circuit offers high parallelism and low power consumption, significantly improving computational energy efficiency. It overcomes the drawback of the traditional von Neumann architecture, which requires a separation between the arithmetic unit and memory, and achieves high-speed, low-power multiplication-accumulation calculations. Furthermore, it can operate in normal SRAM mode without affecting normal read and write operations of the memory array.

[0050] Performance Testing

[0051] In order to verify the effectiveness of the solution provided by the present invention, this embodiment also conducts data testing. The test content and test results are as follows:

[0052] 1. The test is conducted under the condition that the gain of the operational amplifier is 10000, the stable current is 1μA as the input current, and the memory array is measured using 6T memory cells with 16 rows and one column. The theoretical output current and the actual output current are as follows Figure 5 shown.

[0053] Depend on Figure 5 It can be seen that the increase in the number of open rows has little impact on the overall error. As the number of open rows increases, the overall error is within a smaller error range. Therefore, the in-memory multiplication circuit based on branch current is less affected by the number of open rows, the overall error is small, and the accuracy of the multiplication result is relatively stable.

[0054] 2. The test is conducted under the condition that the gain of the operational amplifier is 10000, the stable current is 0.8μA as the input current, and the memory array is measured using 6T memory cells with 16 rows and one column. The theoretical output current and the actual output current are as follows Figure 6 shown.

[0055] Depend on Figure 6It can be seen that when the number of enabled rows does not exceed 11, the error remains relatively stable. As the number of enabled rows increases, the error generally increases. This shows that after the input current value exceeds a certain range, increasing the number of enabled rows will increase the error.

[0056] In summary, when the input current value is within the appropriate range, the in-memory multiplication circuit based on branch current of the present invention is less affected by the number of open rows, has a small overall error, and has a high accuracy of the multiplication result, and can achieve high-speed and low-power multiplication calculation.

[0057] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0058] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A branch current-based in-memory cumulative multiplication calculation circuit, characterized in that: It includes a storage array for storing weight data, the storage array is composed of multiple identical SRAM cells, each column of SRAM cells shares bit lines BL and BLB; the bit lines BL and BLB are connected to a cascode current mirror unit for replicating a constant current source current; each column of SRAM cells is connected to an operational amplifier unit for outputting a cumulative multiplication result through the bit line BL; The operational amplifier unit includes four PMOS transistors P7 to P10, two NMOS transistors N1 to N2, and an operational amplifier OP; the negative input terminal of OP is connected to the bit line BL, the positive input terminal is connected to the drains of N1 and P8, and the output terminal is connected to the gates of P7 and P9; the source of P7, the source of P9, and the gate of N2 are connected to VDD, the drain of P7 is connected to the source of P8, the source of N1 is connected to the drain of N2, and the drain of P9 is connected to the source of P10; the gates of P8 and P10 are controlled by a control signal Vca, and the gate of N1 is controlled by a control signal Vwl; the drain of P10 serves as the output terminal of the operational amplifier unit; When any column of SRAM cells performs a cumulative multiplication calculation, the operational amplifier OP is connected to the bit line BL, P9 replicates the current transmitted from OP to P7, and outputs a current signal representing the cumulative multiplication result through P10.

2. The in-memory multiplication calculation circuit based on branch current according to claim 1, characterized in that: The cascode current mirror unit includes six PMOS tubes P1 to P6; the sources of P1, P3, and P5 are connected to VDD; the drain of P1 is connected to the source of P2, the drain of P3 is connected to the source of P4, and the drain of P5 is connected to the source of P6; the gate and drain of P1 are connected; the gate and drain of P2 are connected and connected to a constant current source; the gates of P1, P3, and P5 are connected, and the gates of P2, P4, and P6 are connected; the drain of P4 is connected to the bit line BL, and the drain of P6 is connected to the bit line BLB.

3. The in-memory multiplication calculation circuit based on branch current according to claim 1, characterized in that: The branch current-based in-memory cumulative multiplication calculation circuit further includes a quantization unit; the quantization unit is connected to the drain of P10 and is used to quantize the current signal output by P10 representing the cumulative multiplication result into a corresponding binary number.

4. The in-memory multiplication calculation circuit based on branch current according to claim 1, characterized in that: The SRAM cell adopts a 6T memory cell including 6 transistors.

5. The in-memory multiplication calculation circuit based on branch current according to claim 4, characterized in that: The 6T memory cell includes two PMOS transistors P01 and P02, and four NMOS transistors N01, N02, N03, and N04; wherein P01 and N01 form an inverter structure, P02 and N02 form another inverter structure, and N03 and N04 serve as transmission transistors respectively; the sources of P01 and P02 are both connected to VDD, and the sources of N01 and N02 are both connected to VSS; the drain of P01, the drain of N01, the gate of P02, and the gate of N02 are connected and serve as a storage node Q and are connected to the drain of N03, and the source of N03 is connected to the bit line BL; the drain of P02, the drain of N02, the gate of P01, and the gate of N01 are connected and serve as a storage node QB and are connected to the drain of N04, the gates of N03 and N04 are connected to the word line WL, and the source of N04 is connected to the bit line BLB.

6. The in-memory multiplication calculation circuit based on branch current according to claim 5, characterized in that: When the storage node Q is at a high level and QB is at a low level, it indicates that the weight data stored in the 6T storage unit is 0; when the storage node Q is at a low level and QB is at a high level, it indicates that the weight data stored in the 6T storage unit is 1.

7. The in-memory multiplication calculation circuit based on branch current according to claim 6, characterized in that: When the 6T storage unit executes the SRAM mode, the connection with the operational amplifier unit and the cascode current mirror unit is disconnected; the 6T storage unit implements the SRAM mode including a hold operation, a write operation, and a read operation; the hold operation is used to hold the data stored in the 6T storage unit; the write operation is used to write the required stored data into the 6T storage unit; and the read operation is used to read the data stored in the 6T storage unit.

8. The in-memory multiplication calculation circuit based on branch current according to claim 7, characterized in that: When the 6T memory cell performs a hold operation, the word line WL maintains a low level, N03 and N04 are turned off, and the latch structure composed of N01, N02, P01, and P02 latches the storage data of the storage nodes Q and QB.

9. The in-memory multiplication calculation circuit based on branch current according to claim 8, characterized in that: When the 6T memory cell performs a write operation, the word line WL maintains a high level, N03 and N04 are turned on, and the data to be written is loaded onto the bit lines BL and BLB. The feedback mechanism of the latch structure is broken, and the data is written into the storage nodes Q and QB.

10. The in-memory multiplication calculation circuit based on branch current according to claim 9, characterized in that: When the 6T memory cell performs a read operation, the bit lines BL and BLB are precharged to a high level, the word line WL remains at a high level, N03 and N04 are turned on, and the bit lines BL and BLB output electrical signals representing the results of the read operation.

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