Memory device and memory control method thereof

Abstract

A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information and a target threshold voltage level corresponding to the target memory state. The memory controller determines one or more program pulses for a pre-programming cycle based at least on the target memory state, including determining a voltage level of the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information and pre-programs the selected memory location by applying the one or more program pulses at the respective voltage levels, the one or more program pulses being applied without a program verify operation. After pre-programming, the memory controller programs the information to the selected memory location.

Description

TECHNICAL FIELD

[0001] The following disclosure relates to memory devices, and in particular, to methods, apparatuses, and systems related to programming semiconductor memory devices with threshold voltage distributions. BACKGROUND

[0002] Semiconductor memory devices include storage memory, such as flash memory, and a memory controller that manages the storage memory. The memory controller receives commands from a host device to operate on data stored in the storage memory.

[0003] SUMMARY

[0004] The present disclosure describes methods, apparatuses, and systems to tighten a threshold voltage (VT) distribution in a semiconductor memory device to produce improved performance of the memory device (e.g., accurate read performance with low bit error rates). The memory device includes a memory storage array having one or more arrays of storage cells for storing data, and a memory controller that manages access to the storage memory, such as after receiving a read or program / write command from a host device coupled to the memory device. Upon receiving a command to program data to the memory device, the memory controller performs a pre-filled program (PFP) cycle on target memory locations, such as memory blocks, sub-blocks, or pages, before using conventional programming to program the data to the memory locations. In the PFP cycle, the memory controller preprograms one or more storage cells of the target memory locations by applying one or more program pulses to the storage cells, but does not perform any accompanying program verify (PV) operations. Using the PFP cycle, electrons are pre-filled into the trap layers of the storage cells. These pre-filled electrons redistribute or spread out in the trap layers after the PFP cycle. Subsequently, the electrons programmed in a conventional program (PGM) cycle are inhibited from redistributing due to repulsion from the pre-filled electrons, which results in a reduced number of programmed / data electrons that spread out after the PGM cycle is completed. As a result, the VT distribution attributed to the spread out of the programmed / data electrons is tightened (e.g., limited or reduced), producing improved read performance of the memory device.

[0005] In a general case, a memory controller performs a memory control method that includes receiving a command to program information to a memory storage array controlled by the memory controller, determining a target memory state to store the information and a target threshold voltage level corresponding to the target memory state, determining one or more program pulses for a pre-programming cycle based at least on the target memory state, including determining voltage levels of the one or more program pulses based at least on the target threshold voltage level, selecting a memory location in the memory storage array to program the information, pre-programming the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without a program verify operation, and after the pre-programming, programming the information to the selected memory location.

[0006] Particular embodiments can include one or more of the following features. In some embodiments, programming the information to the selected memory location includes applying one or more additional program pulses to the selected memory location to reach the target threshold voltage level, the one or more additional program pulses applied with respective accompanying program verify operations.

[0007] In some embodiments, calculating the voltage levels of the one or more program pulses based at least on the target threshold voltage level includes determining that the voltage levels of the one or more program pulses are less than the target threshold voltage level. In some embodiments, determining that the voltage levels of the one or more program pulses are within a specified range of the target threshold voltage level.

[0008] In some implementations, the method includes receiving a second command to program second information to the memory storage array; determining a plurality of target memory states to store the second information, the plurality of target memory states including a first memory state and a second memory state; determining a plurality of target threshold voltage levels corresponding to the plurality of target memory states, the plurality of target threshold voltage levels including a first target voltage level corresponding to the first memory state and a second target voltage level corresponding to the second memory state, the second target voltage level being higher than the first target voltage level; determining one or more second programming pulses based at least on the plurality of target memory states, the one or more second programming pulses including a combined programming pulse to pre-program the first memory state and the second memory state; calculating voltage levels of the one or more second programming pulses based at least on the plurality of target threshold voltage levels, including calculating a first voltage level of the combined programming pulse; selecting a second memory location in the memory storage array to program the second information; pre-programming the second memory location by applying the one or more second programming pulses at respective voltage levels, including applying the combined programming pulse at the first voltage level to pre-program the second memory location for the first memory state and the second memory state, the one or more second programming pulses being applied without a program verify operation; and programming the information to the second memory location after pre-programming the second memory location. In some implementations, the first voltage level is less than the first target voltage level, and the first voltage level is within a specified range of the first target voltage level. In some implementations, determining that a threshold voltage of the selected memory location after completion of the pre-programming is less than the first target voltage level and within a specified range of the first target voltage level.

[0009] In some implementations, the selected memory location includes a first memory block associated with a first word line and a second memory block associated with a second word line. In such implementations, pre-programming the selected memory location and programming the information to the selected memory location includes pre-programming the first memory block by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; programming the information to the first memory block after pre-programming the first memory block; pre-programming the second memory block by applying the one or more programming pulses at respective voltage levels after programming the information to the first memory block, the one or more programming pulses being applied without a program verify operation; and programming the information to the second memory block after pre-programming the second memory block.

[0010] In some implementations, each of the first memory block and the second memory block respectively includes a plurality of first memory cells and second memory cells. In such implementations, pre-programming and programming the first memory block and the second memory block includes: pre-programming the plurality of first memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; after pre-programming the plurality of first memory cells, programming the information to the plurality of first memory cells; after programming the information to the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; and after pre-programming the plurality of second memory cells, programming the information to the plurality of second memory cells.

[0011] In some implementations, each of the first memory block and the second memory block respectively includes a plurality of first memory cells and second memory cells. In such implementations, pre-programming and programming the first memory block and the second memory block includes: pre-programming the plurality of first memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; after pre-programming the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; after pre-programming the plurality of second memory cells, programming the information to the plurality of first memory cells; and after programming the information to the plurality of first memory cells, programming the information to the plurality of second memory cells.

[0012] An implementation includes a memory device comprising: a memory storage array including one or more memory blocks, wherein at least one of the memory blocks includes one or more memory cells; and a memory controller to manage access to the memory storage array, wherein the memory controller is configured to perform the above operations. An implementation also includes a memory controller to manage a memory storage array in a memory device, wherein the memory controller comprises: one or more processors; and one or more machine-readable media storing instructions that, when executed, cause the one or more processors to perform the above operations.

[0013] Implementations also include non-transitory computer-readable media and systems. One such non-transitory computer-readable medium stores instructions that, when executed, cause one or more processors to perform the above-described operations. One such system includes a memory device having a memory controller to manage access to one or more arrays of memory cells in the memory device, where the memory controller is configured to perform the above-described operations. In some implementations, one such system includes a host device communicably coupled to the memory device and configured to access the arrays of memory cells. In such implementations, the memory controller is configured to perform the disclosed PFP cycling upon receiving a program command from the host device.

[0014] Using the novel features described above and in the following sections of this specification, the performance (e.g., memory read performance) of a semiconductor memory device such as a flash memory device can be improved. In conventional memory devices, VT redistribution can cause the VT range of a programmed state of a memory cell to encroach on the VT range of an adjacent programmed state. This encroachment or overlap can cause read operations to return incorrect results, e.g., values corresponding to an adjacent programmed state. Some approaches attempt to address the VT distribution problem using additional PV operations, which can add significant delay to programming operations and reduce the overall performance of the memory device.

[0015] In contrast, using the disclosed technique of PFP cycling, VT redistribution is reduced, such read operations return accurate results. PFP cycling does not use PV operations, thus programming time is shorter compared to other approaches. Thus, the disclosed technique improves the VT distribution of a memory device with better performance (e.g., shorter programming time) (e.g., by tightening) compared to other approaches.

[0016] The disclosed technology can be applied to various types of non-volatile memory devices. For example, the disclosed technology can be applied to NAND flash memory, including 2-dimensional (2D) and 3-dimensional (3D) NAND memory, or NOR flash memory or phase change memory (PCM), among others. Additionally or alternatively, the technology can be applied to various types of main memory or cache memory devices, such as resistive random access memory (ReRAM), or MRAM, among others. For various memory technologies, the disclosed technology can be applied to memory arrays having different types of storage cells, including single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC), among others.

[0017] The details of one or more disclosed implementations are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 A block diagram showing an example system using a pre-fill program (PFP) cycle during a memory program operation of a memory device is shown, in accordance with some embodiments.

[0019] Figure 2A And Figure 2B An example of a memory program operation with a pre-fill program (PFP) cycle before a traditional program (PGM) cycle is shown, in accordance with some embodiments.

[0020] Figure 3 A comparison between voltage levels of a pre-fill program (PFP) cycle and a corresponding traditional program (PGM) cycle is shown.

[0021] Figure 4A And Figure 4B Examples showing threshold voltage (VT) distributions after a memory program using the disclosed technology with a pre-fill program (PFP) cycle before a traditional program (PGM) cycle and a memory program using only traditional programming are shown, respectively.

[0022] Figure 5 An example of a memory program operation with a pre-fill program (PFP) cycle before a traditional program (PGM) cycle is shown, in accordance with some embodiments.

[0023] Figures 6A to 6D Examples of different sequences of memory cell selection during a program operation involving a pre-fill program (PFP) cycle are shown.

[0024] Figure 7 Examples of a process used by a memory controller to program data to a memory storage array using a program operation with a pre-fill program (PFP) cycle before a traditional program (PGM) cycle are shown.

[0025] Like reference numbers in the figures indicate like elements.

[0026] FIGURE NUMBER EXPLANATION

[0027] 1, A, B, C, D, E, F, G: State

[0028] 100: System

[0029] 110: Memory device

[0030] 112: Memory controller

[0031] 114: Memory storage array / Storage array

[0032] 116a, 116n, 602a, 602_0, 602_1, 602_n: Memory block

[0033] 116a_1, 116a_m, 116n_1, 116n_m, Unit0, Unit1, Unit2, Unit3: Memory cell / Cell

[0034] 117: Bus

[0035] 120: Host device

[0036] 200, 200A, 200B, 500: Program operation

[0037] 202, 242, 502, 604_0, 604_1, 604_n: Pre-fill program cycle

[0038] 202a, 202b, 202c, 202d, 202e, 202f, 202g, 502b, 502d, 502f: PFP pulse

[0039] 210, 250, 510, 606_0, 606_1, 606_n: Program cycle

[0040] 210a, 210b, 210c, 210n-1, 250a, 250b, 250c, 250d, 250n-1, 250n, 510a, 510b, 510c, 510d, 510n-1, 510n: Programming Pulse

[0041] 212a, 212b, 212c, 212n-1, 252a, 252b, 252c, 252n-1, 512a, 512b, 512c, 512n-1: PV pulses

[0042] 220, 420, 440, 520, 530: VT distribution curves

[0043] 222a, 222b, 222c, 222d, 222e, 222f, 222g, 522b, 522d, 522f: PFP curves

[0044] 320, 530: VT distribution

[0045] 322a, 322b, 322c, 322d, 322e, 322f, 322g, 532a, 532b, 532c, 532d, 532e, 532f, 532g: VT curves

[0046] 324, 534, 536: Margin

[0047] 400A, 400B: Storage Units

[0048] 410, 430: Semiconductor layers

[0049] 412, 414, 422a, 432, 442a, 452a: Curves

[0050] 422C, 452C: VT distribution curves

[0051] 600A, 600B, 600C, 600D: Sequence

[0052] 700: Process

[0053] 702, 704, 706, 708, 710, 712: Steps

[0054] WL0, WL1, WLn: Word lines Detailed Implementation

[0055] Figure 1A block diagram of an example system 100 using a pre-filled programming (PFP) cycle during memory programming operations of a memory device is shown. System 100 includes a memory device 110 coupled to a host device 120 via a bus 117. Memory device 110 includes a memory controller 112 and a memory storage array 114 for storing data and other information.

[0056] In some embodiments, memory device 110 is a memory storage device. As illustrative examples, memory device 110 may be an embedded multimedia card (eMMC), a secure digital card (SD), a solid-state drive (SSD), laptop or desktop computer memory, or some other suitable memory. In some embodiments, memory device 110 is a client device coupled to host device 120. For example, memory device 110 may be an SD card coupled to a digital camera or media player that is host device 120.

[0057] Memory controller 112 manages access to and operations performed on memory array 114. The following sections describe various techniques based on implementations using memory controller 112 to manage read and write operations on memory array 114. However, the techniques described in the following sections are also applicable to implementations using another type of controller (different from the memory controller) in memory device 110 to manage operations on memory array 114.

[0058] In some embodiments, memory array 114 is a non-volatile memory, such as NAND or NOR non-flash memory, or some other suitable non-volatile memory. In embodiments where memory array 114 is NAND or NOR non-flash memory, memory device 110 is a flash memory device, such as a flash memory card, and memory controller 112 is a flash controller. For example, in some cases, memory device 110 is a Serial Peripheral Interface (SPI) device, where the memory is NAND or NAND flash memory. For illustrative purposes, examples of using flash memory as memory array 114 are described below.

[0059] As illustrated, memory array 114 comprises multiple memory blocks: memory blocks 116a to memory blocks 116n. Each memory block contains one or more memory cells. For example, memory block 116a contains memory cells 116a_1...116a_m; and memory block 116n contains memory cells 116n_1...116n_m. In some embodiments, a memory cell is a memory sub-block. In other embodiments, a memory cell is a memory page.

[0060] A memory cell consists of one or more memory cells. Memory blocks and constituent memory cells are configured to store data or instructions, or both, in memory cells for use by the host device 120. Memory cells may include single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), or higher-level memory cells beyond QLC, or any combination thereof. An SLC stores one data bit per memory cell; an MLC stores two data bits per memory cell; a TLC stores three data bits per memory cell; a QLC stores four data bits per memory cell; and higher-level memory cells beyond QLC store five or more data bits per memory cell.

[0061] The memory controller 112 is a general-purpose microprocessor or microcontroller, or an application-specific integrated circuit (ASIC) chip, or other suitable type. The memory controller 112 receives programming (e.g., write) or read commands from the host device 112 via bus 117, and thus performs programming or read operations on the memory array 114 respectively.

[0062] In some embodiments, the memory controller 112 performs a PFP operation after receiving a programming command from the host device 120. As described in detail below, upon receiving the programming command, the memory controller 112 identifies memory locations (e.g., memory blocks, subblocks, or pages) to program data and performs a PFP operation on one or more memory cells at the memory location before writing the data to the memory cells using conventional programming operations. In some embodiments, the memory controller 112 performs PFP operations using the disclosed techniques at the level of memory blocks (such as memory block 116a or memory block 116n). In other embodiments, the memory controller 112 performs PFP operations using the disclosed techniques at the level of memory cells (memory subblocks or memory pages), such as memory cells 116a_1, 116a_m, 116n_1, or 116n_m. PFP operations can also be performed at different levels of detail for target memory locations in the storage array 114, such as memory blocks or memory cells, etc. In the following sections, PFP operations using the disclosed techniques are described relative to system 100.

[0063] Figure 2A and Figure 2B Examples of memory programming operations 200A and 200B, respectively, are shown, preceding conventional programming (PGM) cycle 210 and programming cycle 250, respectively, with pre-filled programming (PFP) cycles 202 and 242. In some embodiments, programming operations 200A and 200B are performed by memory controller 112 to program data to a target memory location in memory array 114 after receiving a programming command from host device 120, and the following description is relative to operations performed by memory controller 112. However, in other embodiments, programming operation 200A or programming operation 200B, or both, may be performed by other hardware and / or software in the system associated with the programmed memory array.

[0064] Memory controllers program memory locations by applying a set of voltage pulses, called programming pulses or shots, to memory cells during a programming cycle. This includes actions such as writing data to a constituent memory cell or erasing data from a self-contained memory cell. Programming pulses are applied to achieve a target threshold voltage (VT) level for the memory cell. When writing to a memory cell, the target VT level corresponds to the voltage level state of the memory cell representing the data bit to be written. When erasing data from a memory cell, the target VT level corresponds to the voltage level state that resets the memory cell to the erase state.

[0065] The voltage level of each programming pulse can be a fraction of the target VT level.Figure 2A The diagram illustrates PFP cycle 202 and PGM cycle 210 relative to the memory cell associated with the word line WLn. In PGM cycle 210, after each programming pulse, a PV operation is performed to determine whether the target VT has been reached, and accordingly, whether data has been correctly written to the memory cell or correctly erased from the memory cell. If the target VT level has not been reached, another programming pulse is applied to adjust the voltage level in the memory cell toward the target VT level, followed by a PV operation. For example, programming pulse 210a is followed by PV operation 212a, programming pulse 210b by PV operation 212b, programming trigger 210c by PV operation 212c, and programming trigger 210n-1 by PV operation 212n-1. The process is repeated until the target VT level of the memory cell is reached.

[0066] Prior to the conventional programming cycle 210, the memory controller performs a PFP cycle 202, in which the memory controller applies PFP pulses (i.e., programming pulses or excitation pulses) 202a, 202b, 202c, 202f, or 202g to the target memory cell without applying any program verification (PV) pulses. For example, no PV pulse is applied after PFP pulses 202a, 202b, 202c, 202f, or 202g. In contrast, as described above, in the PGM cycle 210, the memory controller performs a program verification operation by applying a PV pulse after each programming pulse. For example, the memory controller applies PV pulses 212a, 212b, 212c, and 212n-1 after programming pulses 210a, 210b, 210c, and 210n-1, respectively. Because the PFP pulse is applied without a PV, the extra programming time that would otherwise be used for PV operation is eliminated in the PFP cycle. Therefore, the PFP cycle 202 takes less time compared to schemes using PV operation. In some cases, due to the lack of PV after the programming pulse, the PFP cycle 202 is referred to as a dumb programming cycle.

[0067] As previously noted, a memory cell has several target VT levels corresponding to the voltage levels of several states in which data (e.g., bit values) are stored in the cell. For example, SLC, MLC, TLC, and QLC have two, four, eight, and sixteen target VT levels, respectively. Without loss of generality, programming operation 200A is shown relative to a TLC, which has a zero state (e.g., erase state) called state 1 and seven non-zero states called state A, state B, state C, state D, state E, state F, and state G, each corresponding to a target VT level. VT distribution curves 220 show the distribution curves of VT levels corresponding to different states in PFP cycle 202. For example, PFP curve 222a corresponds to the VT distribution of PFP pulse 202a. Similarly, PFP curves 222b, 222c, 222d, 222e, 222f, and 222g correspond to the VT distributions of PFP pulses 202b, 202c, 202d, 202e, 202f, and 202g, respectively.

[0068] During PFP cycle 202, the memory controller applies a PFP pulse corresponding to the VT level of the target state of the memory cell, the PFP pulse being determined based on the data to be programmed (e.g., if the value "010" or "011" is to be stored in the TLC cell, the target state is state B or state C, respectively). For illustration, the memory controller may determine that the target state for storing data "010" in the memory cell is state B. In this case, the target VT level of PFP cycle 202 corresponds to distribution curve 222b, and the memory controller applies PFP pulse 202b to achieve the target VT level of curve 222b. Subsequently, during PGM cycle 210, the memory controller applies programming pulse 210b, followed by PV 212b, to store data in the memory cell under state B.

[0069] As illustrated, PFP cycle 202 includes individual PFP pulses for each different state of the memory cell. For example, PFP pulses 202a, 202b, 202c, 202f, and 202g are applied respectively to achieve target VT levels for states A, B, C, F, and G. By having individual PFP pulses for individual states, the width of the VT distribution curve can be improved. PFP cycle 202 corresponds to an implementation of the memory controller 112 applying a single PFP pulse in the direct self-erasure state to achieve the VT level of the target state. For example, to achieve state F, a single PFP pulse 202f with a voltage level close to the target VT level of state F is applied in the direct self-erasure state.

[0070] In some implementations, the memory controller 112 applies multiple PFP pulses to achieve the VT level of the target state. For example, in such cases, two or more pulses with progressively increasing intensity may be applied to reach the target state. By applying multiple pulses with progressively increasing intensity, a better window is achieved when the VT level is obtained. Figure 2B A programming operation 200B for such an implementation is illustrated, where PFP loop 242 precedes PGM loop 250.

[0071] In PFP cycle 242, one or more PFP pulses are applied to train the target VT level of a specific state of the memory cell. For example, to pre-fill the programming memory cell to state A, PFP pulse 242a is applied. However, to pre-fill the programming memory cell to state B, a first PFP pulse 242a is applied to change the VT level of the memory cell from the erase state to a VT level close to that of state A, and then a second PFP pulse 242b with a progressively larger intensity than pulse 242a is applied, further increasing the VT level of the memory cell to a target VT level close to that of state B. Since the PFP pulse 242a corresponding to state A has a lower VT level than that of state B, there is no problem of over-programming when using PFP pulse 242a to pre-fill the memory cell to state B (or other higher states, such as state C, state D, state E, state F, or state G). However, the PFP pulse 242b corresponding to state B has a higher level than the VT level of state A and cannot be used to pre-fill the memory cell to state A because it would be over-programmed for state A.

[0072] Similarly, to pre-fill and program a memory cell to the VT level of state C, a PFP pulse 242a is first applied to the memory cell to achieve the VT level of state A in a self-erasing state; then, a PFP pulse 242b is applied to shift the VT level higher to the VT level of state B; and finally, a PFP pulse 242c is applied to achieve the target VT level corresponding to state C. Likewise, to pre-fill and program to state F, PFP pulses 242a, 242b, 242c, and up to PFP pulse 242f are applied in successive operations; and to pre-fill and program to state G, PFP pulses 242a, 242b, 242c, and up to PFP pulse 242f are applied in successive operations, and finally, a PFP pulse 242g is applied.

[0073] Therefore, using PFP cycle 242, the memory cell is programmed to the target state by incremental pre-filling, starting from the lowest state and moving to the next higher state with each PFP pulse until the VT level of the target state is reached. However, when programming pulses 250a, 250b, 250c, 250d, 250n-1, and 250n are applied, PGM cycle 250 is similar to PGM cycle 210, with each programming pulse followed by a PV pulse, such as PV pulses 252a, 252b, 252c, and 252n-1.

[0074] In some implementations, depending on the programming options, it is possible to modify whether the VT level of the target state is achieved using a single PFP pulse (as in PFP loop 202) or multiple PFP pulses (as in PFP loop 242). This is achieved by providing different programming commands for the bit line (BL) signal. For example, achieving state F of the memory cell using a single PFP pulse can be done by providing the programming (PGM) command "BL with state F added to PGM (0 volts)". In contrast, achieving state F using multiple PFP pulses can be done by providing the programming (PGM) command "BL with state A / B / C / D / E / F added to PGM (0 volts)".

[0075] In some implementations, the level of the PFP pulse is determined such that the corresponding VT level of the memory cell after the PFP pulse is applied is close to but less than the PV level used for the actual programming operation. In such implementations, after the PFP pulse is applied, the PFP pulse level is determined to reach individual VT levels within a specified range of the PV level used for the actual programming operation. The PFP pulse level is selected within the specified range to avoid overprogramming the memory cell, for example, to avoid the VT level after the PFP operation exceeding the PV level used for the actual programming operation, which could lead to errors in the data stored in the memory cell (e.g., the state of the memory cell may be higher than the target state). In such cases, the PFP pulse level is determined by the programming speed associated with the programming process. As an example, the difference between the higher limit of the VT level after the PFP cycle (“PFP_VT_HB”) and the higher limit of the VT level after the PGM cycle (“PGM_VT_HB”) can be in the range of 0 volts (V) to 1.2 volts, as indicated by the following equation (1). A poor lower bound value may be better for achieving the window when obtaining the VT level, but carries a greater risk of overprogramming.

[0076] PGM_VT_HB-PFP_VT_HB=0V~1.2V (1)

[0077] In this way, the memory controller selects the PFP pulse optimized for the corresponding VT level.

[0078] Figure 3 This diagram shows a comparison between the voltage levels of a pre-filled programming (PFP) cycle and its corresponding conventional programming (PGM) cycle. VT distribution curve 220 corresponds to PFP cycle 202, as described above. VT distribution 320 shows the distribution curves of VT levels for different states of PGM cycle 210. For example, VT curve 322a corresponds to the VT level distribution at the end of the PV cycle for state A. Similarly, VT curves 322b, 322c, 322d, 322e, 322f, and 322g correspond to the VT distributions at the end of the respective PV cycles for states B, C, D, E, F, and G, respectively. As illustrated, for each state, the PFP pulse level is close to but less than the corresponding VT level for that state. For example, for state A, margin 324 shows the difference between the PFP pulse level (given by curve 222a) and the VT level (given by curve 322a), the difference indicating that the PFP pulse level is less than its corresponding VT level. Similarly, in each of the other states, the PFP level is less than its corresponding VT level.

[0079] Figure 4A and Figure 4BExamples are provided showing the threshold voltage (VT) distributions after memory programming using the disclosed technique with a pre-filled programming (PFP) cycle prior to the conventional programming (PGM) cycle and memory programming using only conventional programming. Figure 4A A schematic diagram illustrating the distribution of electrons in the semiconductor layer 410 of the memory cell 400A during a read operation following a programming cycle (e.g., programming operation 200) that includes a PFP cycle prior to the PGM cycle according to the disclosed technology.

[0080] Curve 412 indicates the distribution of PFP electrons in the trapping layer of the memory cell between oxide layers after a PFP cycle (e.g., PFP cycle 202) is completed, in which one or more PFP pulses are applied to the memory cell to achieve a VT level corresponding to the target programming state. Curve 412 indicates that the PFP electrons have been redistributed (spread out) in the trapping layer.

[0081] Curve 414 indicates the distribution of programming electrons in the trapping layer after a programming cycle (e.g., PGM cycle 210) is completed, in which one or more programming pulses are applied to the memory cell to store data in the memory cell under the target programming state. Curve 414 indicates that the programming electrons have been redistributed (spread out) to a significantly smaller extent in the trapping layer compared to PFP electrons. This is because the earlier spread-out redistributed PFP electrons block the redistribution of programming electrons due to electron repulsion, and thus limit the redistribution of the target VT.

[0082] VT distribution curves, as shown in Figure 420, depict the distribution of VT levels in memory cell 400A for different states at (i) after programming verification (or after PV) and (ii) during read operations. For example, curve 322a corresponds to the VT distribution after PV for state A, while curve 422a plots the VT distribution for state A during subsequent read operations. The proximity of curves 422a to 322a indicates that the VT redistribution of memory cell 400A is limited by the application of the PFP cycle. VT distribution curves for other states follow a similar pattern. For example, for state C, VT distribution curve 422C is close to the corresponding VT distribution curve 322c after PV during read operations.

[0083] Figure 4BThis diagram illustrates the distribution of electrons in the semiconductor layer 430 of memory cell 400B during a read operation following a conventional programming operation without a PFP cycle. Curve 432 indicates the distribution of programming electrons in the trapping layer after conventional programming is completed. Curve 432 indicates that the programming electrons have been redistributed (spread out) in the trapping layer; a comparison of curve 432 with curve 414 for programming electrons in memory cell 400A shows that the programming electrons for memory cell 400B have been redistributed to a significantly larger area compared to those for memory cell 400A. This is because there are no PFP electrons in the trapping layer of memory cell 400B to prevent the redistribution of programming electrons, since the conventional programming operation for memory cell 400B does not include a PFP cycle.

[0084] VT distribution curves, shown in Figure 440, depict the distribution of VT levels in memory cell 400B for different states during (i) the completion of the programming verification operation (after PV) and (ii) during a read operation. For example, curve 442a corresponds to the VT distribution after PV in state A, while curve 452a plots the VT distribution for state A during a subsequent read operation. Compared to the divergence of curve 322a from memory cell 400A, curve 452a diverges with greater margin from curve 442a. The increased divergence of curves 442a and 452a compared to the divergence of curves 322a and 422a indicates that the VT level of memory cell 400B has been redistributed to a larger range after PV compared to the corresponding VT level after PV in memory cell 400A. The redistribution in the latter case is limited by the application of the PFP cycle. VT distribution curves for other states follow a similar pattern. For example, for state C, compared with the corresponding level of state C of storage cell 400A, the VT distribution curve 452C diverges more significantly from PV to VT distribution curve 442c during the read operation, as shown by curves 322c and 422c.

[0085] In the above implementations, a separate PFP pulse is applied for each state of the memory cell, as described above. In some implementations, a single PFP pulse is applied for two or more states of the memory cell. In such cases, when applying a PFP pulse for a specific state of the memory cell, the same PFP pulse can also be used to pre-fill and program one or more higher memory cell states (states at higher VT levels). For example, when a PFP pulse is applied to state B, state C can also be pre-filled and programmed. Such multi-state PFP pulses can be useful in some cases to improve performance because fewer PFP pulses are used to achieve the target state, thus reducing the time spent on PFP cycles. Figure 5An example of a memory programming operation 500 is shown, having a pre-filled programming (PFP) cycle 502 preceding a conventional programming (PGM) cycle 510. In some embodiments, the programming operation 500 is performed by a memory controller 112 to program data to one or more memory cells at a target memory location in the memory array 114 after receiving a programming command from a host device 120, and the following description is relative to the operation performed by the memory controller 112. However, in other embodiments, the programming operation 500 may be performed by other hardware and / or software in the system associated with the programmed memory array.

[0086] like Figure 5 As illustrated, PFP loop 502 precedes PGM loop 510 in programming operation 500. In PFP loop 502, each PFP pulse is used for two states of the memory cell. For example, PFP pulses 502b, 502d, and 502f are used for combining states B and C, combining states D and E, and combining states F and G, respectively. In this example, no PFP pulse is used for combining states 1 and A. PGM loop 510 is similar to PGM loop 210, in which programming pulses 510a, 510b, 510c, 510d, 510n-1, and 510n are applied, each followed by PV pulses, such as PV pulses 512a, 512b, 512c, and 512n-1.

[0087] In some cases, greater flexibility can be achieved by using combined PFP pulses for fewer states than the number shown. For example, there could be combined PFP pulses 502d (states D and E) and PFP pulses 502f (states F and G), but no PFP pulses for states A, B, or C. The number of PFP pulses is a design choice that may depend on the trade-off between performance and window size.

[0088] To prevent over-programming of states, the level of the PFP pulse used for combining two or more states is configured to reach the VT level of the memory cell after the PFP pulse is applied, wherein the PFP pulse is close to but less than the PV level corresponding to the lowest state in the combined states. For example, the level of PFP pulse 502b (which is used for combining states B and C) is determined to be close to but less than the PV level of state B.

[0089] VT distribution curve 520 shows the distribution curves of VT levels corresponding to PFP cycle 502 for different states. For example, PFP curves 522b, 522d, and 522f represent the VT distributions of PFP pulses 502b, 502d, and 502f, respectively. VT distribution 530 shows the distribution curves of VT levels for different states of PGM cycle 510. For example, VT curves 532a, 532b, 532c, 532d, 532e, 532f, and 532g correspond to the VT distributions at the end of each PV cycle for states A, B, C, D, E, F, and G, respectively. A comparison of distribution curves 520 and 530 shows that the PFP pulse level is close to but less than the corresponding VT level for the lowest state of the PFP pulse. For example, for the PFP pulse 502b used to combine states B and C, margin 534 shows the difference between the VT level after PFP in state B (given by curve 522b) and the VT level after PV (given by curve 532b), while margin 536 shows the difference between the VT level after PFP in state C (given by curve 522b) and the VT level after PV (given by curve 532c).

[0090] Margins 534 and 536 indicate that the post-PFP VT level of PFP pulse 502b is less than the post-PV VT level of states B and C, respectively. Margins 534 and 536 also indicate that the difference between the post-PFP VT level and the post-PV VT level of state B is less than the difference between the post-PV VT level of state C (which is higher than state B). This demonstrates that the PFP pulse level is closer to (but less than) the PV VT level for lower states (state B) but further away from the PV VT level for higher states (state C). In this example, the VT level of PFP pulse 502b is set so that state B is not overprogrammed. State C is also not overprogrammed because the PFP pulse 502b level is further lower than the VT level of state C.

[0091] By making the VT level of the PFP pulse lower than the lowest PV VT level of the combined states, overprogramming of the lowest state is avoided. However, this results in the VT level of the PFP pulse being further away from the PV VT level of higher states (e.g., state C). Consequently, the subsequent PV VT distribution of state C can be wider than that of state B, which may make read operations of state C less accurate in some cases.

[0092] The above programming operation 500 illustrates one embodiment in which a combined PFP pulse is used for two states of a memory cell. In some embodiments, a combined PFP pulse is applied for more than two states of a memory cell. In such cases, a PFP pulse for a specific state of the memory cell can be used to pre-fill all higher states of the programmed memory cell using the same PFP pulse. For example, when a PFP pulse is applied to state B, states C, D, E, F, and G can also be pre-filled and programmed.

[0093] In some implementations, the number of memory cell states pre-filled using PFP pulses can be modified depending on the programming options. For example, depending on the choice of different programming options, PFP pulses can be used for pre-filling programming: state A only; state A and state B; or state A, state B, and state C, and other suitable combinations.

[0094] In some implementations, there is a finite delay between the end of a PFP cycle and the start of an associated PGM cycle during a programming operation. In such implementations, the memory controller waits a finite amount of time after completing a PFP cycle and before initiating a PGM cycle. For example, for programming operation 200A or programming operation 200B, the memory controller 112 waits a finite amount of time between PFP cycle 202 and PGM cycle 210, or between PFP cycle 242 and PGM cycle 250, respectively. Similarly, for programming operation 500, the memory controller 112 waits a finite amount of time between PFP cycle 502 and PGM cycle 510. This waiting time allows for the redistribution of PFP electrons within the trapping layer. In some cases, the waiting time is approximately tens of microseconds or milliseconds.

[0095] The memory controller can program a series of memory cells (e.g., in units of memory blocks, sub-blocks, or pages) by selecting different sequences of memory cells in different implementations. Figures 6A to 6D Examples of different sequences of memory cell selection are shown during programming operations involving pre-filled programming (PFP) cycles. In some embodiments, the different sequences shown are used by the memory controller 112 during any of programming operations 200A, 200B, or 500.

[0096] Figure 6AThe diagram illustrates sequence 600A, in which the memory controller completes a pre-filled programming (PFP) cycle and an associated conventional programming (PGM) cycle on the same word line before moving to the next word line. The diagram illustrates three distinct word lines WL0, WL1, and WLn of a memory array (e.g., memory storage array 114). Memory blocks 602_0, 602_1, and 602_n are associated with word lines WL0, WL1, and WLn, respectively. When using sequence 600A, the memory controller completes programming operations on the memory block associated with the word line (e.g., a PFP cycle on the memory block, followed by a PGM cycle on the same memory block) before moving to a different memory block associated with another word line. For example, the memory controller 112 performs a PFP cycle 604_0 on the memory block 602_0 associated with word line WL0, waits for a finite amount of time after completing the PFP cycle 604_0, and then performs a PGM cycle 606_0 on the memory block 602_0.

[0097] After completing both the PFP loop and the PGM loop for memory block 602_0, the memory controller proceeds to program the next target memory block (e.g., memory block 602_1 associated with word line WL1), completing PFP loop 604_1 followed by PGM loop 606_1, and then proceeds to the next target memory block. Following this method in sequence 600A, when memory block 602_n associated with word line WLn is programmed, the memory controller performs PFP loop 604_n followed by PGM loop 606_n for the memory block, as illustrated. The memory controller waits for a finite amount of time between PFP loop 604_1 and PGM loop 606_1, and between PFP loop 604_n and PGM loop 606_n.

[0098] In some implementations, the memory controller utilizes the waiting period between the PFP cycle and the associated PGM cycle to pre-populate different target memory blocks for programming. Instead of remaining idle, the memory controller utilizes the waiting period in such implementations. The performance of the memory programming operation can thus be improved (e.g., by reducing the total operation time). Sequence 600B illustrates one such implementation. In sequence 600B, after completing PFP cycle 604_0 for memory block 602_0, the memory controller 112 utilizes the waiting time before conventional programming of memory block 602_0 can be completed to perform a PFP cycle for another target memory block. For example, as illustrated, after PFP cycle 604_0 for memory block 602_0, the memory controller immediately proceeds to PFP cycle 604_1 for memory block 602_1, and then returns to perform PGM cycle 606_0 for memory block 602_0. After PGM cycle 606_0, the memory controller performs PGM cycle 606_1 on memory block 602_1. In this way, the memory controller utilizes the waiting time of other PFP operations to achieve an overall reduction in programming time.

[0099] Other permutations of the order of PFP and PGM cycles for memory blocks are possible. For example, in some cases, after PGM cycle 606_0, the memory controller 112 performs a PFP cycle for the next target memory block and then resumes to perform PGM cycle 606_1 for memory block 602_1.

[0100] In some cases, the memory controller 112 performs a PFP cycle on three or more memory blocks sequentially before performing a PGM cycle on these memory blocks. For example, after a PFP cycle 604_1 on memory block 602_1, before returning to perform a PGM cycle 606_0 on memory block 602_0, the memory controller may perform a PFP cycle on one or more other target memory blocks.

[0101] The number of memory blocks addressed in consecutive PFP cycles can depend on the latency. Longer latency allows the memory controller to perform PFP operations on a larger number of memory blocks consecutively, while shorter latency allows for consecutive PFP operations on a smaller number of memory blocks.

[0102] Although instances of memory programming operations for sequences 600A and 600B are described at the granularity of memory blocks, the memory controller can use different sequences at the granularity of sub-blocks or pages. For example, Figures 6A to 6DEach of memory blocks 602_0, 602_1, and 602_n contains memory cells Unit0, Unit1, Unit2, and Unit3. A memory cell can be a sub-block or a page. The numerical markers 1, 2, 3, 4…15, 16, etc., in the PFP and PGM rows indicate the order in which the memory controller performs PFP and PGM cycles on the memory cells within the memory block. For sequences 600A and 600B as illustrated, during the PFP and PGM cycles on the memory block, the memory controller performs PFP and PGM operations on the constituent memory cells of memory block 602a in the time sequence of Unit1, Unit0, Unit2, and Unit3. The difference in the arrangement of sequences 600A and 600B lies at the memory block level. However, in some cases, the memory controller may use different sequences at the memory cell level.

[0103] Figure 6C and Figure 6D Sequences 600C and 600D are shown, in which the memory controller uses different arrangements of PFP cycles and associated PGM cycles at the memory cell granularity, where the memory cell can be a memory subblock or a memory page. When using sequence 600C, the memory controller completes the PFP cycle and associated PGM cycle for the same memory cell (memory subblock or memory page) before proceeding to the next memory cell (which may be in a different memory block). An example of sequence 600C shows the memory controller performing memory programming operations at the memory cell granularity in the following time sequence:

[0104] • Perform a PFP loop (value mark 1) on Unit0 of memory block 602_0, followed by a PGM loop (value mark 2);

[0105] • Perform a PFP loop (3) on Unit0 of memory block 602_1, followed by a PGM loop (4);

[0106] • Perform a PFP loop (5) on Unit1 of memory block 602_0, followed by a PGM loop (6);

[0107] • Perform a PFP loop (7) on Unitl of memory block 602_1, followed by a PGM loop (8), etc.

[0108] Compared to Sequence 600C, in some embodiments, after completing the PFP cycle for a memory cell, the memory controller uses a waiting period to perform a PFP cycle on one or more other memory cells before performing a programming operation immediately after the waiting period. For example, an example of Sequence 600D shows the memory controller performing memory programming operations at the memory cell granularity in the following time sequence:

[0109] • Perform a PFP loop (1) on Unit0 of memory block 602_0;

[0110] • Perform a PFP loop (2) on Unitl of memory block 602_0;

[0111] • Perform PGM loop on Unit0 of memory block 602_0 (3);

[0112] • Perform a PFP loop (4) on Unitl of memory block 602_0;

[0113] • Perform a PFP loop (5) on Unit2 of memory block 602_0;

[0114] ● Perform PFP loop (6) on Unit3 of memory block 602_0;

[0115] ● Perform PGM loop (7) on Unit2 of memory block 602_0;

[0116] • Perform PGM loop (8) on Unit3 of memory block 602_0;

[0117] • Perform a PFP loop (9) on Unit0 of memory block 602_1;

[0118] • Perform a PFP loop (10) on Unit1 of memory block 602_1;

[0119] • Perform a PGM loop on Unit0 of memory block 602_1 (11);

[0120] • Perform PGM loop (12) on Unit1 of memory block 602_1; etc.

[0121] The example shown in Sequence 600D illustrates that, in some cases, the memory controller interleaves PFP and PGM cycles for adjacent memory cells within a memory block to utilize latency. Other permutations are also possible. For example, in some cases, the memory controller may interleave PFP and PGM cycles for non-adjacent memory cells within a memory block (e.g., memory cells Unit0 and Unit2 in memory block 602_0), or for memory cells in different memory blocks (e.g., memory cell Unit0 in memory block 602_0 and Unit0 in memory block 602_1). In some cases, the memory controller may sequentially cycle through three or more memory cells within a memory block before cycling through PGM for these memory cells. In some cases, the memory controller may sequentially cycle through memory cells in two or more memory blocks before cycling through PGM for these memory cells. Other suitable permutations are also possible.

[0122] Figure 7 An example of process 700 is shown, which is used by a memory controller to program data into a memory array using a programming operation having a pre-filled programming (PFP) cycle preceding a conventional programming (PGM) cycle. In some embodiments, process 700 is performed by memory controller 112 to program data into one or more target memory cells in memory array 114 after receiving a programming command from host device 120. Therefore, process 700 is described in the following sections with respect to the operation performed by memory controller 112. However, process 700 may also be performed by other hardware and / or software in the system associated with the programmed memory array. In some embodiments, the operation described with respect to process 700 corresponds to memory programming operation 200A, programming operation 200B, or programming operation 500.

[0123] Process 700 begins when the memory controller receives a command to program information into the memory storage array (702). For example, the memory controller 112 receives a programming command from the host device 120 to write data into the memory device 110.

[0124] Upon receiving a programming command, the memory controller determines the target memory state and the corresponding target threshold voltage (VT) level to store the information or data specified by the programming command (704). For example, the programming command could be to write data containing the bit value "010". In this case, the memory controller determines that the target memory state for writing the bit value "010" is the third state or state B of the TLC memory cell, and therefore determines the VT level after PV in state B as the target VT level.

[0125] After determining the target memory state and the corresponding target threshold voltage level, the memory controller determines one or more programming pulses and associated voltage levels of the pre-programming cycle for the programming operation used in the programming command (706). For example, the memory controller 112 determines one or more PFP pulses based on the target VT level of the programming command, as described with respect to programming operation 200A, programming operation 200B, or programming operation 500.

[0126] The memory controller selects a memory location in the memory array to program information (708). For example, the memory controller 112 selects one or more memory blocks or memory cells (e.g., memory subblocks or memory pages) to program data for programming operation 200A, programming operation 200B, or programming operation 500.

[0127] The memory controller applies one or more programming pulses to the selected memory location (710) at individual voltage levels without a programming verification operation. For example, the memory controller 112 performs a memory programming operation 200A on the target memory location. As part of the memory programming operation 200A, the memory controller performs a PFP loop 202 on one or more memory cells at the target memory location. In the PFP loop 202, the memory controller 112 applies one of PFP pulses 202a, 202b, 202c, 202f, or 202g to pre-fill the memory cells to a VT level close to but less than the PV-VT level of the target state. As another example, the memory controller 112 performs a memory programming operation 200B on the target memory location, wherein the memory controller performs a PFP loop 242 on one or more memory cells at the target memory location. In PFP loop 242, memory controller 112 applies one or more PFP pulses (e.g., one or more PFP pulses 242a, 242b, 242c, 242f, or 242g) in a stepwise operation to pre-fill the memory cells to a VT level close to but less than the post-PV VT level of the target state by incrementally increasing the VT level of the memory state. As another example, memory controller 112 performs a memory programming operation 500 on a target memory location, wherein the memory controller performs a PFP loop 502 on one or more memory cells at the target memory location. In PFP loop 502, memory controller 112 applies one or more combined PFP pulses (e.g., PFP pulse 502b, PFP pulse 502d, or PFP pulse 502f) to pre-fill the memory cells to a VT level close to but less than the post-PV VT level of multiple target states. As previously described, PFP pulses in PFP cycle 200A, PFP cycle 200B, or PFP cycle 500 are applied without programming verification.

[0128] After a PFP cycle is performed on the selected memory location, the memory controller programs the selected memory location (712) with information indicated by the programming command. For example, when performing memory programming operation 200A or programming operation 200B on the target memory location, the memory controller 112 performs PGM cycle 210 or PGM cycle 250 after PFP cycle 202 or PFP cycle 242, respectively, to program data in one or more memory cells of the target memory location. As another example, when performing memory programming operation 500 on the target memory location, the memory controller 112 performs PGM cycle 510 after PFP cycle 502 to program data in one or more memory cells of the target memory location. As previously described, PGM cycle 210, PGM cycle 250, or PGM cycle 510 includes conventional programming operations, where a programming pulse is followed by programming verification.

[0129] It should be noted that although process steps, method steps, algorithms or the like may be described in the above order, such processes, methods and algorithms may often be configured to work in an alternative order unless specifically stated otherwise.

[0130] The processes and logic described in this document can be performed by one or more programmable processors that execute one or more computer programs to perform the functions described herein. The processes and logic can also be performed by a dedicated logic circuit system (e.g., an FPGA or an application-specific integrated circuit (ASIC)), and the device can also be implemented as said dedicated logic circuit system.

[0131] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors, as well as any one or more processors of any kind of digital computer. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices. Processors and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0132] While this document may describe numerous details, these details should not be construed as limiting the scope of the invention as claimed or potentially claimed, but rather as describing features specific to a particular embodiment. Certain features described in this document within the context of a single embodiment may also be implemented in combination in that single embodiment. Conversely, various features described within the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even initially claimed in this manner, one or more features from the claimed combination may be removed from said combination in some cases, and the claimed combination may be for sub-combinations or variations thereof. Similarly, although operations are depicted in a particular order in the figures, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or to perform all shown operations to achieve the desired result.

[0133] Only a few examples and implementation schemes are disclosed. Variations, modifications, and enhancements to the described examples and implementation schemes, as well as other implementation schemes, can be based on the disclosed content.

Claims

1. A memory control method suitable for a memory controller, characterized by, The method comprises: receiving a command to program information to a memory storage array controlled by the memory controller; determining a target memory state to store the information and a target threshold voltage level corresponding to the target memory state; determining one or more programming pulses for a pre-programming cycle based at least on the target memory state, including determining a voltage level of the one or more programming pulses based at least on the target threshold voltage level; selecting a memory location in the memory storage array to program the information; pre-programming the selected memory location by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; and programming the information to the selected memory location after the pre-programming; further comprising: receiving a second command to program second information to the memory storage array; determining a plurality of target memory states to store the second information, the plurality of target memory states including a first memory state and a second memory state; determining a plurality of target threshold voltage levels corresponding to the plurality of target memory states, the plurality of target threshold voltage levels including a first target voltage level corresponding to the first memory state and a second target voltage level corresponding to the second memory state, the second target voltage level higher than the first target voltage level; determining one or more second programming pulses based at least on the plurality of target memory states, the one or more second programming pulses including a combined programming pulse for pre-programming the first memory state and the second memory state; calculating voltage levels of the one or more second programming pulses based at least on the plurality of target threshold voltage levels, including calculating a first voltage level of the combined programming pulse; selecting a second memory location in the memory storage array to program the second information; pre-programming the second memory location by applying the one or more second programming pulses at respective voltage levels, including applying the combined programming pulse at the first voltage level to pre-program the second memory location for the first memory state and the second memory state, the one or more second programming pulses applied without a program verify operation; and programming the information to the second memory location after pre-programming the second memory location.

2. The memory control method according to claim 1, wherein, Programming the information to the selected memory location includes applying one or more additional programming pulses to the selected memory location to reach the target threshold voltage level, the one or more additional programming pulses applied with respective accompanying program verify operations.

3. The memory control method of claim 1, wherein, Calculating voltage levels of the one or more programming pulses based at least on the target threshold voltage level includes: determining that the voltage levels of the one or more programming pulses are less than the target threshold voltage level.

4. The memory control method according to claim 3, wherein, Further comprising: determining that the voltage levels of the one or more programming pulses are within a specified range of the target threshold voltage level.

5. The memory control method of claim 1, wherein, the first voltage level is less than the first target voltage level, and the second voltage level is greater than the second target voltage level. wherein the first voltage level is within a specified range of the first target voltage level.

6. The memory control method of claim 1, wherein, Also included are: determining that a threshold voltage of the selected memory location is less than the first target voltage level and within a specified range of the first target voltage level after completing the pre-programming.

7. The memory control method of claim 1, wherein, The selected memory location includes a first memory block associated with a first word line and a second memory block associated with a second word line, and wherein pre-programming the selected memory location and programming the information to the selected memory location comprises: pre-programming the first memory block by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; after pre-programming the first memory block, programming the information to the first memory block; after programming the information to the first memory block, pre-programming the second memory block by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; and after pre-programming the second memory block, programming the information to the second memory block.

8. The memory control method according to claim 7, wherein, Each of the first memory block and the second memory block respectively includes a plurality of first memory cells and a plurality of second memory cells, wherein pre-programming and programming the first memory block and the second memory block comprises: pre-programming the plurality of first memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; after pre-programming the plurality of first memory cells, programming the information to the plurality of first memory cells; after programming the information to the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; and after pre-programming the plurality of second memory cells, programming the information to the plurality of second memory cells.

9. The memory control method of claim 7, wherein, Each of the first memory block and the second memory block respectively includes a plurality of first memory cells and a plurality of second memory cells, wherein pre-programming and programming the first memory block and the second memory block comprises: pre-programming the plurality of first memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; after pre-programming the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses being applied without a program verify operation; after pre-programming the plurality of second memory cells, programming the information to the plurality of first memory cells; and after programming the information to the plurality of first memory cells, programming the information to the plurality of second memory cells.

10. A memory device, comprising: comprises one or more memory cells; a memory controller to manage access to the memory storage array, wherein the memory controller is configured to perform operations comprising: receiving a command to program information to the memory storage array; determining a target memory state to store the information and a target threshold voltage level corresponding to the target memory state; determining one or more programming pulses for a pre-programming pass based at least on the target memory state, including determining a voltage level of the one or more programming pulses based at least on the target threshold voltage level; selecting a memory location in the memory storage array to program the information; pre-programming the selected memory location by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; and programming the information to the selected memory location after the pre-programming; the operations further comprising: receiving a second command to program second information to the memory storage array; determining a plurality of target memory states to store the second information, the plurality of target memory states including a first memory state and a second memory state; determining a plurality of target threshold voltage levels corresponding to the plurality of target memory states, the plurality of target threshold voltage levels including a first target voltage level corresponding to the first memory state and a second target voltage level corresponding to the second memory state, the second target voltage level higher than the first target voltage level; determining one or more second programming pulses based at least on the plurality of target memory states, the one or more second programming pulses including a combined programming pulse for pre-programming the first memory state and the second memory state; calculating voltage levels of the one or more second programming pulses based at least on the plurality of target threshold voltage levels, including calculating a first voltage level of the combined programming pulse, wherein the first voltage level is less than the first target voltage level; selecting a second memory location in the memory storage array to program the second information; pre-programming the second memory location by applying the one or more second programming pulses at respective voltage levels, including applying the combined programming pulse at the first voltage level to pre-program the second memory location for the first memory state and the second memory state, the one or more second programming pulses applied without a program verify operation; and programming the information to the second memory location after pre-programming the second memory location. Programming the information to the selected memory location includes applying one or more additional programming pulses to the selected memory location to reach the target threshold voltage level, the one or more additional programming pulses applied with respective accompanying program verify operations.

11. The memory device of claim 10, wherein, ​ 12. The memory device of claim 10, wherein, Computing voltage levels of the one or more program pulses based at least on the target threshold voltage level includes: determining that the voltage level of the one or more program pulses is less than the target threshold voltage level.

13. The memory device of claim 10, wherein, The operations further include: determining that a threshold voltage of the selected memory location is less than the first target voltage level and within a specified range of the first target voltage level after completing the pre-programming.

14. The memory device of claim 10, wherein, The selected memory location includes a first memory block associated with a first word line and a second memory block associated with a second word line, and wherein pre-programming the selected memory location and programming the information to the selected memory location includes: pre-programming the first memory block by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the first memory block, programming the information to the first memory block; after programming the information to the first memory block, pre-programming the second memory block by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; and after pre-programming the second memory block, programming the information to the second memory block.

15. The memory device of claim 14, wherein, Each of the first memory block and the second memory block includes a plurality of first memory cells and a plurality of second memory cells, respectively, wherein pre-programming and programming the first memory block and the second memory block includes: pre-programming the plurality of first memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the plurality of first memory cells, programming the information to the plurality of first memory cells; after programming the information to the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; and after pre-programming the plurality of second memory cells, programming the information to the plurality of second memory cells.

16. The memory device of claim 14, wherein, Each of the first memory block and the second memory block includes a plurality of first memory cells and a plurality of second memory cells, respectively, wherein pre-programming and programming the first memory block and the second memory block includes: pre-programming the plurality of first memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the plurality of second memory cells, programming the information to the plurality of first memory cells; and after programming the information to the plurality of first memory cells, programming the information to the plurality of second memory cells. After programming the information to the plurality of first memory cells, the information is programmed to the plurality of second memory cells.

17. A memory controller, comprising: Comprise: one or more processors; and one or more machine-readable media storing instructions that, when executed, cause the one or more processors to perform operations comprising: receiving a command to program information to a memory storage array in a memory device, the memory storage array managed by the memory controller; determining a target memory state to store the information and a target threshold voltage level corresponding to the target memory state; determining one or more programming pulses for a pre-programming pass based at least on the target memory state, including determining a voltage level of the one or more programming pulses based at least on the target threshold voltage level; selecting a memory location in the memory storage array to program the information; pre-programming the selected memory location by applying the one or more programming pulses at respective voltage levels, the one or more programming pulses applied without a program verify operation; and after the pre-programming, programming the information to the selected memory location; the operations further comprising: receiving a second command to program second information to the memory storage array; determining a plurality of target memory states to store the second information, the plurality of target memory states including a first memory state and a second memory state; determining a plurality of target threshold voltage levels corresponding to the plurality of target memory states, the plurality of target threshold voltage levels including a first target voltage level corresponding to the first memory state and a second target voltage level corresponding to the second memory state, the second target voltage level higher than the first target voltage level; determining one or more second programming pulses based at least on the plurality of target memory states, the one or more second programming pulses including a combined programming pulse for pre-programming the first memory state and the second memory state; calculating voltage levels of the one or more second programming pulses based at least on the plurality of target threshold voltage levels, including calculating a first voltage level of the combined programming pulse, wherein the first voltage level is less than the first target voltage level; selecting a second memory location in the memory storage array to program the second information; pre-programming the second memory location by applying the one or more second programming pulses at respective voltage levels, including applying the combined programming pulse at the first voltage level to pre-program the second memory location for the first memory state and the second memory state, the one or more second programming pulses applied without a program verify operation; and after pre-programming the second memory location, programming the information to the second memory location.

18. The memory controller of claim 17, wherein, Programming the information to the selected memory location includes applying one or more additional programming pulses to the selected memory location to reach the target threshold voltage level, the one or more additional programming pulses applied with respective accompanying program verify operations.

19. The memory controller of claim 17, wherein, Computing voltage levels of the one or more program pulses based at least on the target threshold voltage level includes: determining that the voltage level of the one or more program pulses is less than the target threshold voltage level.

20. The memory controller of claim 17, wherein, The operations further include: determining that a threshold voltage of the selected memory location is less than the first target voltage level and within a specified range of the first target voltage level after completing the pre-programming.

21. The memory controller of claim 17, wherein, The selected memory location includes a first memory block associated with a first word line and a second memory block associated with a second word line, and wherein pre-programming the selected memory location and programming the information to the selected memory location includes: pre-programming the first memory block by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the first memory block, programming the information to the first memory block; after programming the information to the first memory block, pre-programming the second memory block by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; and after pre-programming the second memory block, programming the information to the second memory block.

22. The memory controller of claim 21, wherein, Each of the first memory block and the second memory block includes a plurality of first memory cells and a plurality of second memory cells, respectively, wherein pre-programming and programming the first memory block and the second memory block includes: pre-programming the plurality of first memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the plurality of first memory cells, programming the information to the plurality of first memory cells; after programming the information to the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; and after pre-programming the plurality of second memory cells, programming the information to the plurality of second memory cells.

23. The memory controller of claim 21, wherein, Each of the first memory block and the second memory block includes a plurality of first memory cells and a plurality of second memory cells, respectively, wherein pre-programming and programming the first memory block and the second memory block includes: pre-programming the plurality of first memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the plurality of first memory cells, pre-programming the plurality of second memory cells by applying the one or more program pulses at respective voltage levels, the one or more program pulses being applied without a program verify operation; after pre-programming the plurality of second memory cells, programming the information to the plurality of first memory cells; and after programming the information to the plurality of first memory cells, programming the information to the plurality of second memory cells. programming the information to the plurality of second memory cells after programming the information to the plurality of first memory cells.

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