Apparatus comprising reconfigurable interface and method of manufacturing the same

Abstract

Disclosed herein is an apparatus including a reconfigurable interface and methods of manufacturing the same. A reconfigurable interface circuit can include an output buffer and an input buffer coupled to a connector for generating and receiving signals, respectively. The reconfigurable interface circuit can include a control circuit configured to control operation of the input and output buffers along with additional circuitry to selectively implement one or more of a set of selectable communication settings.

Description

TECHNICAL FIELD

[0001] The technology is directed to devices, such as semiconductor devices including a memory and a processor, and several embodiments are directed to semiconductor devices including a reconfigurable interface. BACKGROUND

[0002] A device (e.g., a processor, a memory device, a memory system, or a combination thereof) can include one or more semiconductor circuits configured to store and / or process information. For example, the device can include a memory device, such as a volatile memory device, a non-volatile memory device, or a combination device. Memory devices, such as dynamic random access memory (DRAM) and / or high bandwidth memory (HBM), can utilize electrical energy to store and access data.

[0003] As technology in other fields advances and applications increase, the market continues to seek faster, more efficient, and smaller devices. In addition, devices are manufactured to support more and more new devices and new modes of implementation. To meet market demands, semiconductor devices are pushed to the limit and various improvements are made. Generally, improving a device can include increasing circuit density, increasing operating speed or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. However, such improvements often introduce challenges in subsequent data processing, such as due to different requirements related to applicable modes of implementation. SUMMARY

[0004] Aspects of the present disclosure provide a memory device comprising: a connector configured to signal communicate with an external circuit; a variable output source configured to provide a variable driver voltage; an output buffer coupled to the connector and the variable output source, the output buffer configured to generate an output signal based on the variable driver voltage, wherein the output signal is sent to the external circuit through the connector; a variable reference generator configured to provide a variable signal reference; an input buffer coupled to the connector and the variable reference generator, the input buffer configured to receive an input signal from the external circuit through the connector, wherein the input signal is received based on the variable signal reference; and a control circuit configured to control the variable output source, the output buffer, the variable reference generator, the input buffer, or a combination thereof, to selectively configure communication settings for signals exchanged through the connector.

[0005] Another aspect of the disclosure provides a method of operating a semiconductor device, where the method includes accessing a setting indicative of a communication setting of the semiconductor device, and selectively controlling one or more components of the semiconductor device to select, for an exchanged signal, (1) a multi-drop communication configuration or a point-to-point communication configuration, (2) an input communication path and / or an output communication path, (3) a terminated path or an un-terminated path, (4) a single-ended communication configuration or a complementary communication configuration, or a combination thereof, in accordance with the accessed setting. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1A-1E is a description of an example operating environment for a device according to embodiments of the present technology.

[0007] Figure 2A and 2B is a block diagram of an example connection according to embodiments of the present technology.

[0008] Figure 3 is a block diagram of a memory device according to embodiments of the present technology.

[0009] Figure 4 is a block diagram of a reconfigurable interface circuit according to embodiments of the present technology.

[0010] Figures 5A-5D is a block diagram of an example configuration according to embodiments of the present technology.

[0011] Figure 6A and 6B is a flowchart illustrating an example method of manufacturing a device according to embodiments of the present technology.

[0012] Figure 7 is a flowchart illustrating an example method of operating a device according to embodiments of the present technology.

[0013] Figure 8 is a schematic diagram of a system including a device configured according to embodiments of the present technology. DETAILED DESCRIPTION

[0014] As described in greater detail below, the technology disclosed herein relates to apparatuses (e.g., for memory systems) having reconfigurable interface circuits, systems having memory devices, related methods, etc. An apparatus (e.g., a memory device such as an HBM, and / or a system including an HBM) can include a reconfigurable interface circuit, e.g., for communicating test signals. The reconfigurable interface circuit can include input buffers and / or output buffers connected to one or more external connectors (e.g., bumps, pins, pads, etc.) for facilitating communication between one or more external devices and internal functional circuitry. The reconfigurable interface circuit can be configured to selectively support multiple communication settings. For example, the reconfigurable interface circuit can be configured to operate as a single-ended path, an input-only / receive-only path, a power (VDD) terminated path, and / or a multi-point path. Further, the reconfigurable interface circuit can be configured to operate as a single-ended path, an input-only / receive-only path, a non-terminated path, and / or a point-to-point path. Additionally, the reconfigurable interface circuit can be configured to operate as a single-ended path, an input / output combination path, a VDD terminated path, and / or a multi-point path. In some embodiments, the reconfigurable interface circuit can be configured to selectively connect two paths and operate the connected paths to accommodate differential signals, e.g., an input-only path, a VDD terminated path, and / or a multi-point path.

[0015] Conventional devices require predetermined vendor specifications and communication schemes. For example, input buffer types, output buffer types, reference voltage levels, termination configurations, etc. are typically set prior to silicon design. Thus, conventional devices are often designed specifically for a need and are not as flexible in accommodating other implementation modes.

[0016] In contrast, the reconfigurable interface circuit, particularly when providing a test interface, provides the ability for different parties to design / utilize suitable configurations after the device is manufactured without requiring modification of the circuit (e.g., silicon-level modification). For example, the reconfigurable interface circuit can selectively facilitate multi-point or point-to-point connections, single-ended or differential signals, various termination settings, input and / or output communications, or combinations thereof. Thus, the reconfigurable interface circuit provides increased flexibility in operating in different environments, different circuit configurations, different performance criteria, user-specific communication schemes, etc.

[0017] Example Environment

[0018] Figures 1A-1Eis a description of example operating environments for devices in accordance with embodiments of the present technology. The operating environments can include systems that include the devices. In some embodiments, the devices can be included in a system-in-a-package (SiP) device that includes a processor 110 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), etc.) and one or more memory devices 102 (e.g., an HBM) mounted on a support structure 103 (e.g., a package substrate, an interposer, etc.). For example, Figure 1A A first SiP device 100a is described that includes one memory device 102a and one processor 110a mounted on a structure 103a. Figure 1B A second SiP device 100b is described that includes two memory devices 102b1 and 102b2 and one processor 110b mounted on a structure 103b. Figure 1C A third SiP device 100c is described that includes four memory devices 102c1-102c4 and one processor 110c mounted on a structure 103c. Figure 1D A fourth SiP device 100d is described that includes six memory devices 102d1-102d6 and one processor 110d mounted on a structure 103d.

[0019] For purposes of illustration, the devices are described as being implementable across the SiP devices 100a-100b. However, it should be understood that the devices can be implemented in other environments, such as for other systems or devices that include different numbers or arrangements of memory devices and / or processors, or for other circuitry that corresponds to variable potential interface options between communication devices.

[0020] Using the SiP device 100a as an illustrative example, Figure 1E A schematic cross-sectional view of the SiP device 100a taken along line 1E-1E of Figure 1A The SiP device 100 can include a memory device 102 and a processor 110 packaged on a package substrate 114 (e.g., a support structure 103a of Figure 1A The processor 110 can act as a host device for the SiP device 100a.

[0021] In some embodiments, the memory device 102 can be an HBM device that includes an interface die (or logic die) 104 and one or more memory core dies 106 stacked on the interface die 104. The memory device 102 can include one or more through-silicon vias (TSVs) 108 that can be used to couple the interface die 104 and the core dies 106.

[0022] The interposer 112 can provide electrical connections between the processor 110, the memory device 102, and / or the package substrate 114. For example, both the processor 110 and the memory device 102 can be coupled to the interposer 112 through a plurality of internal connectors (e.g., micro bumps 111). The interposer 112 can include channels 105 (e.g., interfaces or connection circuitry) that electrically couple the processor 110 and the memory device 102 through corresponding micro bumps 111. Although only three channels 105 are shown in Figure 1E Although only three channels 105 are shown in FIG. 1, a greater or fewer number of channels 105 can be used. The interposer 112 can be coupled to the package substrate through one or more additional connections (e.g., middle bumps 113, such as C4 bumps).

[0023] The package substrate 114 can provide an external interface for the SiP device 100a. The package substrate 114 can include external bumps 115, some of which can be coupled (e.g., using through-silicon vias (TSVs)) to the processor 110, the memory device 102, or both. The package substrate can further include direct access (DA) bumps that are coupled through the package substrate 114 and the interposer 112 to the interface die 104.

[0024] In some embodiments, a direct access bump 116 (e.g., one or more of the bumps 115) can be organized into a probe pad (e.g., a set of test connectors). An external device, such as a tester, can be coupled to the probe pad in order to directly communicate with the memory device 102. In other words, the external device can send signals to and / or receive signals from the memory device 102 without the signals passing through the processor 110. The tester can be used to preload one or more test patterns into a lookup table of the interface die 104. The tester can then provide one or more test instructions along the direct access terminal 116. The interface die 104 can perform one or more tests on the core die 106 based on the test instructions and the preloaded test patterns, and can generate result information. After performing the tests, the tester can read out the result information through the DA terminal 116.

[0025] The test patterns and instructions can correspond to one or more tests performed on the memory device 102 after the memory device 102 has been packaged into a SiP device. The tests can involve loading data patterns into one or more memory cells of the memory device 102 as part of a write operation, retrieving stored information from the memory cells as part of a read operation, and comparing the write data with the read data. The tests can be performed using a built-in self-test (BIST) circuit of the memory device 102. The tests can be performed using very long test patterns with random characteristics, which can require more storage space than is actually available to the BIST circuit. Such tests can be performed by directly sending the test patterns and instructions through the DA terminal 116.

[0026] Another potential change in the operating environment can include a change in a connection configuration. As described in detail below, a device can be configured to selectively accommodate multiple connection configurations. Figure 2A and 2B is a block diagram of an example connection according to embodiments of the present technology.

[0027] Figure 2A A multi-drop (connection) configuration 200a for a set of memory devices 202al-202a4 (HBMs) is illustrated. In some embodiments, the multi-drop configuration 200a can include a common bus connecting the set of memory devices 202al-202a4. In other embodiments, the multi-drop configuration 200a can include a daisy chain connection between the set of memory devices 202al-202a4.

[0028] Figure 2B A point-to-point (connection) configuration 200b for a set of memory devices 202bl-202b4 (HBMs) is illustrated. For the point-to-point configuration 200b, each memory device can have a direct connection to a corresponding circuit (e.g., a processor 110 of Figure 1E or an external device such as a tester).

[0029] Figure 3 is a block diagram of a memory device 300 (e.g., a memory device 102 or portions thereof of Figure 1E according to embodiments of the present technology. The memory device 300 can include an interface die 304 and one or more core dies 306. For clarity, Figure 3 only a single core die 306 is shown in FIG. 3, it should be understood that multiple core dies 306 can be coupled to the interface die 304 (e.g., there can be 3, 7, or other number of core dies 306).

[0030] The memory device 300 can include different interface terminals for accessing one or more circuits of the core dies 306 and / or the memory. In some embodiments, the different interface terminals can include native micro bumps (uBumps) 305, DA uBumps 316, and / or test interface uBumps 320. The test interface uBumps 320 can be part of a specific interface protocol, such as the IEEE 1500 interface (also referred to as the P1500 interface). In some embodiments, the native uBumps 305 can be included in the uBumps 111 of Figure 1E The native uBumps 305 can be coupled to a processor (e.g., a processor 110 of Figure 1E via one or more connections (e.g., channels 105 of Figure 1EThe local uBump 305 and connection can enable the processor to access information in the core die 306 (e.g., via read or write operations and corresponding information exchange). For example, the core die 306 can receive a command (e.g., a read command) along with address information (AWORD), such as a row address, a column address, a bank address, a die identifier, etc., that specifies a location of a memory access. The AWORD can also include command information, such as a clock signal for operation timing and a command identifier. Access information (DWORD), such as write data or read data, can also be exchanged through the local uBump 305.

[0031] In some embodiments, the interface die 304 can include a serializer 333 configured to process DWORDs between the core die 306 and the local uBump 305. For example, the serializer 333 can receive information in parallel along a first number of data lines (e.g., from the core 306) and then provide the information in serial along a second number of data lines (e.g., to the local uBump 305). The serializer 333 can be used to multiply a number of outputs (e.g., from the core 306) to a fewer number of data lines (e.g., to the local uBump 305).

[0032] In addition to the operational configuration associated with the local uBump 305 (e.g., the local operational mode), the memory device 300 can be configured to operate in a test mode (e.g., a BIST mode or other self-test mode). In the test mode, the memory device 300 can determine one or more characteristics of the memory device 300 (e.g., signal response, manufacturing defects, fault or error related aspects, or other aspects of the circuit). The memory device 300 can utilize the P1500 uBump 320 and / or the DAuBump 316 as a test interface. For example, the P1500 uBump 320 can be used to communicate signals with a host device according to a predetermined sequence or protocol for sending and receiving signals.

[0033] The memory device 300 can use the BIST sequencer 328 (e.g., during the P1500 operational mode) to process signals communicated through the P1500 uBump 320. The P1500 uBump 320 and the BIST sequencer 328 can be coupled to test interface circuitry (e.g., P1500 circuitry) 324 configured to interpret signals according to the P1500 protocol. For example, the P1500 circuitry 324 can translate signals received at the P1500 uBump into signals that can be used by other circuitry of the memory device 300, and vice versa.

[0034] During a test mode (e.g., a BIST mode of operation), instructions can be received to operate the BIST sequencer 328 to perform a test on the memory device 300. The BIST sequencer 328 can generate a test sequence (e.g., a string of logic bits) to write to the memory cells of the core die 306. The BIST sequencer 328 can include a plurality of registers that can be used to store addresses of memory cells to be tested as well as the test sequence. In some embodiments, the test sequence and / or the addresses can be generated within the BIST sequencer 328 based on the instructions. For example, the BIST sequencer 328 can perform a test on a certain address value, increment the address value by one, and then perform the test again. In some embodiments, to conserve space in the BIST sequencer 328, the BIST sequencer 328 can load the test sequence into a lookup table (e.g., a data topology (DTOPO) circuit 330). Each entry in the DTOPO circuit 330 can be associated with a pointer value (e.g., an index value), and in a manner similar to addresses, the BIST sequencer 328 can generate a sequence of pointer values.

[0035] During a write portion of the test, the BIST sequencer 328 can provide address information (e.g., one or more row and column addresses) and a test sequence (e.g., data to be written to the memory cells specified by the address information) to the input buffer 334 (e.g., a register such as a write FIFO (WFIFO)). In some embodiments, the BIST sequencer 328 can provide the address information to the input buffer 334 and can provide index information to the DTOPO circuit 330, which can provide the test sequence to the input buffer 334. Based on the address information provided from the WFIFO 334, the test sequence can be written to the memory cells specified by the address information.

[0036] During a read portion of the test, the BIST sequencer 328 can provide address information to retrieve a test sequence previously stored in the core die 306. The information can be read from the memory cells specified by the address information to the output buffer 335 (e.g., a read FIFO (RFIFO)). The output buffer circuit 335 can generally be similar to the input buffer 334, except that the output buffer 335 can receive information from the core die 306 and then provide it to other circuits of the interface die 304.

[0037] The interface die 304 can include error capture memory (ECM) circuitry 332 configured to generate error-related results based on read test sequences. The ECM circuitry 332 can be coupled to the address information and test sequences provided to the input buffer 334 and include one or more registers for storing write test sequences as well as address information. When read operations are performed, the ECM circuitry 332 can compare read test sequences from the output buffer 335 to test sequences written to those memory cells as part of an earlier write operation. The ECM circuitry 332 can generate results (e.g., indications of mismatches, faulty memory cells, etc.) based on such comparisons. The ECM circuitry 332 can then provide the result information to the P1500 circuitry 324, which can then provide the result information from the memory through the P1500 uBumps.

[0038] In addition to or as an alternative to the P1500 uBumps 320, the memory device 300 can provide access to the core die 306 through DA uBumps 316 (e.g., Figure 1E The memory device 300 can be configured to provide direct access thereto, such as by bypassing other components of the SiP package (e.g., the processor 110) through the DA bumps 316. In some embodiments, these DA uBumps 316 can be organized into probe pads, where an external device (e.g., a probe, a tester) can be coupled to the DA uBumps 316 in order to access the interface die 304 (and through it, the core die 306). For example, the memory device 300 can directly communicate with an external tester through the DA uBumps 316 to implement testing. Signals can be communicated according to the P1500 interface protocol. Thus, the DA uBumps 316 can be used to implement self-testing described above for the P1500 uBumps, such as by DA uBumps 316 load information to and from test circuitry (e.g., the DTOPO circuitry 330 and / or the ECM circuitry 332). Test information can be communicated between the DA uBumps 316 and the P1500 circuitry 324 and then communicated to / from other circuitry as described above.

[0039] As an illustrative example, a test sequence can be loaded into the DTOPO circuit 330 via a DA uBump 316. Each test sequence can represent a string of logic bits that can be provided (serially or in parallel) to the core die. A test sequence can have a number of bits to match the amount of data in one or more DWORDs. In example operation, when loading the DTOPO circuit, the tester can provide a string of bits to the DA uBump 316, which can be routed to the P1500 circuit 324. The P1500 circuit can then provide the bit string to the DTOPO circuit 330, where the bits can be stored.

[0040] The DA uBump 316 facilitates functionality / communication similar to the native uBump 305, for example, for testing purposes. The DA uBump 316 can be used to convey AWORD and DWORD in a manner similar to the native uBump 305. In some embodiments, fewer DA uBumps 316 may be present compared to the presence of the native uBump 305. To mimic signal operation along the native uBump 305, the interface die 304 may include a deserializer circuit 322. The deserializer circuit 322 receives AWORD and DWORD from the DA uBump 316 and then splits the received serial data into multiple parallel channels. In some embodiments, the deserializer circuit 322 may split the AWORD and DWORD into multiple parallel channels corresponding to circuit paths associated with the native uBump 305. In some embodiments, the interface die 304 may include a DA converter 326 configured to route the conveyed information to the core die 306 for testing purposes.

[0041] Even when using different connectors (e.g., native uBump 305, DA uBump 316, and / or P1500 uBump 320), system requirements can still favor different connection configurations based on the overall context. For example, in some embodiments, the SiP may require a multipoint configuration 200a instead of a point-to-point configuration 200b, or vice versa. Furthermore, the same memory device 300 can be implemented or included in different system configurations (e.g., Figures 1A-1D Examples of SiP devices 100a to 100d.

[0042] To adapt to different system configurations, the memory device 300 may include reconfigurable interface circuitry that selectively changes the communication mode of the memory device 300. For example, the reconfigurable interface circuitry may selectively enable the memory device 300 to operate one or more signal paths as transmit and / or receive paths, power-terminated or unterminated paths, single-ended or differential signal paths, multi-point paths, or point-to-point paths, etc. As an illustrative example, Figure 4is a block diagram of a reconfigurable interface circuit 400 according to embodiments of the present technology. The memory device (e.g., Figures 1A-1E HBM 102 of Figure 3 The memory device 300) can include a reconfigurable interface circuit 400 configured to selectively change a communication mode of the memory device 300.

[0043] For purposes of illustration, the reconfigurable interface circuit 400 is described as facilitating communication and functionality for memory testing by Figure 3 DA uBumps 316. However, it should be understood that the reconfigurable interface circuit 400 can be implemented for other paths, such as for communication paths associated with Figure 3 native uBumps 305 of Figure 3 P1500 uBumps 320 of and / or other communication interfaces. Further, it should be understood that the reconfigurable interface circuit 400 can be implemented in other types of devices and / or facilitate other types of signals, such as for normal operations (e.g., read and / or write), internal management operations (e.g., refresh, garbage collection, or other housekeeping operations), etc.

[0044] In some embodiments, the memory device 300 can include the reconfigurable interface circuit 400 in an interface die (e.g., Figure 1E the interface die 104 of Figure 3 the interface die 304 of The reconfigurable interface circuit 400 can be positioned closer to a corresponding interface (e.g., DA uBumps 316) than other / functionality circuitry (e.g., core die 306). For example, the reconfigurable interface circuit 400 can be adjacent to Figure 3 DA uBumps 316 of Figure 3 deserializer 322 of Figure 3 P1500 circuit 324 of Figure 3 BIST sequencer 328 of Thus, internal communication can remain unchanged for functional operations, and the reconfigurable interface circuit 400 can adapt or translate external interfaces according to external / system requirements.

[0045] The reconfigurable interface circuit 400 can include a configuration control circuit 402, an output buffer 404, and an input buffer 406 coupled to an external connector 408 (e.g., one of the uBumps, such as one of the DA uBumps 316). The output buffer 404 can be configured to communicate data to an external device (e.g., a tester) through the external connector 408. The input buffer 406 can be configured to communicate data from an external device through the external connector 408. In other words, the output buffer 404 can be used to send information (e.g., data from the core die 306) out of the memory device, and the input buffer 406 can be used to receive information (e.g., data from a tester) into the memory device.

[0046] The configuration control circuit 402 can include circuitry / logic configured to control communication settings. For example, the configuration control circuit 402 can operate according to predetermined settings stored in a configuration source 410 (e.g., one or more fuses, mode registers, etc.). The configuration control circuit 402 can operate the output buffer 404, the input buffer 406, and / or other circuitry within the reconfigurable interface circuit 400, such as by activating certain circuitry, controlling voltage sources, connecting / disconnecting circuit paths, or combinations thereof.

[0047] In some embodiments, the output buffer 404 can include a pull-up (PU) driver 422 and / or a pull-down (PD) driver 424 that can be operated or activated by the configuration control circuit 402. The PU driver 422 and / or the PD driver 424 can be configured to operate based on an output source 426 (VTT). The PU driver 422 can generate / drive output data using a pull-up resistor, such as by driving a signal from a neutral-low state to high. The PU driver 422 can include on-chip termination circuitry. The PD driver 424 can generate / drive output data using a pull-down resistor, such as by driving a signal from a neutral-high state to low. The configuration control circuit 402 can select or activate one of the PU driver 422 and the PD driver 424 according to the configuration source 410. Further, the configuration control circuit 402 can control the output source 426 to provide different levels, such as a system voltage (VDD) 414, a reduced voltage (e.g., VDD / 2), an open circuit, or other levels.

[0048] The configuration control circuit 402 can control the reference generator 412. The reference generator 412 can be configured to provide a variable reference level for receiving / processing signals. For example, the input buffer 406 can include one port connected to the external connector 408 (e.g., high level input) and one port connected to the reference generator 412 (e.g., low level input). The reference generator 412 can provide a reference level between electrical ground and the system voltage 414. In some embodiments, the reference generator 412 can provide a voltage level lower than electrical ground (e.g., a negative voltage level).

[0049] In some embodiments, the reconfigurable interface circuit 400 can include a coupling mechanism 428 configured to electrically couple a set of interface circuits. For example, the coupling mechanism 428 can electrically couple a set (e.g., two) of external connectors 408 to one of the buffers (e.g., the input buffer 406). Thus, the set of connectors can be used to communicate different portions of a single signal, such as for differential signal transmission. The coupling mechanism 428 can include a switch configured to electrically couple a corresponding set of external connectors (e.g., adjacent uBumps). Alternatively or additionally, the coupling mechanism 428 can include a switch matrix that can be configured to electrically connect a selectable set of external connectors.

[0050] The configuration control circuit 402 can control components in the reconfigurable interface circuit 400 to facilitate a selected communication setting. For example, the reconfigurable interface circuit 400 can activate the output buffer 404 and / or the input buffer 406, control the output source 426, control the reference level, and / or control the coupling structure 428 according to a predetermined setting (e.g., system requirements). Figures 5A-5D is an example configuration according to embodiments of the present technology (e.g., Figure 4 a block diagram of a setting of the reconfigurable interface circuit 400 of

[0051] Figure 5A A first example setting 500a of the reconfigurable interface circuit 400 according to embodiments of the present technology is described. The first example setting 500a can facilitate input-only communication, single-ended signals, signal termination (e.g., VDD termination, ODT, etc.), and / or Figure 2A of the multi-point configuration 200a. For the first example setting 500a, the configuration control circuit 402 can deactivate the output buffer 404, activate the input buffer 406, and / or control the reference generator 412 to provide a higher range of references. In some embodiments, the configuration control circuit 402 can deactivate the output buffer 404 based on activating the PU driver 422, deactivating the PD driver 424, and / or driving the output source 426 to the system voltage 414 (VDD).

[0052] Figure 5BThis describes a second instance configuration 500b of the reconfigurable interface circuit 400 according to an embodiment of the present technology. The second instance configuration 500b facilitates input-only communication, single-ended signaling, no-terminal communication, and / or... Figure 2B The point-to-point configuration is 200b. For the second instance configuration 500b, the configuration control circuit 402 can deactivate the output buffer 404 (e.g., both the PU driver 422 and the PD driver 424), activate the input buffer 406, and / or control the reference generator 412 to provide a lower range reference. Along with deactivating the output buffer 404, the configuration control circuit 402 can further drive the output source 426 to open circuit.

[0053] Figure 5C This describes a third instance configuration 500c of the reconfigurable interface circuit 400 according to an embodiment of the present technology. The third instance configuration 500c facilitates input and / or output communication, single-ended signals, signal termination, and / or... Figure 2A The multi-point configuration 200a. For the third instance configuration 500c, the configuration control circuit 402 can activate the output buffer 404 (e.g., both the PU driver 422 and the PD driver 424), activate the input buffer 406, and / or control the reference generator 412 to provide a higher range reference. Along with activating the output buffer 404, the configuration control circuit 402 can further drive the output source 426 to the system voltage 414.

[0054] Figure 5D The third instance setting 500d of the reconfigurable interface circuit 400 according to an embodiment of the present technology is described. The fourth instance setting 500d may correspond to a differential signal transmission configuration. The fourth instance setting 500d may correspond to a first interface circuit 502 (e.g., electrically coupled to a second interface circuit 504 (e.g., a second instance of the reconfigurable interface circuit 400)). Figure 4 (A first example of a reconfigurable interface circuit 400). Configuration control circuitry 402 controls coupling mechanism 428 of the first interface circuitry 502 and the second interface circuitry 504 to form a cross-connection 506. Cross-connection 506 connects the low port of the active input buffer 406 (e.g., the input buffer of the first interface circuitry 502) to the external connector 408 of the second interface circuitry 504. Configuration control circuitry 402 can disconnect and / or deactivate the reference generator 412 for the first interface circuitry 502 and / or the second interface circuitry 504. In other words, configuration control circuitry 402 can connect a second connector (e.g., another uBump) to the input buffer 406 to facilitate differential signal connection.

[0055] Figure 5D The examples described herein can be further corresponding to promoting Figure 2AThe configuration is a single-input communication, signal terminal, and / or multipoint configuration 200a. Therefore, the configuration control circuit 402 can deactivate the output buffer 404, activate the input buffer 406, and / or deactivate the reference generator 412 of the first interface circuit 502 and / or the second interface circuit 504. In some embodiments, the configuration control circuit 402 can activate the PU driver 422 and deactivate the PD driver for the first interface circuit 502 and / or the second interface circuit 504. Furthermore, the configuration control circuit 402 can further drive the output source 426 to the system voltage 414.

[0056] Figure 6A and 6B This is a flowchart illustrating an example method of manufacturing equipment according to an embodiment of the present technology. Figure 6A Example method 600 of manufacturing apparatus (e.g., SiP apparatus 100a, 100b, 100c and / or 100d) according to embodiments of the present technology.

[0057] At box 602, method 600 may include providing a memory device (e.g., Figures 1A-1E The memory device 102 and / or Figure 3 One or more of the memory devices 300, such as HBM devices. The memory devices may be placed on a platform and / or gripped for subsequent processing.

[0058] As illustrated in box 612, providing a memory device may include providing interface circuitry (e.g., Figure 1E Interface bare die 104, Figure 3 Interface bare die 304 and / or Figure 4 (A reconfigurable interface circuit 400). For example, the provided memory device may include the interface circuit. Furthermore, the provided memory device may include the attachment, adjustment, configuration, or similar processing interface circuitry and / or other related circuitry.

[0059] In some embodiments, providing a memory device and / or interface circuitry may include manufacturing the memory device or a portion thereof, for example, using a silicon-level manufacturing process. Examples of memory device manufacturing processes are described below.

[0060] At block 604, method 600 may include setting a communication configuration for the memory device. In some embodiments, configuration settings for the interface circuitry may be set or written to... Figure 4 In the configuration source 410, for example, through the initial configuration process. For example, specific setting values ​​representing communication settings (e.g., representing...) can be... Figures 5A-5BThe value of one of the instances 500a to 500d or other similar settings is written to one or more fuses, other non-volatile memory, MRS settings, etc. Additionally, setting the communication configuration may include attaching jumpers and / or adjusting pins or other external settings for the memory device, interface circuitry, or both. Alternatively or additionally, the initial communication configuration may be a default setting that can be adjusted or overridden during the deployment / operation of the memory device, such as a value set in the MRS by the processor or external system. The initial communication configuration may be the default setting.

[0061] At block 606, method 600 may include mounting a memory device on an interposer. For example, method 600 may include mounting one or more of memory devices 102 (e.g., HBM) on interposer 112. Mounting the memory device may include aligning the memory device and / or corresponding connector (e.g., uBump) to connection pads on interposer 112 (e.g., with...). Figure 1E Channel 105 and / or Figure 1E (The pads associated with the direct access bump 116). The mounting memory device may further include physical connection structures, such as those by reflow soldering, diffusion bonding, physical and / or chemical adhesives, etc.

[0062] At box 608, method 600 may include a processor (e.g., Figures 1A-1E The processor 110 is mounted on an interposer (e.g., interposer 112). The processor mounting process may be similar to the memory mounting process. For example, bumps on the processor and / or thereon may be aligned with corresponding locations on the interposer. Furthermore, the processor may be physically attached to the interposer. In some embodiments, the processor and memory device may be mounted simultaneously.

[0063] At box 610, method 600 may include mounting an interposer layer on a substrate (e.g., Figure 1E The interposer mounting process may be similar to the device mounting process described above, for example, by combining alignment and physical attachment processes. In some embodiments, the interposer mounting and device mounting processes may occur simultaneously. In other embodiments, the device mounting and insertion mounting processes may occur separately, for example, using different reflow temperatures / durations, different attachment mechanisms or arrangements, etc.

[0064] Figure 6B Instructions for manufacturing memory devices (e.g., Figures 1A-1E The memory device 102 and / or Figure 3An example method 650 for fabricating one or more of the memory devices 300 of FIG. 1. At block 652, the method 650 can include providing interface circuits (e.g., a set of reconfigurable interface circuits 400). As explained in block 662, providing interface circuits can include providing each interface circuit with configurable components (e.g., the control circuit 402, the output buffer 404, etc. described above for the reconfigurable interface circuit 400).

[0065] Providing interface circuits can also include providing each interface circuit with a coupling mechanism (e.g., the coupling mechanism 428), as explained in block 664. The coupling mechanism 428 can include a connection path configured to selectively connect / disconnect an electrical connection, a switch, a multiplexer, a switch matrix, a bus, etc., to selectively form different electrical paths between different endpoints. In some embodiments, the coupling mechanism 428 can be formed to enable selective electrical connections between predetermined or neighboring interface circuits. In other embodiments, the coupling mechanism 428 can be formed (e.g., using a bus and / or a switch matrix) to enable selective electrical connections between predetermined groups of interface circuits or between all available interface circuits.

[0066] At block 656, the method 650 can include providing each interface circuit with a configuration source (e.g., the configuration source 410). As an example, the provided configuration source can include a register, a latch, a non-volatile memory (e.g., a fuse, a flash memory cell, etc.), an adjustable physical configuration (e.g., a dip switch, a set pin), a jumper configuration / receptacle, etc., or a combination thereof.

[0067] Providing circuits and components can include forming silicon-level circuits, such as by doping, depositing metal, masking, removing / planarizing, and / or other silicon-level manufacturing processes. Alternatively or additionally, providing circuits and components can include mounting the circuits onto a device substrate. The circuits can be electrically coupled by one or more traces, wires, connection layers, etc.

[0068] At block 654, the method 650 can include connecting the interface circuits to connectors (e.g., the uBumps of FIG. 2). For example, a set of pads can be formed on a surface of a substrate (e.g., a silicon substrate or a device substrate) based on masking, metalization, and / or other silicon-level manufacturing processes. Pads or other metal connectors can be formed on the pads for electrically connecting the interface circuits to external devices (e.g., the interposer 112).

[0069] Blocks 652 and 654 and / or blocks 661-663 can correspond to one or more processes or aspects for fabricating an interface die (e.g., the interface die 104 of FIG. 1, Figure 1E the interface die 304 of FIG. 3). Figure 3 In some alternative embodiments, the interface die can include wires instead of pads and bumps / connectors as described above.

[0070] At block 658, method 650 may include coupling interface circuitry to functional circuitry (e.g., Figure 1E One or more memory core dies 106 and / or Figure 3 One or more core dies 306). In some embodiments, the core dies may be mounted above the interface dies and electrically coupled to each other, for example, to form a die stack. In other embodiments, the core dies and interface dies may be arranged differently (e.g., one or more dies may be in parallel or embedded in another structure) while remaining electrically coupled to each other. The means resulting from coupling the interface circuitry to the functional circuitry may include a memory device 102 (e.g., HBM).

[0071] Figure 7 This describes an operating device (e.g., a SiP device, a memory device, or a portion thereof) according to embodiments of the present invention. Figure 4 A flowchart of an example method 700 for a reconfigurable interface circuit 400 is provided. At block 702, the device can access communication settings. For example, Figure 4 The control circuit 402 can access Figure 4 The configuration source 410 is used to obtain the settings information stored therein.

[0072] At box 704, the device may select one or more communication configurations. For example, the device may select: (1) a multipoint communication configuration or a point-to-point communication configuration, (2) an input communication path and / or an output communication path, (3) a terminated path or an unterminated path, (4) a single-ended communication configuration or a complementary communication configuration or a combination thereof for exchanging / communicating signals.

[0073] As illustrated in box 706, the selected configuration may correspond to or be implemented by selectively controlling the interface components according to the accessed communication settings. For example, control circuitry 402 may set, adjust, activate / deactivate, connect / disconnect, or similarly operate one or more reconfigurable components within reconfigurable interface circuitry 400 according to the accessed communication settings.

[0074] Selectively, the control interface component may include a control output buffer (e.g., Figure 4 The output buffer 404, as illustrated in block 712, is used. For example, control circuitry 402 can be activated / deactivated according to communication settings. Figure 4 PU driver 422 and / or Figure 4 The PD driver 424. As illustrated in block 714, the control circuit 402 can also control the output driver voltage utilized by the output buffer (e.g., Figure 4the output source 426). For example, the control circuit 402 can set the output source 426 to the system voltage 414 (e.g., VDD or full / high level), an intermediate voltage lower than the system voltage 414, or open circuit.

[0075] Selectively controlling the interface components can further include controlling the input buffers (e.g., Figure 4 the input buffers 406) as explained in block 712 and / or the variable references (e.g., Figure 4 the reference generators 412) as explained in block 712. For example, the control circuit 402 can activate / deactivate the input buffers 406 and / or activate / deactivate the reference generators 412 according to the communication settings. Further, the control circuit 402 can adjust the reference levels / outputs from the reference generators 412 to enable a full / high range (e.g., up to the system voltage 414) or a reduced range of the signal magnitude to be received.

[0076] At block 720, the device can control the coupling mechanisms (e.g., Figure 4 the coupling mechanisms 428) to selectively control the interface components. For example, the control circuit 402 can implement a single-ended path or a complementary path (e.g., a differential signal path) based on controlling the coupling mechanisms. As described above, the control circuit 402 can implement a single-ended path based on operating the coupling mechanisms 428 to connect each input buffer 406 to Figure 4 the corresponding connector 408 and the corresponding reference generator 412. The control circuit 402 can implement a complementary path by coupling one input buffer to a set (e.g., two) of connectors and disconnecting / deactivating / adjusting other components as needed to enable one input buffer to receive and process signals communicated through a set of connectors. An example of a complementary path setting is described above with respect to the example setting 500d of Figure 5D the interface circuit 400.

[0077] At block 722, the device can communicate with an external device according to the settings. For example, the memory device can communicate with a processor and / or external device (e.g., a tester, such as through a P1500 connection and / or DA connection) according to the implemented communication settings. Thus, the reconfigurable interface circuit 400 can enable one device (e.g., the memory device 102) to meet any one of a variety of communication / system requirements as described above. Thus, the reconfigurable interface circuit 400 can provide increased applicability for the memory device 102 and provide a reduction in design / engineering resources otherwise to adapt the device to each unique set of requirements.

[0078] Figure 8 is a schematic diagram of a system including a device according to embodiments of the present technology. The above references to the interface circuit 400 apply to the interface circuit 402. Figures 1A-7Any of the semiconductor devices described can be incorporated into any of a wide array of larger and / or more complex systems, representative examples of which are Figure 8 The system 880 is schematically shown in FIG. 8B. The system 880 can include the semiconductor device 800 ("device 800") (e.g., a semiconductor device, package, and / or assembly), a power source 882, a driver 884, a processor 886, and / or other subsystem or component 888. The device 800 can include features generally similar to those described above. The resulting system 880 can perform any of a wide array of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 880 can include, without limitation, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and home appliances. The components of the system 880 can be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system 880 can also include remote devices and any of a wide array of computer readable media.

[0079] The present disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. As will be understood by one of ordinary skill in the art, various equivalent modifications are possible in the absence of the specific

[0080] Unless the context clearly indicates otherwise, throughout the present disclosure, the singular terms "a," "an," and "the" include plural referents. Similarly, the word "or" as used in this disclosure is understood to cover all of its ordinary meanings, including the exclusive sense (a or b, but not both), unless the context clearly indicates otherwise. Additionally, the terms "comprising," "including," and "having" as used in this disclosure are specifically intended to be read as open-ended terms of art. The term "consisting of" is intended to be interpreted as a functional description of a process or composition, rather than a structural description. As such, the term "consisting of" is intended to mean that the process or composition includes only the recited elements, and does not include any additional elements. The term "consisting essentially of" is intended to mean the recited elements, and any additional elements that do not materially affect the basic and novel characteristics of the process or composition.

Claims

1. A memory device comprising: Connectors configured to communicate signals with external circuitry; A variable output source configured to provide a variable driver voltage; An output buffer coupled to the connector and the variable output source, the output buffer being configured to generate an output signal based on the variable driver voltage, wherein the output signal is transmitted to the external circuitry via the connector; A variable reference generator configured to provide a variable signal reference; An input buffer coupled to the connector and the variable reference generator, the input buffer being configured to receive an input signal from the external circuitry via the connector, wherein the input signal is received based on the variable signal reference. and A control circuit configured to control the variable output source, the output buffer, the variable reference generator, the input buffer, or a combination thereof, to selectively configure communication settings for signals exchanged through the connector.

2. The memory device of claim 1, wherein the control circuitry is configured to control the variable output source, the output buffer, the variable reference generator, the input buffer, or a combination thereof to implement (1) a multi-point communication configuration or a point-to-point communication configuration, (2) an input communication path and / or an output communication path through the connector, (3) a terminated path or an unterminated path through the connector, (4) a single-ended communication configuration or a complementary communication configuration, or a combination thereof.

3. The memory device of claim 2, wherein the control circuitry is configured to selectively configure the communication settings to implement (1) the multi-point communication configuration, (2) the input communication path without the output communication path, (3) the termination path, and (4) the single-ended communication configuration.

4. The memory device of claim 3, wherein the control circuitry is configured to selectively configure the communication configuration based on: (a) activating the termination circuitry in the output buffer, (b) activating the input buffer, (c) controlling the variable output source to provide a system voltage, and (d) controlling the variable reference generator to receive up to the system voltage.

5. The memory device of claim 2, wherein the control circuitry is configured to selectively configure the communication settings to implement (1) the point-to-point communication configuration, (2) the input communication path without the output communication path, (3) the unterminated path, and (4) the single-ended communication configuration.

6. The memory device of claim 5, wherein the control circuitry is configured to selectively configure the communication configuration based on: (a) deactivating the output buffer, (b) activating the input buffer, (c) controlling the variable output source to provide an open-circuit setting, and (d) controlling the variable reference generator to receive a reduced voltage up to less than the system voltage.

7. The memory device of claim 2, wherein the control circuitry is configured to selectively configure the communication settings to implement (1) the multipoint communication configuration, (2) both the input communication path and the output communication path via the connector, (3) the termination path, and (4) the single-ended communication configuration.

8. The memory device of claim 7, wherein the control circuitry is configured to selectively configure the communication settings based on: (a) activating both the pull-up driver and the pull-down driver in the output buffer, (b) activating the input buffer, (c) controlling the variable output source to provide a system voltage, and (d) controlling the variable reference generator to receive up to the system voltage.

9. The memory device according to claim 2, wherein: The connector includes a first connector configured to communicate a first signal with the external circuitry; The input buffer includes a signal port and a reference port, and the input buffer is configured to receive the input signal based on a comparison of the voltages at the signal port and the reference port. Further includes: A second connector, which communicates a second signal with the external circuitry; and A coupling mechanism is connected between (1) the first connector and the signal port of the input buffer, and (2) the variable reference generator and the reference port of the input buffer. The coupling mechanism is selectively operable to couple the input buffer to the second connector for implementing the complementary communication configuration, wherein the first signal and the second signal are complementary signals corresponding to a single information stream.

10. The memory device according to claim 9, wherein: The control circuitry is configured to operate the coupling mechanism to couple the reference port of the input buffer to the second connector instead of the variable reference generator; and Further includes: A first reconfigurable interface circuit for the first connector includes a first output source, a first output buffer, a first reference generator, a first input buffer, a first coupling mechanism, and a first control circuit; and The second reconfigurable interface circuit includes a second output source, a second output buffer, a second reference generator, a second input buffer, a second coupling mechanism, and a second control circuit. The second reconfigurable interface circuit is configured to selectively configure communication settings for signals exchanged via the second connector, wherein the second control circuit is configured to operate the second coupling mechanism to connect the second connector to the first input buffer instead of the second input buffer for the complementary communication configuration.

11. The memory device of claim 10, wherein the first control circuit and the second control circuit are configured to configure the communication settings to implement (1) the multipoint communication configuration, (2) the input communication path without the output communication path, and (3) the termination path for the first and second connectors together with the complementary communication configuration.

12. The memory device of claim 1, wherein the variable output source configured to provide a variable driver voltage is configured to at least selectively provide a system voltage, a reduced voltage below the system voltage, and an open-circuit setting.

13. The memory device according to claim 1, wherein: The output buffer includes A pull-up driver configured to selectively generate the output signal; A pull-down driver configured to selectively generate the output signal; and The control circuitry is configured to activate the pull-up driver, the pull-down driver, or both, based on the selected communication settings.

14. The memory device of claim 13, wherein the pull-up driver comprises on-chip termination circuitry.

15. The memory device of claim 1, further comprising: A configuration source, configured to store settings representing the communication settings; and in: The control circuitry includes logic configured to access the settings and control the variable output source, the output buffer, the variable reference generator, the input buffer, or a combination thereof according to the accessed settings.

16. The memory device of claim 1, wherein the memory device comprises a high-speed memory (HBM) device.

17. The memory device of claim 16, wherein the HBM includes a system-in-package (SiP) device, the SiP device further including a processor coupled to the HBM.

18. The memory device of claim 17, wherein the connector is a direct access connector configured to facilitate direct exchange of information between the external circuitry and the HBM without communication through the processor.

19. A method of operating a semiconductor device, the method comprising: Access settings representing the communication settings of the semiconductor device; and Depending on the access settings, one or more components of the semiconductor device are selectively controlled to select (1) a multi-point communication configuration or a point-to-point communication configuration, (2) an input communication path and / or an output communication path, (3) a terminated path or an unterminated path, (4) a single-ended communication configuration or a complementary communication configuration, or a combination thereof, for communication signals. Selectively controlling one or more components includes: Control the operating state of the output buffer configured to generate an output signal based on a variable driver voltage; and The input buffer is configured to receive input signals from external circuitry within a predetermined voltage range, depending on the operating state of the variable reference control input buffer.

20. The method of claim 19, wherein controlling the operating state of the output buffer includes activating or deactivating the pull-up driver and the pull-down driver; The variable driver voltage is set to the system voltage, an intermediate voltage less than the system voltage, or an open-circuit setting for generating the output signal; and The variable reference is configured to provide a read range up to the system voltage or up to a reduced voltage for receiving the input signal.

21. The method of claim 20, wherein: The input buffer is connected to a first connector configured to receive a first signal; Selectively control one or more components to include Disconnect the input buffer from the variable reference; and The input buffer is connected to a second connector instead of the variable reference, wherein the second connector is configured to receive a second signal complementary to the first signal for conveying a single stream of information.

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