Storage device, controller, and method of operating a storage device

Abstract

A memory device, controller, and method of operating a memory device are provided. The memory device includes a memory array and a memory controller. The memory controller generates read and write commands for the memory array. An error correction code engine for the memory device is operable to use a plurality of different codeword sizes, different code rates, or different error correction code (ECC) algorithms. Logic to apply a selected codeword size, code rate, or ECC algorithm depending on operating conditions of the memory array is included.

Description

Technical Field

[0001] This invention relates to error correction using storage of data in a memory, which may have different error rates depending on the operating conditions of the memory. Background Technology

[0002] In data storage systems, error checking and correction (ECC) algorithms are commonly used to improve reliability. ECC algorithms are more commonly used in integrated circuit memory devices, such as high-capacity NAND and NOR flash memory devices, where the error rate can depend on memory operating conditions, such as temperature, number of write and erase cycles, and access frequency.

[0003] Furthermore, many storage systems require optimizing power consumption and speed while maintaining a specified error rate. Using ECC algorithms, storage systems store codewords that comprise a combination of a data carrier segment and an ECC code segment computed on that data carrier segment. For example, one algorithm computes a codeword with a 4,000-bit data carrier segment plus an ECC code segment computed on that 4,000 bits. Another algorithm computes a codeword with a 2,000-bit data carrier segment plus an ECC code segment computed on that 2,000 bits. Moreover, different ECC algorithms can have different code rates, where the code rate is the size of the data carrier segment divided by the sum of the size of the data carrier segment and the size of the ECC code segment in the codeword, indicating the amount of available data transmitted within a given codeword size. Various codeword sizes and code rates can be used depending on the specific needs of the system.

[0004] The codeword size and code rate can vary depending on the specific ECC algorithm applied. Larger ECC codewords for a given data segment size provide better error protection, but require more power consumption and more complex algorithms that may consume significant processing resources. On the other hand, smaller codewords save power and rely on simpler algorithms, but may offer weaker protection for a given code rate.

[0005] This invention provides a technique for using ECC algorithms more efficiently in terms of power consumption, operating speed, and complexity in data storage systems. Summary of the Invention

[0006] The aforementioned storage technology provides adaptability for ECC algorithms with different codeword sizes and / or different code rates for memory arrays whose error rates can change with operating conditions.

[0007] The error rate may depend on the operating conditions of the storage device. In one aspect, the storage device includes a memory array and a controller disposed in a data path between an input for receiving data and the memory array. The controller includes an Error Correction Code (ECC) engine and adjustment logic. The ECC engine generates codewords for storage in write addresses in the memory array, the codewords including respective data segments and ECC code segments. The ECC engine includes logic for implementing codewords having at least two ECC code rates, and the adjustment logic for mapping the at least two ECC code rates to a log of addresses based on data reliability in addressed memory blocks stored in a plurality of memory blocks, and for selecting one of the at least two ECC code rates using the log, which varies with the address and the operating conditions.

[0008] In one aspect of the storage technology, a memory array includes a plurality of memory blocks, each of which is disposed on a single integrated circuit chip; and a controller including an ECC engine is disposed in a data path between an input terminal for receiving bearer data and the memory array, the ECC engine being used to generate codewords for storage in addresses of addressed memory blocks in the plurality of memory blocks, the codewords comprising respective bearer data segments and ECC code segments, the ECC engine including logic for implementing codewords having at least two ECC code rates. The controller further includes adjustment logic, which is a log mapping at least two ECC code rates to addresses and logic for selecting one of the at least two ECC code rates using the log that varies with address and operating conditions. In this aspect of the technology, the bearer data segment and ECC code segment of a given codeword are stored together in the same block of the memory array. In some embodiments, the bearer data segment and ECC code segment of a given codeword are stored together on the same page of the same block of the memory array.

[0009] In various aspects of the storage technology, the storage device includes a memory array and a memory controller operatively connected to the memory array. The memory controller generates read and write commands for the memory array. The ECC engine for the storage device includes logic operable to implement multiple different ECC algorithms, which may result in the use of different codeword sizes, different code rates, and different correction capabilities. It includes logic that applies a selected codeword size, code rate, or ECC algorithm depending on the operating conditions of the memory array.

[0010] In one approach, the memory controller includes logic for counting accesses to portions of the memory array, and the operating conditions include counting accesses to portions of the memory array to which codewords are to be written.

[0011] In another approach, a temperature sensor or other environmental sensor accessible to the memory controller is included. The operating conditions in this approach may include the sensor's output, which may indicate the operating temperature of the memory array or a portion of the memory array that is accessed.

[0012] In another implementation, the memory controller includes wear leveling logic applied to the high-density flash memory, which identifies data as hot or cold data based on monitored memory block durability (e.g., the number of write and erase cycles in blocks of the memory array) and data access frequency in the flash memory. Operating conditions may include wear leveling status and hot or cold data.

[0013] In some embodiments, the memory controller includes logic for recording the codeword size, code rate, or ECC algorithm selected for the logical address corresponding to the physical address, and stores this mapping table in a portion of the flash memory array space.

[0014] In another aspect, the memory array may include portions for "hot" data storage and portions for "cold" data storage, with high and low access frequencies, respectively. The operating conditions applied in the selection of the ECC algorithm, codeword size, or code rate may include whether the address portion is specified for "hot" or "cold" data.

[0015] In a storage technology described in this invention, the memory array may include a first subarray and a second subarray. In one embodiment, the memory array may include a high-density flash memory on an integrated circuit, having logic for operating the first subarray on the integrated circuit to store one bit per memory cell and for operating the second subarray on the integrated circuit to store more than one bit per memory cell. For example, the memory controller may be programmably applied to select an ECC algorithm for accessing the first subarray, and different programs may be applied to select an ECC algorithm for accessing the second subarray as discussed above.

[0016] Furthermore, the memory controller can execute a program to move a data set from a first subarray to a second subarray, and during the execution of the program, change the ECC algorithm applied to the data set.

[0017] Generally, a method for operating a storage device is described, comprising writing a data set to a memory array. The process of writing the data set includes identifying a portion of the memory array storing codewords of the data set, and determining operating conditions for the identified portion. The process may include selecting an ECC algorithm from a plurality of ECC algorithms, which may have different codeword sizes or code rates depending on the determined operating conditions. When selecting an ECC algorithm, one or more codewords are computed using the selected ECC algorithm for the data set. Then, the computed one or more codewords are written to the identified portion or portion of the memory array.

[0018] The method may also include reading a specific codeword from an addressed portion of the memory array; mapping the addressed portion of the memory array to an ECC algorithm selected for the addressed portion; and applying the selected ECC algorithm to check for errors in the specific codeword.

[0019] The technology utilizes "adaptive ECC". The non-volatile memory controller can contain a configurable ECC engine that supports a number of different types of ECC codewords, "n". Smaller ECC codewords save power and reduce the number of logic gates. Larger ECC codewords offer better protection strength but require more additional space and involve higher power consumption and a larger number of logic gates.

[0020] Further details and advantages of the technology will become apparent after reviewing the following drawings, detailed description, and claims. Attached Figure Description

[0021] Figure 1 This is a block diagram of a storage device having a memory array and a memory controller, the storage device including a multi-mode ECC engine as described in this invention.

[0022] Figure 2 To show with Figure 1 A diagram of the ECC rate log and memory structure of a storage device similar to the storage device.

[0023] Figure 3 An example of a memory array is shown, the memory array comprising components configured with... Figure 1 The system is similar to a system with multiple NAND memory chips in multiple channels.

[0024] Figure 4 An example of a memory structure is shown, which includes blocks suitable for use in pages of a storage device as described in this invention.

[0025] Figure 5 A simplified block diagram of a memory array comprising a first subarray and a second subarray, according to one aspect of the technology.

[0026] Figure 6 This is a flowchart illustrating the operation of the logic in one aspect of a memory controller that selects the ECC algorithm in the write procedure.

[0027] Figure 7 A flowchart illustrating the operation of the ECC algorithm based on one aspect of the technology.

[0028] Figure 8 A flowchart illustrating the operation of selecting the ECC algorithm according to another aspect of the technology.

[0029] Figure 9 A flowchart illustrating an operation for generating codewords in a memory array comprising a first subarray and a second subarray, according to one aspect of the art.

[0030] Figure 10 For self-possession such as Figure 9 The flowchart shown illustrates the process of reading data from a memory array containing a first subarray and a second subarray, resulting in generated codewords.

[0031] Figure 11 This shows the SLC region operating in circular buffer mode.

[0032] Figure 12 To write data to and Figure 11 The flowchart in the SLC region is similar to that in the SLC region.

[0033] Explanation of reference numerals in the attached figures

[0034] 100: Storage System

[0035] 101: Host Interface

[0036] 102a, 102b: Subarrays

[0037] 103: Processor

[0038] 104: Buffer

[0039] 105: Scrambler

[0040] 106: Multi-mode ECC engine

[0041] 107: NAND interface

[0042] 108: Temperature sensor

[0043] 109: Mapping Table

[0044] 110, 220: Memory array

[0045] 201, 204, 206: Bus

[0046] 202, 203: Signal lines

[0047] 205, 306: NAND interface

[0048] 210: Log

[0049] 215: ECC Level Diagram

[0050] 221: Peripheral Circuits

[0051] 250: Pseudo-single-order unit SLC block

[0052] 251: Third-order unit TLC block

[0053] 310, 311, 321, 322, 323: NAND flash chips

[0054] 401: Plane

[0055] 410: Block

[0056] 420: Main Area

[0057] 421: Backup Area

[0058] 501: First subarray

[0059] 502: Second subarray

[0060] 600, 601, 603, 604, 605, 606, 700, 701, 702, 703, 704, 705, 706, 707, 710, 800, 801, 802, 803, 804, 900, 901, 902, 903, 904, 905, 906, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1200, 1202, 1203, 1204, 1205, 1211, 1212, 1213, 1214, 1215, 1220: Steps

[0061] 602: Operating Condition Monitor

[0062] 1100: SLC Block

[0063] 1101: Write pointer

[0064] 1102: ECC Level changes pointer

[0065] BLK 0, BLK 2, ... BLK n-1: Block address / block

[0066] Ch(0), Ch(1), ..., Ch(N-1): Data channels Detailed Implementation

[0067] refer to Figures 1 to 12 A detailed description of embodiments of the provided technology.

[0068] Figure 1 This is a block diagram of an example storage system 100 including a memory controller and a memory array. In this example, storage system 100 can operate as a solid-state drive. This technology can be applied to other types of storage systems utilizing ECC technology.

[0069] Figure 1 The storage system 100 illustrated includes a host interface 101 connected to a host system that can generate read and write commands for carrying data sets using logical addresses. Furthermore, the storage system 100 includes a memory array 110, which may include an integrated circuit non-volatile memory device, or such as... Figure 1 The diagram illustrates multiple integrated circuit non-volatile memory devices. In the illustrated examples, the integrated circuit non-volatile memory devices may include high-density flash memory having a NAND array architecture, a NOR array architecture, or other array architecture. Furthermore, the integrated circuit non-volatile memory devices may include multiple subarrays. In the illustrated examples, subarray 102a is used for single-level cell (SLC) operations where each cell stores one bit, and subarray 102b is used for multiple-level cell (Multiple-Level Cell) operations, such as triple-level cell (TLC), where each cell stores more than one bit.

[0070] In this example, a memory controller is connected between the host interface 101 and the memory array 110. The memory controller may include one or more processors 103 to execute memory programs, such as wear leveling, logic-to-physical address translation, arbitration of accesses to the memory array 110, read access counts to maintain hot and cold data classification, program and erase counts to maintain portions of the memory array, etc. The memory controller may include a buffer 104, for example implemented using DRAM or SRAM, which can be accessed by one or more processors 103. In some embodiments, the memory controller includes a scrambler 105 that communicates data streams with one or more processors 103 and the buffer 104. Figure 1The memory controller illustrated includes a multi-mode ECC engine 106, which includes logic for implementing multiple ECC algorithms with different codeword sizes and code rates suitable for a particular embodiment. The multi-mode ECC engine 106 may include a state machine implemented using dedicated logic circuitry, configurable logic circuitry, a general-purpose processor executing software, or otherwise. In some embodiments, the multi-mode ECC engine 106 may be implemented using a processor program executed by one or more processors 103. The memory controller may implement, for example, a Flash Translation Layer (FTL) protocol to translate host read and write commands carrying data into commands accessible via flash memory physical addresses for reading and writing ECC codewords.

[0071] exist Figure 1 In the configuration, the multi-mode ECC engine 106 communicates with the NAND interface 107 via data stream (when the memory array 110 is implemented using NAND architecture integrated circuits). The NAND interface 107 may include circuitry for executing input / output protocols for integrated circuit memory devices within the memory array 110, including logic for providing commands and physical addresses for read, write, and erase operations within the memory array 110. A "write" operation to non-volatile memory may be a "programming" operation, or a combination of programming and erasing operations.

[0072] The memory controller may also maintain a log, such as a mapping table 109 in memory or other types of logic circuitry or programs, which maps the entity address (e.g., block address) of the codeword to a selected ECC algorithm used to generate the codeword.

[0073] The memory array 110 can be characterized by error rates in different portions of the memory array 110, which vary under different operating conditions. Operating conditions can be reflected by: operating temperature; wear leveling parameters provided by a wear leveling procedure; write / erase cycles and the access frequency (including reads) maintained in the memory controller; error rates periodically detected by the read and copy return procedures of blocks of memory cells in array 110 (for data that is not frequently changed); certain memory operations, such as moving a data set from one subarray (e.g., an SLC subarray) to a different subarray (e.g., a TLC subarray); or other conditions that can be represented by signals applied to the memory controller or data provided to the memory controller. Figure 1In the memory system 100, a temperature sensor 108 (or other type of environmental sensor) provides data to the memory controller, which can indicate the temperature or other environmental conditions for the operation of the memory array 110 or a portion thereof, and is used by logic in the memory controller to select the ECC algorithm, code rate, or codeword size.

[0074] Many categories of ECC algorithms are suitable for use in this technology. Examples of ECC algorithm categories include the Low-Density Parity Check (LDPC) algorithm (also known as the Gallagher algorithm), the Hamming algorithm, the Reed-Solomon algorithm, and the Bose-Chaudhuri-Hocquenghem (BCH) algorithm. Algorithms of a single category can be tuned to achieve different error detection and correction capabilities, different code rates, and different codeword sizes by changing the parameters used to compute the codewords. Therefore, for the purposes of this specification, one category of algorithms can be used to implement the logic of multiple ECC algorithms by using different parameters of the ECC algorithm in the memory controller (e.g., in the multi-mode ECC engine 106). Furthermore, more than one category of algorithms can be used to implement the logic of multiple ECC algorithms in the memory controller. The reliability of data stored in each memory array, typically in non-volatile memory, is determined by a combination of parameters, such as the memory array temperature, the number of program / erase cycles, the number of read cycles, the erase time, the read time, the temperature, and the threshold voltage of the memory cells. These parameters are used to more robustly reflect the actual data reliability in each memory array, thereby enhancing the reliability of the data.

[0075] refer to Figure 1The memory controller described in the example includes logic for executing a program for operating the memory, the program including reading and writing codewords in a memory array, wherein the codewords are combined to form a data set used in a host processor. The program executed in this scenario may include writing the data set to the memory array, including identifying a portion of the memory array and determining operating conditions for the identified portion; selecting an ECC algorithm from a plurality of ECC algorithms with different codeword sizes or code rates, depending on the determined operating conditions and the identified portion of the array; using the selected ECC algorithm for the data set to compute one or more codewords; and writing the computed one or more codewords to the identified portion of the memory array. Furthermore, the program executed in this scenario may include reading a specific codeword from an addressed portion of the memory array; mapping the addressed portion of the memory array to the ECC algorithm selected for the addressed portion; and applying the selected ECC algorithm to check for errors in the specific codeword. See reference... Figure 1 The logic described or otherwise configured to execute the program. For example, the memory controller and memory array may be part of a single integrated circuit.

[0076] Figure 2 A portion of the storage system technology shown has an ECC rate log and memory architecture. In this example, the data carrier provides input on bus 201 to a multi-mode ECC engine 106. Furthermore, operating conditions are transmitted as input on signal line 202 to the multi-mode ECC engine 106, as described above. The multi-mode ECC engine 106 uses an ECC rate selected from log 210 to generate codewords for storage in memory array 220. The multi-mode ECC engine 106 is used for data stream communication across bus 204 with NAND interface 205, which manages access to one or more integrated circuit memory devices. In the illustrated embodiment, NAND interface 205 is used for data communication across bus 206 with the integrated circuit containing memory array 220. In this embodiment, for example, the processor 103 in the controller further includes adjustment logic to adapt to the data reliability of the memory array 220. This logic can adjust the corresponding ECC code rate based on one or more parameters of the operating conditions or the history of one or more parameters. These parameters include: a number of programming / erasing cycles, a number of read cycles, an erase time, a read time, temperature, and the threshold voltage of the memory cell, etc., to maintain data reliability under different operating conditions, which is more consistent with the actual data reliability of each memory array.

[0077] In this example, memory array 220 is a NAND flash memory disposed on a single integrated circuit having peripheral circuitry 221, which includes a command decoder, an address decoder, and other circuitry necessary for memory operations within memory array 220. Furthermore, in this example, the memory is organized on a single integrated circuit into multiple blocks, labeled as block address BLK 0, block address BLK 1, block address BLK 2, ..., block address BLK n-1. These multiple blocks can be organized for the purposes of this example into multiple pseudo-single-level cell (SLC) blocks 250 comprising blocks with addresses BLK 0 and BLK 1, and multiple three-level cell (TLC) blocks 251 for the purposes of this example comprising blocks with addresses BLK 2 to BLK n-1. The multiple blocks may include memory cells implemented using the same technology, which operate as single-level cells in some blocks and as multi-level cells (e.g., three-level cells) in other blocks. In other instances, multiple blocks may be contained within memory cells of different types or variations within blocks of different types.

[0078] As described in this invention, a memory block is a portion of physical memory that can be identified by a block address. A block address is a portion of the address used to access data in a memory array. For example, a memory address may contain 38 bits to identify the storage location of individual bits stored in the memory array. Of these 38 bits, several higher-order bits identify a memory plane on the integrated circuit chip, such as two higher-order bits; several first intermediate-order bits identify an individual block within the memory plane (e.g., 16 intermediate-order bits); several second intermediate-order bits identify an individual page within the individual block (e.g., 12 intermediate-order bits); and several lower-order bits identify individual bits within the individual page (e.g., 8 lower-order bits). In some embodiments, an individual page within a block may include an extended (or spare) area typically used to maintain metadata associated with the data in the individual page. The block address contains address bits in the memory address sufficient to uniquely identify the block. The logical and physical configuration of blocks depends on a variety of factors, including the specific type of memory, write and erase algorithms, and the manufacturing techniques applied, and therefore can vary from one type of memory array to another.

[0079] like Figure 2As shown, the multi-mode ECC engine 106 is coupled to log 210 via signal line 203. Log 210 may be stored in a memory such as a register file, SRAM, DRAM, PCRAM, or flash memory, which stores a mapping of block addresses to ECC rates, where the ECC rate is indicated by the parameter ECC LEVEL# shown in the figure. Different blocks may have different ECC rates. As mentioned above, the multi-mode ECC engine 106 may have resources for executing multiple different ECC algorithms and implementing multiple different rates. Each ECC LEVEL may indicate one of the algorithms selected for implementing a selected rate. As shown in the figure, each of the blocks in memory array 220 with block addresses BLK0, BLK1, BLK2, ..., BLKn-1 has a corresponding entry in log 210. In this example, as indicated by ECC LEVEL Figure 215, SLC blocks BLK 0 and BLK 1 may have an ECC LEVEL for determining the corresponding memory level. This ECC LEVEL may be fixed as ECC LEVEL 5 as indicated in the figure or any other arbitrary value, or it may be dynamically determined using a different procedure than that applied to other blocks (see, for example, below). Figures 11 to 12 ).

[0080] Figure 3 Showing with Figure 1 The system configuration is similar to that of the system in which the memory array includes multiple NAND flash memory chips coupled to NAND interface 306, and the NAND interface 306 is connected to... Figure 1 Similar to NAND interface 107. In this configuration, NAND interface 306 provides communication with multiple data channels Ch(0), data channel Ch(1), ... data channel Ch(N-1). Each data channel is coupled to multiple NAND flash chips. Thus, as shown, channel Ch(N-1) is coupled to a set of NAND flash chips 321, 322, 323... Channel Ch(0) is coupled to a set of NAND flash chips including NAND flash chip 310. Channel Ch(1) is coupled to a set of NAND flash chips including NAND flash chip 311. Figure 3 Each NAND flash chip in the system may contain one or more blocks. For example, for a NAND flash chip with megabit storage capacity, the chip may contain 4 planes, each plane having 1438 blocks, each block having 1536 pages, and each page having 16,384 primary region bits and 2048 spare region bits.

[0081] Figure 4 The structure of a 3D NAND flash array on a single integrated circuit is shown, supporting multi-mode ECC operation as described in this invention. In this example, plane 401 comprises multiple blocks (e.g., 410). Each block comprises multiple pages, wherein each page comprises a main region 420 and a spare region 421, the spare region 421 typically used to store metadata. When writing codewords as described in this invention, both the bearer data segment and the ECC code segment of the codeword may be written in the same physical block, and in some embodiments, in the same physical page. In embodiments where ECC codewords are written on physical pages, the bearer data segment and the ECC code segment may be written consecutively in the main region. In other embodiments where ECC codewords are written on physical pages, the bearer data segment may be written in the main region of the page, and the ECC code segment may be written in the spare region of the page. In another embodiment, codewords with different code rates are stored so that they can be retrieved in a single read operation on a single chip, such as a single-page read operation, or in consecutive read operations using consecutive addresses from consecutive pages of a memory array. In the illustrated example, the ECC level or bitrate is set based on the block address. In other embodiments, the ECC level or bitrate may be set based on a combination of block address and page address for some or all blocks in the memory array.

[0082] Figure 5 This illustration shows a memory array including a first subarray 501 and a second subarray 502. In this example, the first subarray 501 includes multiple single-level cell (SLC) blocks and the second subarray 502 includes multiple three-level cell (TLC) blocks, presenting a configuration deployed as a high-density NAND flash integrated circuit device and potentially deployable as other types of memory devices. In some embodiments, the SLC blocks and TLC blocks may be implemented on the same integrated circuit. In some embodiments, the SLC blocks and TLC blocks are statically configured and may have different memory cell structures or different read / program / erase algorithms to accommodate per-cell or per-cell multi-bit operations. In other embodiments, an array of memory cells suitable for multi-level cell operations is provided, and blocks in the first subarray can be dynamically selected for SLC operations, sometimes referred to as pseudo-SLC blocks. SLC blocks can have faster access times and larger operational tolerance potential offsets compared to multi-level cell blocks. Therefore, in some instances, for a given amount of data, SLC blocks can achieve a higher ECC code rate (more data per codeword) and fewer codeword operations compared to TLC blocks. Thus, in embodiments with this feature, the operating condition for selecting the ECC algorithm can be whether the entity address points to an SLC block or a TLC block.

[0083] Figure 6 In order to be with Figure 1 A simplified flowchart of the program implemented in a memory controller similar to the memory controller. Figure 6 In the process, a write command is received at the memory controller (step 600). The memory controller receives input from the operating condition monitor 602 and selects an ECC level using the algorithm of the multi-mode ECC engine application to be used, in order to implement it at the selected ECC bit rate (step 601). The selected ECC level can also be a function of the physical address of the data to be written in the memory array.

[0084] After selecting an ECC level (step 601), the multi-mode ECC engine uses the selected ECC level to generate a codeword to be written to the memory array (step 603). Next, the codeword is written to the memory array (step 604). Furthermore, the selected ECC code rate is recorded in a table to map physical addresses to codewords, and the selected ECC code rate is written to the selected ECC level to generate a codeword (step 605). Then, the process is complete. Figure 6 The flowchart (step 606).

[0085] Figure 7 This is a flowchart of a procedure executed by the memory controller to select an ECC level in response to operating conditions. In this example, multiple ECC levels are characterized by different ECC code rates, where the ECC code rate is equal to n / n+k for an ECC codeword with an n-bit native bearer data segment and a k-bit redundant ECC code data segment.

[0086] exist Figure 7 In the procedure, the flow begins at step 700. An initial ECC code rate is set to the maximum code rate (step 701), which is typically associated with lower error correction capability and higher throughput. The procedure periodically or from time to time probes pages in the memory array to detect bit counts, which are corrected by ECC operations (step 702) or other operating conditions (bit flips). These probes can be performed using read and copy-back operations. Bit flip information can be accumulated to form a statistical measure “m” (step 703). For example, in a memory array comprising subarrays with multiple blocks, the statistical measure may be the average of the number of bit flip counts on the word lines of the block set in the earliest accessed subarray. In other embodiments, the statistical measure may be simply the bit flip count on a single word line, which generally reflects the operating conditions of the array or a portion of the array.

[0087] Next, the statistical measurement m is compared with the threshold TH (step 704). If the measurement m is greater than the threshold TH, the ECC algorithm branches to the procedure of selecting the next ECC code rate (step 705). Next, it is determined whether the ECC code rate parameter (e.g., ECC LEVEL#) in decreasing form is less than or equal to the minimum value, corresponding to the lowest ECC code rate that can be used for a specific portion of the memory array (step 706). In one approach, the ECC code rate can be decreased by one, and if the decreasing ECC code rate parameter is not set at the minimum value, the ECC algorithm changes to an algorithm that supports the next code rate (step 707) and the algorithm ends (step 710). If the ECC code rate parameter is less than or equal to the minimum value at step 706, the ECC algorithm with the minimum code rate is set or maintained (step 707), and the flowchart ends (step 710).

[0088] Figure 8 This is a flowchart of another procedure executed by the memory controller to select an ECC algorithm in response to operating conditions of the memory array, wherein in this example, the operating conditions are indicated by an environmental sensor, such as a temperature sensor. The algorithm begins at step 800. In this procedure, the output of the temperature sensor is used to calculate a statistical parameter “TA ratio”, which is equal to HT / (HT+LT), where HT is the high temperature sensed during the interval, and LT is the low temperature sensed during the interval (step 801). In this way, a higher TA ratio indicates a larger temperature fluctuation during the interval, and a lower TA ratio indicates a smaller temperature fluctuation during the interval. Next, the TA ratio is periodically checked against a threshold (step 802). If it exceeds the threshold TH, a new ECC level is adopted by changing the bit rate (step 803), and the flowchart ends (step 804). If the TA ratio does not exceed the threshold TH, the same ECC level can be maintained, and the flowchart ends (step 804).

[0089] Available Figure 8 Other algorithms and other statistical parameters corresponding to temperature include, for example, raw temperature measurements of the environment in which the integrated circuit memory device is in use or in which the memory system is deployed.

[0090] Figure 9 This is a flowchart of a write procedure for a memory array having SLC subarrays and TLC subarrays (or multi-level cell subarrays), which can be executed by the memory controller. Figure 9 The procedure begins at step 900, receiving a write command. The command is processed to determine the location of the entity containing the data to be written, including whether the target is an SLC block (step 901). If the target entity address is within an SLC block, the SLC ECC LEVEL set for the operation (e.g., as in...) is used. Figure 2The codeword is generated using ECC LEVEL 5 (step 903). If the target entity address is not in the SLC block at step 901, the ECC mode can be determined as ECC LEVEL n based on the operating conditions (step 902). The selected ECC mode is recorded in a mapping table, which corresponds to the entity address ECC LEVEL n in the corresponding position, and the selected ECC mode is used to generate the ECC codeword (step 904). After the codeword is generated at step 903 or step 904, the codeword is written to the entity address in the SLC block or TLC block when appropriate (step 905), and the flowchart ends (step 906).

[0091] The memory array has multiple subarrays, such as SLC subarrays and TLC (or multilevel cell) subarrays. Taking advantage of the difference in access time between SLC and TLC subarrays, the SLC subarray can be operated as a cache memory. Moving data between SLC and TLC subarrays is part of the cache management operation, which can be implemented by a processor program executed by the processor. Figure 1 In storage systems. For example... Figure 10 As illustrated, the write procedure for moving data between SLC and TLC subarrays or between TLC and SLC subarrays can be executed in a manner that causes the ECC LEVEL to change as data moves between subarrays.

[0092] Figure 10 This is a flowchart of a read procedure for a memory array having SLC and TLC subarrays, which can be executed by the memory controller. Figure 10 The procedure begins by receiving a read command (step 1000). The command is processed to determine the Physical Block Address (PBA) and whether the target is an SLC block (step 1001). If, at step 1001, the target physical address is an SLC block, the SLC ECC mode is determined (step 1003), and a codeword is output from the array (step 1005) for ECC processing. If, at step 1001, the target physical address is a TLC block, the ECC mode is determined from the log that maps the ECC mode to the physical block address (step 1002). Next, the ECC mode indicated by the log is established (step 1004), and a codeword is output from the memory array for ECC processing (step 1005). After outputting the codeword, Figure 10 The procedure shown in the figure is completed (step 1006).

[0093] In some embodiments, the SLC region can be treated as a circular buffer to operate a memory device containing both SLC and MLC regions. This can be achieved through the memory controller (e.g., Figure 1 The circular buffer manager is executed in the flash transition layer logic of the processor 103 or other control nodes in the system. Figure 11 This is a simplified illustration of accessing SLC block 1100 in response to write pointer 1101. Each new codeword is written to the physical block address identified by write pointer 1101, and the write pointer is incremented. When the write pointer increments to the end of the array, it wraps back to the beginning and continues in a circular buffer configuration. A scrap collection procedure or other program can be executed to keep the next block after the write pointer ready to receive new codewords. For example, an SLC block holding valid data in the area after the write pointer can be copied to an MLC block, and the SLC block can be erased to free it for writing new codewords. In this way, write pointer 1101 should not overflow, resulting in the rewriting of valid data.

[0094] For dynamic control of ECC LEVEL in the SLC region, which operates as a circular buffer, the system can also maintain the ECC LEVEL change pointer 1102. The dynamic selection of the ECC LEVEL for each write to the SLC region can be performed by determining the operating conditions of the block in the SLC at the time of writing. If it is determined that the ECC LEVEL should change based on the current operating conditions, the ECC LEVEL change pointer 1102 is moved to the current write pointer 1101 position, and the new ECC LEVEL is applied to all ongoing blocks until the ECC mode is updated in response to a change in conditions.

[0095] For read operations, the SLC block to be read is compared with ECC LEVEL change pointer 1102. For reads within the SLC region located clockwise (to the right) between ECC LEVEL change pointers 1102 and ECC LEVEL change to ECC LEVEL n+1, ECC LEVEL n+1 is applied to check for erroneous codewords. For reads within the SLC region located counterclockwise (to the left) in the circular buffer addressed between ECC LEVEL change pointer 1102 and the current write pointer 1101, the previous ECC LEVEL n is applied to check for erroneous codewords.

[0096] In this example, only two regions of the SLC circular buffer are defined for the purpose of applying different ECCs. These regions can be defined by the ECC LEVEL change pointer 1102 as discussed above. Ultimately, the SLC block written using the earlier ECC LEVEL n will be freed through scrap collection or otherwise for use with the new ECC LEVEL n+1. The first ECC region includes the block at the ECC LEVEL change pointer and blocks clockwise up to the latest valid SLC block, all of which will be written after the change. The second ECC region includes the block before the ECC LEVEL change pointer and blocks counterclockwise up to the oldest valid block. In some embodiments, more than one ECC LEVEL change pointer can be maintained, dividing the SLC circular buffer into more than two regions.

[0097] Figure 12 For example, references Figure 11 The flowchart describes the memory write operation of the SLC circular buffer. Figure 12 In the process, a write command is received (step 1200). It is determined whether a write command is hit in the SLC region of the memory (step 1202). If not, an ECC mode is determined based on the MLC operation conditions of the Physical Block Address (PBA) used for writing (step 1203). A codeword is generated using the determined ECC mode (step 1204). The codeword is then written at the physical block address, and the ECC mode for the physical block is written to the log (step 1205). At this point, the write operation ends (step 1220).

[0098] If a hit is determined in step 1202 within the SLC circular buffer region, the ECC mode number is determined based on the general operating conditions of the SLC or the operating conditions of the selected block in the SLC (step 1211). Next, it is determined whether the current ECC mode number changes based on the operating conditions (step 1212). If it changes, the current ECC mode changes, and the ECC mode change pointer is moved to the write pointer position (step 1213). If the ECC mode does not change at step 1212 or after the ECC mode change (step 1213), an ECC codeword is generated using the current ECC mode (step 1214). Then, the codeword is written to the entity block address of the write pointer in the SLC region (step 1215). Finally, the algorithm ends (step 1220). This is an example of logic used to operate a first subarray (e.g., an SLC region) as a circular buffer and to change the ECC rate based on a first change in the operating conditions when a current write operation is performed, and to apply the changed ECC rate to subsequent writes in the first subarray until a second change in the operating conditions is determined. This is an example of a method used to operate the first subarray as a circular buffer and maintain a write pointer and an ECC level change pointer; to change the ECC rate based on a change in the operating conditions when a write operation is performed, and to update the ECC level change pointer to the write pointer; and to apply a selected ECC rate based on the position of the read address relative to the ECC level change pointer.

[0099] This invention describes several flowcharts illustrating logic executed via a memory controller or a memory device. The logic can be implemented using a processor programmed with a computer program stored in memory accessible to the computer system, and can be executed via a processor including a field-programmable integrated circuit, dedicated logic hardware, or a combination of dedicated logic hardware and a computer program. As with all the flowcharts in this invention, it will be understood that many steps can be combined, performed in parallel, or in different sequences without affecting the achieved function. In some cases, as the reader will understand, reconfiguration of steps will achieve the same result, provided that certain other changes are also made. In other cases, as the reader will understand, reconfiguration of steps will achieve the same result, provided certain conditions are met. Furthermore, it will be understood that the flowcharts in this invention only illustrate steps relevant to understanding the invention, and it should be understood that numerous additional steps for implementing other functions can be performed before, after, and between the illustrated steps.

[0100] Although the invention has been disclosed with reference to the preferred embodiments and examples detailed above, it should be understood that these examples are intended to be illustrative rather than restrictive. Various modifications and combinations will readily occur to those skilled in the art, and such modifications and combinations will be within the spirit of the invention and the scope of the appended claims.

Claims

1. A memory device whose error rate can depend on operating conditions, characterized in that, The memory device includes: a memory array including a plurality of memory blocks, each of the plurality of memory blocks disposed on a single integrated circuit chip; and a controller disposed in a data path between an input to receive data and the memory array, the controller including an Error Correction Code Engine (ECC Engine) to generate codewords stored in addresses in addressed memory blocks of the plurality of memory blocks, the codewords including respective data segments and ECC code segments, the ECC Engine including logic to implement the codewords with at least two ECC code rates; wherein the controller further includes adjustment logic to select one of the at least two ECC code rates in dependence on data reliability stored in the addressed memory blocks of the plurality of memory blocks, the adjustment logic mapping the at least two ECC code rates to addresses and logic to select one of the at least two ECC code rates using the mapping that varies with the addresses and the operating conditions.

2. The memory device of claim 1, wherein, The ECC Engine includes logic to process read codewords with different ECC code rates from read addresses in the memory array, the memory device including logic to determine the ECC code rate of a read codeword from the mapping.

3. The memory device of claim 1, wherein, includes logic to count accesses to portions of the memory array, and the operating conditions include the access count.

4. The memory device of claim 1, wherein, includes a temperature sensor, and the operating conditions include an output from the temperature sensor.

5. The memory device of claim 1, wherein, includes wear leveling logic that maintains data regarding endurance of portions of the memory array, and maintains the operating conditions, where the operating conditions include the endurance data.

6. The memory device of claim 1, wherein, includes program / erase cycle logic that maintains data regarding program / erase cycle counts of portions of the memory array, and maintains the operating conditions, where the operating conditions include the program / erase cycle counts.

7. The memory device of claim 1, wherein, The addresses include physical block addresses of blocks of the plurality of blocks, and the mapping maps the physical block addresses to ECC code rates.

8. The memory device of claim 1, wherein, The blocks of the plurality of blocks each include a plurality of pages, and wherein the codewords are stored in respective pages.

9. The memory device of claim 1, wherein, The memory array includes a first subarray and a second subarray, including logic to apply a set of ECC code rates to addresses in the first subarray.

10. The memory device of claim 9, wherein, The first subarray and the second subarray are on a single integrated circuit, and the memory device includes logic to operate the first subarray to store one bit per cell and to operate the second subarray to store multiple bits per cell.

11. A controller for use between a non-volatile memory array and a host data source for read and write commands that use physical addresses of the non-volatile memory array, the controller comprising: The controller includes: An Error Correction Code Engine (ECC engine) in a data path between an input to receive data and the memory array, the ECC engine to generate codewords, the codewords stored at addresses in an addressed memory block in the non-volatile memory array, the codewords including respective data segments and ECC code segments, the ECC engine including logic to implement the codewords with at least two ECC code rates; and adjustment logic to select one of the at least two ECC code rates as a function of data reliability stored in the addressed memory block in the plurality of memory blocks; wherein the adjustment logic is to map the at least two ECC code rates to a log of addresses and logic to select one of the at least two ECC code rates using the log as a function of the addresses and operating conditions.

12. The controller of claim 11, wherein, logic to generate the write command to write the codeword in the addressed memory block and the read command to read a codeword using a read address and to process the read codeword from the non-volatile memory array, wherein the read codeword has a different ECC code rate, including logic from the log to determine the ECC code rate of a read codeword.

13. The controller of claim 11, wherein, logic to count accesses to a portion of the non-volatile memory array, and the operating condition includes the access count.

14. The controller of claim 11, wherein, logic to include a temperature sensor coupled to the non-volatile memory array, and the operating condition includes an output from the temperature sensor.

15. The controller of claim 11, wherein, wear leveling logic to maintain endurance data regarding the non-volatile memory array and to maintain the operating condition, wherein the operating condition includes endurance data.

16. The controller of claim 11, wherein, program / erase cycle logic to maintain data regarding program / erase cycle counts for portions of the non-volatile memory array and to maintain the operating condition, wherein the operating condition includes program / erase cycle counts.

17. The controller of claim 11, wherein, the non-volatile memory array includes a first sub-array and a second sub-array, including logic to operate the first sub-array as a circular buffer and to change the ECC code rate based on a first change in operating conditions when performing a write operation and to apply the changed ECC code rate to writes in the first sub-array until a second change in operating conditions is determined.

18. The controller of claim 17, wherein, logic to operate the first sub-array to store one bit per cell and to operate the second sub-array to store multiple bits per cell.

19. An operating method for a storage device whose error rate can depend on operating conditions, characterized in that, The operating method includes: identifying a portion of a memory array and determining operating conditions for the identified portion; selecting an ECC algorithm from a plurality of ECC algorithms having different code rates depending on the identified portion and the determined operating conditions; generating one or more codewords using the selected ECC algorithm stored in the identified portion; mapping portions of the memory to a corresponding selected ECC algorithm in a mapping table that maps different ECC algorithms to addresses of the memory array; and writing the one or more codewords into the identified portion of the memory array according to the selected ECC algorithm.

20. The method of operation of claim 19, wherein, comprising: reading a particular codeword from an addressed portion of the memory array; determining the selected ECC algorithm mapped to the addressed portion; and applying the selected ECC algorithm to check the particular codeword for errors.

21. The method of claim 19, wherein, The memory array includes a first subarray and a second subarray, comprising operating the first subarray as a circular buffer and maintaining a write pointer and an ECC level change pointer; changing an ECC code rate according to a change in operating conditions when performing a write operation, and updating the ECC level change pointer to the write pointer; and applying the selected ECC code rate based on a location of a read address relative to the ECC level change pointer.

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