Method for improving threshold voltage stability of super junction devices after electron irradiation

Abstract

The application provides a method for improving threshold voltage stability of a super-junction device after electron irradiation, comprising the following steps: S1, providing a substrate, wherein a super-junction structure and a gate structure are formed on the substrate; S2, forming an interlayer dielectric layer on the substrate, and forming a contact hole in the interlayer dielectric layer; S3, performing germanium ion implantation to form a silicon amorphous layer at the bottom of the contact hole; S4, sequentially forming an adhesion layer and a metal layer in the contact hole; S5, forming a passivation layer on the interlayer dielectric layer, and performing a first annealing treatment; and S6, performing electron irradiation and executing a second annealing treatment. By performing germanium ion implantation to form a silicon amorphous layer at the bottom of the contact hole, the defect recombination center and the contact resistance stability are improved, so that the threshold voltage stability of the super-junction device after subsequent electron irradiation is significantly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for improving the threshold voltage stability of a superjunction device after electron irradiation. Background Technology

[0002] Fast recovery superjunction devices, with their shorter body diode turn-off recovery time, can reduce system power consumption and increase device switching speed in end-use applications. This device is of great significance for reducing power consumption and increasing the operating speed of circuit systems.

[0003] Electron irradiation can introduce hole recombination centers in the N-type epitaxial layer of fast recovery superjunction devices, thereby reducing the hole lifetime of the body diode: during the body diode turn-off process, it reduces the reverse recovery charge (Q) of the body diode. rr This reduces the reverse recovery peak current (I0). rrm ) and reverse recovery time (T rr This reduces shutdown oscillations.

[0004] Electron irradiation introduces hole recombination centers in the N-type epitaxial layer and also introduces a net positive charge near the gate oxide layer, leading to a decrease in the threshold voltage (V) of the fast recovery superjunction device. th () dropped significantly. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for improving the threshold voltage stability of superjunction devices after electron irradiation, in order to solve the problem of a significant drop in the threshold voltage of superjunction devices caused by electron irradiation in the prior art.

[0006] To achieve the above and other related objectives, this application provides a method for improving the threshold voltage stability of a superjunction device after electron irradiation, comprising:

[0007] Step S1: Provide a substrate on which a superjunction structure and a gate structure are formed;

[0008] Step S2: An interlayer dielectric layer is formed on the substrate, and contact holes are formed in the interlayer dielectric layer;

[0009] Step S3: Germanium ion implantation is performed to form an amorphous silicon layer at the bottom of the contact hole;

[0010] Step S4: An adhesive layer and a metal layer are sequentially formed in the contact hole;

[0011] Step S5: A passivation layer is formed on the interlayer dielectric layer, and a first annealing treatment is performed;

[0012] Step S6: Perform electron irradiation and then perform a second annealing process.

[0013] Preferably, the germanium ion implantation energy is 20 keV-50 keV, and the dose is 1E14 atoms / cm. 2 -1E15atoms / cm 2 .

[0014] Preferably, the temperature of the first annealing treatment is 380℃-420℃, and the duration is 25min-35min.

[0015] Preferably, the absorbed dose of electron irradiation is 200-260 kgy.

[0016] Preferably, the temperature of the second annealing treatment is 330℃-360℃, and the duration is 80min-100min.

[0017] Preferably, a physical vapor deposition process is used to sequentially form an adhesive layer and a metal layer within the contact hole.

[0018] Preferably, the adhesive layer is made of any one or a mixture of titanium nitride, titanium, tantalum nitride, and tantalum.

[0019] Preferably, the material of the metal layer is aluminum.

[0020] Preferably, the passivation layer is made of silicon-rich silicon nitride.

[0021] Preferably, after step S6, a step of thinning the back side of the substrate is further included.

[0022] As described above, the complete method for improving the threshold voltage stability of superjunction devices after electron irradiation provided in this application has the following beneficial effects: by implementing germanium ion implantation, an amorphous silicon layer is formed at the bottom of the contact hole, improving the stability of defect recombination centers and contact resistance, thereby significantly improving the stability of the threshold voltage of the superjunction device after subsequent electron irradiation. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 The flowchart shown is a method for improving the threshold voltage stability of superjunction devices after electron irradiation, as provided in an embodiment of this application. Detailed Implementation

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0026] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0030] Electron irradiation is a lifetime control technique that improves the fast recovery performance of superjunction devices. It reduces the lifetime of minority carriers (holes) by introducing hole recombination centers in the N-type epitaxial layer of the superjunction device, thereby reducing the peak reverse recovery current and reverse recovery time of the superjunction device.

[0031] Research has revealed that electron irradiation excites electron-hole pairs in the gate oxide layer. Electrons flow out of the gate under the influence of an electric field, while holes move towards the interface of the N-type epitaxial layer / gate oxide layer through transitions. The hole mobility is much smaller than that of electrons and cannot be discharged through the gate electrode. When the holes move to the vicinity of the interface of the N-type epitaxial layer / gate oxide layer, they interact with defects at the interface to form fixed charges in the oxide layer and interface state charges. This introduces a net positive charge near the gate oxide layer, resulting in a significant drop in the threshold voltage of the superjunction device.

[0032] During mass production, it was discovered that several batches of electron-irradiated superjunction devices exhibited significant deviations in threshold voltage, leading to a decrease in product yield. Specifically, the threshold voltage of superjunction devices at the wafer edges was lower. Testing of the threshold voltage of electron-irradiated superjunction devices from different wafers revealed no differences in other performance parameters. Therefore, the channel resistance of the electron-irradiated superjunction devices did not show any abnormalities.

[0033] To address this issue, this application provides a method for improving the threshold voltage stability of superjunction devices after electron irradiation.

[0034] Please see Figure 1 The flowchart illustrates a method for improving the threshold voltage stability of superjunction devices after electron irradiation, as provided in an embodiment of this application.

[0035] like Figure 1 As shown, the method for improving the threshold voltage stability of superjunction devices after electron irradiation includes the following steps:

[0036] Step S1: Provide a substrate on which a superjunction structure and a gate structure are formed;

[0037] Step S2: An interlayer dielectric layer is formed on the substrate, and contact holes are formed in the interlayer dielectric layer;

[0038] Step S3: Germanium ion implantation is performed to form an amorphous silicon layer at the bottom of the contact hole;

[0039] Step S4: An adhesive layer and a metal layer are sequentially formed in the contact hole;

[0040] Step S5: A passivation layer is formed on the interlayer dielectric layer, and a first annealing treatment is performed;

[0041] Step S6: Perform electron irradiation and then perform a second annealing process.

[0042] In step S1, optionally, the substrate is a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate, etc.; or the substrate material may also include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material according to the type of device structure formed on the substrate, therefore the type of substrate should not limit the scope of protection of this invention.

[0043] The superjunction structure consists of alternating N-type pillars (N-type epitaxial layers) and P-type pillars (P-type epitaxial layers). The superjunction structure is usually used as the drift region of the superjunction device. The superjunction device includes multiple device unit structures, and each device unit structure is usually formed on the surface of the superjunction structure.

[0044] The gate structure in the device unit structure consists of a gate oxide layer and a gate polysilicon layer stacked from bottom to top. For example, the gate structure is disposed on an N-type epitaxial layer, and the source region is disposed in a P-type epitaxial layer outside the gate structure.

[0045] In step S2, the material of the interlayer dielectric layer may be, but is not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constant (<3.9).

[0046] For example, a deposition process, such as plasma-enhanced chemical vapor deposition, is used to form an interlayer dielectric layer.

[0047] For example, contact holes are formed in the interlayer dielectric layer by an etching process. First, photoresist is formed on the interlayer dielectric layer by a coating process. Then, the photoresist is exposed and developed to form a photoresist layer with a contact hole pattern. Next, using the photoresist layer with the contact hole pattern as a mask, contact holes are formed in the interlayer dielectric layer by etching. Finally, the photoresist layer is removed by an ashing process.

[0048] In step S3, for example, the energy of germanium ion implantation is 20 keV-50 keV, and the dose is 1E14 atoms / cm. 2 -1E15atoms / cm 2 .

[0049] An amorphous silicon layer is formed at the bottom of the contact hole by germanium ion implantation. The thickness of this amorphous layer is easily controlled, and the number of voids is reduced, thus stabilizing the contact resistance. The interface between this amorphous layer and the crystalline epitaxial layer is narrower, resulting in a lower density of secondary defects left at the interface after subsequent annealing.

[0050] Compared to existing technologies, by implementing germanium ion implantation, an amorphous silicon layer is formed at the bottom of the contact hole (metal / semiconductor contact interface), which improves the stability of defect recombination centers and contact resistance, thereby significantly improving the stability of the threshold voltage of the superjunction device after subsequent electron irradiation.

[0051] For example, the amorphous layer covers the source region of the superjunction device.

[0052] In step S4, for example, an adhesive layer and a metal layer are sequentially formed in the contact hole using a physical vapor deposition process. The adhesive layer covers the sidewalls and bottom of the contact hole, and the metal layer fills the contact hole.

[0053] Optionally, the adhesive layer is made of any one or a mixture of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), and tantalum (Ta), and the metal layer is made of aluminum. For example, the thickness of the metal layer is 3 μm-5 μm, preferably 4 μm.

[0054] In step S5, for example, a passivation layer is formed using a deposition process, such as plasma-enhanced chemical vapor deposition.

[0055] Optionally, the passivation layer can be made of silicon-rich silicon nitride (SRN).

[0056] For example, the temperature of the first annealing treatment is 380°C-420°C, preferably 400°C; the duration is 25 min-35 min, preferably 30 min.

[0057] By performing the first annealing treatment, the stress in the passivation layer can be released and defects can be repaired.

[0058] In step S6, the absorbed dose of electron irradiation is 200KGY-260KGY (KGY refers to 1000 joules of energy absorbed by 1 kg of irradiated material), preferably 240KGY.

[0059] For example, the temperature of the second annealing treatment is 330°C-360°C, preferably 350°C; the duration is 80 min-100 min, preferably 90 min.

[0060] By implementing a second annealing process, some energy level defects can be repaired, which can both reduce the reverse recovery time and ensure the stability of the reverse recovery.

[0061] After completing step S6, the back side of the substrate is thinned. For example, the thinning process includes: wafer incoming inspection, film application, grinding, and wafer ripping.

[0062] The wafer incoming inspection process involves using a high-powered microscope to randomly sample wafers to check for surface defects. The wafer lamination process involves placing the wafer carrier into a laminator, which automatically picks up the wafer and applies adhesive film to the front side to protect it from scratches during grinding. The grinding process involves placing the laminated wafer into a grinding machine, which automatically picks it up and places it on a loading stage for rough and fine grinding to achieve the required thickness and surface roughness. The wafer removal process involves placing the ground wafer into a wafer remover, which automatically picks it up and peels off the adhesive film from the front side of the wafer.

[0063] After the thinning process is completed, a drain region is formed on the back side of the substrate. For example, an N+ doped region is formed on the back side of the substrate as the drain region using an ion implantation process.

[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] In summary, the method for improving the threshold voltage stability of superjunction devices after electron irradiation provided in this application forms an amorphous silicon layer at the bottom of the contact hole (metal / semiconductor contact interface) by implementing germanium ion implantation, thereby improving the stability of defect recombination centers and contact resistance, and thus significantly improving the stability of the threshold voltage of the superjunction device after subsequent electron irradiation. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0066] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for improving the threshold voltage stability of a superjunction device after electron irradiation, characterized in that, The method includes: Step S1: Provide a substrate on which a superjunction structure and a gate structure are formed; Step S2: An interlayer dielectric layer is formed on the substrate, and a contact hole is formed in the interlayer dielectric layer; Step S3: Germanium ion implantation is performed to form an amorphous silicon layer at the bottom of the contact hole, which improves the stability of the defect recombination center and contact resistance, thereby improving the stability of the threshold voltage of the superjunction device after subsequent electron irradiation. Step S4: An adhesive layer and a metal layer are sequentially formed in the contact hole; Step S5: A passivation layer is formed on the interlayer dielectric layer, and a first annealing treatment is performed; Step S6: Perform electron irradiation and then perform a second annealing process.

2. The method according to claim 1, characterized in that, The germanium ion implantation energy is 20 keV-50 keV, and the dose is 1E14 atoms / cm. 2 -1E15atoms / cm 2 .

3. The method according to claim 1, characterized in that, The temperature of the first annealing treatment is 380℃-420℃, and the duration is 25min-35min.

4. The method according to claim 1, characterized in that, The absorbed dose of the electron irradiation is 200-260 kgy.

5. The method according to claim 1, characterized in that, The second annealing treatment is performed at a temperature of 330℃-360℃ for a duration of 80 min-100 min.

6. The method according to claim 1, characterized in that, The adhesive layer and the metal layer are sequentially formed inside the contact hole using a physical vapor deposition process.

7. The method according to claim 1 or 6, characterized in that, The adhesive layer is made of any one or a mixture of titanium nitride, titanium, tantalum nitride, and tantalum.

8. The method according to claim 1 or 6, characterized in that, The material of the metal layer is aluminum.

9. The method according to claim 1, characterized in that, The passivation layer is made of silicon-rich silicon nitride.

10. The method according to claim 1, characterized in that, After step S6, a step of thinning the back side of the substrate is also included.

Images