Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application relates to a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises the following steps: providing a substrate; forming an initial groove in the substrate; performing ion implantation on the substrate at the bottom of the initial groove to form an ion implantation area; performing a thermal oxidation treatment on the substrate to form a bottom sacrificial layer with an arc-shaped bottom at the bottom of the initial groove; and removing the bottom sacrificial layer to obtain a groove with an arc-shaped bottom. The semiconductor structure preparation method can reduce the side push of the groove, thereby ensuring that the key size of the structure obtained based on the subsequent process technology of the groove meets the requirements, and can avoid the problem of sharp end discharge caused by the existence of sharp corners at the bottom of the groove, and can better protect the gate when the groove is used as a gate groove.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the continuous improvement of semiconductor process technology, the feature size of the device is also continuously scaled down, and the corresponding device trench size is also smaller. Because the shape of the trench bottom corner is usually a shape with sharp corners, it will cause the phenomenon of sharp tip discharge at the trench bottom corner after applying voltage. Therefore, after trench etching, further rounding etching of the trench bottom is usually required.

[0003] When the general process performs trench rounding etching, an isotropic etching gas is usually used to etch the trench bottom to remove the sharp corners. However, this method has limitations when the trench critical dimension is reduced to a certain size. For example, when the trench bottom is rounded by using an isotropic etching gas, the side push amount of the trench is relatively obvious, which will seriously affect the size of the trench and cannot meet the size requirement of the trench. SUMMARY

[0004] Therefore, it is necessary to provide a preparation method of a semiconductor structure and the semiconductor structure to solve the problem that the side push amount of the trench is relatively obvious when the trench bottom is rounded by using an isotropic etching gas.

[0005] To achieve the above-mentioned purpose, in one aspect, the present application provides a preparation method of a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming an initial trench in the substrate;

[0008] performing ion implantation on the substrate at the bottom of the initial trench to form an ion implantation region;

[0009] performing thermal oxidation treatment on the substrate to form a bottom sacrificial layer with an arc-shaped bottom at the bottom of the initial trench;

[0010] removing the bottom sacrificial layer to obtain a trench with an arc-shaped bottom.

[0011] In one embodiment, after the initial trench is formed in the substrate, before the ion implantation is performed on the substrate at the bottom of the initial trench, the method further comprises:

[0012] forming a covering sacrificial layer covering at least the sidewall and the bottom of the initial trench;

[0013] After the ion implantation is performed on the substrate at the bottom of the initial trench, before the thermal oxidation treatment is performed on the substrate, the method further comprises:

[0014] removing a cover sacrificial layer on a bottom of the initial trench.

[0015] In one embodiment, the removing the bottom sacrificial layer further comprises:

[0016] removing a cover sacrificial layer on a sidewall of the initial trench.

[0017] In one embodiment, the forming the initial trench in the substrate further comprises:

[0018] forming a mask layer on a surface of the substrate, the mask layer having an opening therein, the opening defining a shape and a position of the initial trench;

[0019] etching the substrate based on the mask layer to form the initial trench in the substrate;

[0020] wherein the cover sacrificial layer also covers a surface of the mask layer away from the substrate;

[0021] the removing the cover sacrificial layer on the bottom of the initial trench further comprises:

[0022] removing the cover sacrificial layer on the surface of the mask layer away from the substrate;

[0023] after the removing the bottom sacrificial layer and the cover sacrificial layer, the method further comprises:

[0024] removing the mask layer.

[0025] In one embodiment, the cover sacrificial layer is formed by a chemical vapor deposition process.

[0026] In one embodiment, after the removing the bottom sacrificial layer to obtain a trench with an arc-shaped bottom, a portion of ion implantation region is reserved in the substrate at the bottom of the trench.

[0027] In one embodiment, after the removing the bottom sacrificial layer to obtain a trench with an arc-shaped bottom, the method further comprises:

[0028] forming a gate oxide layer on sidewalls and a bottom of the trench, a thickness of the gate oxide layer at the bottom of the trench being greater than a thickness of the gate oxide layer at the sidewalls of the trench.

[0029] In one embodiment, after the removing the bottom sacrificial layer to obtain a trench with an arc-shaped bottom, the method further comprises:

[0030] Forming a gate oxide layer on the sidewall and the bottom of the trench, and forming a gate conductive layer in the trench; the thickness of the gate oxide layer on the bottom of the trench is greater than the thickness of the gate oxide layer on the sidewall of the trench.

[0031] In one of the embodiments, the forming a gate oxide layer on the sidewall and the bottom of the trench, and forming a gate conductive layer in the trench comprises:

[0032] Forming a gate oxide material layer on the sidewall of the trench, the bottom of the trench and the substrate;

[0033] Forming a gate conductive material layer in the trench and on the surface of the gate oxide material layer;

[0034] Removing the gate conductive material layer on the substrate and the gate oxide material layer on the substrate to obtain the gate conductive layer and the gate oxide layer.

[0035] The application further provides a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of the above embodiments.

[0036] The method for preparing a semiconductor structure according to the application forms an initial trench in a substrate, performs ion implantation in the substrate at the bottom of the initial trench to form an ion implantation region, and then performs a thermal oxidation treatment on the substrate. Since the ion implantation damages the crystal lattice of the ion implantation region at the bottom of the initial trench, oxygen is more likely to reach the bottom of the initial trench and react with the substrate to obtain a bottom sacrificial layer during the thermal oxidation treatment. Moreover, since the ions implanted at both ends are sputtered at the bottom corner during the ion implantation, part of the ions are sputtered to the sidewall. Therefore, the ion implantation depth of the ion implantation region in the middle region is greater than the ion implantation depth of the ion implantation region in the two end regions. Under the action of the subsequent thermal oxidation, the bottom sacrificial layer formed is further rounded along the morphology of the ion implantation region. Therefore, the bottom sacrificial layer with an arc-shaped bottom can be formed at the bottom of the initial trench. After the bottom sacrificial layer is removed, a trench with an arc-shaped bottom can be obtained, which avoids the problem of sharp end discharge caused by the existence of sharp corners at the bottom. When the trench is used as a gate trench, the gate can be better protected. Moreover, compared with the conventional scheme of directly etching the bottom of the trench by using an isotropic etching method to realize the rounding of the bottom of the trench, the method for preparing a semiconductor structure according to the application can reduce the side push of the trench, and thus can ensure that the critical dimension of the structure obtained based on the trench in the subsequent process meets the requirements.

[0037] The semiconductor structure of the present application is prepared by the preparation method of the semiconductor structure described above, and the semiconductor structure comprises a trench with an arc-shaped bottom, which can reduce the occurrence of device leakage and better protect the gate; and the trench size is not affected by the preparation process, so as to ensure that the key size of the structure obtained based on the trench in subsequent process technology meets the requirements. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0039] Figure 1 A flowchart of the preparation method of the semiconductor structure provided in an embodiment;

[0040] Figure 2 A cross-sectional structure schematic diagram of the structure obtained in step S11 in the preparation method of the semiconductor structure provided in an embodiment;

[0041] Figure 3 A cross-sectional structure schematic diagram of the structure obtained in step S121 in the preparation method of the semiconductor structure provided in an embodiment;

[0042] Figure 4 A cross-sectional structure schematic diagram of the structure obtained in step S122 in the preparation method of the semiconductor structure provided in an embodiment;

[0043] Figure 5 A cross-sectional structure schematic diagram of the structure obtained in the step of forming a covering sacrificial layer covering at least the sidewall and the bottom of the initial trench in the preparation method of the semiconductor structure provided in an embodiment;

[0044] Figure 6 A cross-sectional structure schematic diagram of the structure obtained in step S13 in the preparation method of the semiconductor structure provided in an embodiment;

[0045] Figure 7 A cross-sectional structure schematic diagram of the structure obtained in the step of removing the covering sacrificial layer located at the bottom of the initial trench in the preparation method of the semiconductor structure provided in an embodiment;

[0046] Figure 8 A cross-sectional structure schematic diagram of the structure obtained in step S14 in the preparation method of the semiconductor structure provided in an embodiment;

[0047] Figure 9A cross-sectional structure schematic diagram of a structure obtained in step S15 in the method for manufacturing a semiconductor structure provided in an embodiment;

[0048] Figure 10 A cross-sectional structure schematic diagram of a structure obtained in the step of removing the mask layer in the method for manufacturing a semiconductor structure provided in an embodiment;

[0049] Figure 11 A cross-sectional structure schematic diagram of a structure obtained in step S161 in the method for manufacturing a semiconductor structure provided in an embodiment;

[0050] Figure 12 A cross-sectional structure schematic diagram of a structure obtained in step S162 in the method for manufacturing a semiconductor structure provided in an embodiment;

[0051] Figure 13 A cross-sectional structure schematic diagram of a structure obtained in step S163 in the method for manufacturing a semiconductor structure provided in an embodiment.

[0052] BRIEF DESCRIPTION OF DRAWINGS

[0053] 1, substrate; 2, mask layer; 21, opening; 3, initial trench; 4, covering sacrificial layer; 5, ion implantation region; 6, bottom sacrificial layer; 7, trench; 8, gate oxide layer; 81, gate oxide material layer; 9, gate conductive layer; 91, gate conductive material layer. DETAILED DESCRIPTION

[0054] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0056] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.

[0057] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0058] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, use of the term "and / or" includes any and all combinations of associated items.

[0059] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0060] To form a better trench bottom rounding profile while reducing the trench sidewall side push, the application provides a method for preparing a semiconductor structure, as shown in Figure 1 The method for preparing a semiconductor structure can include the following steps:

[0061] S11: providing a substrate;

[0062] S12: forming an initial trench in the substrate;

[0063] S13: performing ion implantation on the substrate at the bottom of the initial trench to form an ion implantation region;

[0064] S14: performing thermal oxidation treatment on the substrate to form an arc-shaped bottom sacrificial layer at the bottom of the initial trench;

[0065] S15: removing the bottom sacrificial layer to obtain an arc-shaped trench.

[0066] Specifically, the ion implantation refers to accelerating ions by an electric field and then implanting the ions into the substrate, the crystal lattice of the material in the ion implantation region is destroyed, and the depth of ion implantation near the middle region of the ion implantation region is greater than the depth of ion implantation near the two end regions; while forming the bottom sacrificial layer at the bottom of the initial trench by performing thermal oxidation treatment on the substrate, an oxide layer is also formed on the sidewall of the initial trench, and the thickness of the bottom sacrificial layer is much greater than the thickness of the oxide layer formed on the sidewall of the initial trench, because during the thermal oxidation treatment, oxygen is more likely to reach the bottom to react along the fractured crystal lattice, so the thickness of the bottom sacrificial layer formed is much greater than the thickness of the oxide layer formed on the sidewall of the initial trench. The implanted ions can include but are not limited to at least one of phosphorus ions, arsenic ions and antimony ions.

[0067] The preparation method of the semiconductor structure in the above embodiment forms an initial trench in the substrate, performs ion implantation in the substrate at the bottom of the initial trench to form an ion implantation region, and then performs thermal oxidation treatment on the substrate. Due to the ion implantation, the lattice of the ion implantation region at the bottom of the initial trench is easily damaged, and oxygen is more likely to reach the bottom of the initial trench and react with the substrate during the thermal oxidation treatment to obtain a bottom sacrificial layer. Moreover, during the ion implantation, ions implanted at both ends will sputter at the bottom corner, causing some ions to sputter to the sidewall. Therefore, the ion implantation depth of the ion implantation region in the middle region is greater than that of the ion implantation region in the two end regions. Under the action of subsequent thermal oxidation, the bottom sacrificial layer formed will be further rounded along the morphology of the ion implantation region. Therefore, the bottom sacrificial layer with an arc-shaped bottom can be formed at the bottom of the initial trench. After the bottom sacrificial layer is removed, a trench with an arc-shaped bottom can be obtained, which avoids the problem of sharp end discharge caused by the existence of sharp corners at the bottom. When the trench is used as a gate trench, the gate can be better protected. Moreover, compared with the conventional scheme of directly etching the bottom of the trench to round the bottom of the trench by using an isotropic etching method, the preparation method of the semiconductor structure can reduce the side push of the trench, and thus can ensure that the critical dimension of the structure obtained based on the trench during subsequent process technology meets the requirements.

[0068] In some examples, the bottom sacrificial layer can include, but is not limited to, at least one of a silicon layer and a silicon oxide layer.

[0069] In step S11, please refer to the S11 step in Figure 1 , and Figure 2 , a substrate 1 is provided.

[0070] Specifically, the substrate 1 can include, but is not limited to, at least one of a single crystal silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate. Specifically, the substrate 1 can be any one of a single crystal silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate, and a silicon carbide substrate, or a composite substrate composed of two or more of them.

[0071] In step S12, please refer to the S12 step in Figure 1 , and Figures 3-4 , an initial trench 3 is formed in the substrate 1.

[0072] In one embodiment, the initial trench 3 is formed in the substrate 1, including:

[0073] S121: a mask layer 2 is formed on the surface of the substrate 1, and the mask layer 2 has an opening 21 therein, which defines the shape and position of the initial trench 3, as shown in Figure 3 ;

[0074] S122: etching the base 1 based on the mask layer 2 to form an initial groove 3 in the base 1, as shown in Figure 4 .

[0075] The method for etching the base 1 based on the mask layer 2 can adopt, but is not limited to, a dry etching process. The etching gas used in the dry etching process can include at least one of sulfur hexafluoride, chlorine, methane, silicon chloride, and argon. The mask layer 2 is formed on the surface of the base 1, and can isolate and protect the surface of the base 1 during the subsequent etching process to form the initial groove 3.

[0076] In some embodiments, the mask layer 2 can include at least one of a silicon nitride layer, a silicon carbide layer, and a silicon oxynitride layer.

[0077] In step S121, forming the mask layer 2 on the surface of the base 1 can include: forming an initial mask layer on the surface of the base 1, the initial mask layer can include at least one of a silicon nitride layer, a silicon carbide layer, and a silicon oxynitride layer; forming a photoresist layer away from the surface of the base 1 on the initial mask layer, exposing the photoresist layer based on a patterned photomask; developing the exposed photoresist layer to obtain a patterned photoresist layer; and etching the initial mask layer based on the patterned photoresist layer to obtain the mask layer 2.

[0078] In some examples, the photoresist layer can include a positive photoresist layer, or a negative photoresist layer.

[0079] In one embodiment, after forming the initial groove 3 in the base 1, before ion implantation is performed on the base 1 at the bottom of the initial groove 3, the method can further include: forming a covering sacrificial layer 4, the covering sacrificial layer 4 covering at least the sidewall and the bottom of the initial groove 3, as shown in Figure 5 .

[0080] The covering sacrificial layer 4 can include, but is not limited to, at least one of a silicon layer and a silicon oxide layer. The thickness of the covering sacrificial layer 4 is greater than or equal to 5 nanometers. Specifically, the thickness of the covering sacrificial layer 4 can be 5 nanometers, 10 nanometers, or any thickness greater than 5 nanometers, which is not limited by the examples.

[0081] In one embodiment, the covering sacrificial layer 4 can be formed by, but is not limited to, a chemical vapor deposition process. Further, the covering sacrificial layer 4 can be formed by a sub-atmospheric chemical vapor deposition method.

[0082] In one embodiment, refer to Figure 5The covering sacrificial layer 4 also covers the surface of the mask layer 2 away from the substrate 1. Specifically, the substrate 1 is etched based on the mask layer 2 to form the initial trench 3 in the substrate 1, and the covering sacrificial layer 4 is formed on the sidewall and bottom of the initial trench 3 and the surface of the mask layer 2 away from the substrate 1. After the initial trench 3 is formed in the substrate 1, before the ion implantation is performed on the substrate 1 at the bottom of the initial trench 3, the step of forming the covering sacrificial layer 4 on the sidewall of the initial trench 3, the bottom of the initial trench 3, and the surface of the mask layer 2 away from the substrate 1 is further included.

[0083] Specifically, because the surface of the substrate 1 will be damaged if the ions are directly implanted into the substrate 1 during the ion implantation process, the covering sacrificial layer 4 is formed on the sidewall of the initial trench 3, the bottom of the initial trench 3, and the surface of the mask layer 2 away from the substrate 1 to protect the surface of the substrate 1 in the initial trench 3, especially the surface of the substrate 1 at the bottom of the initial trench 3.

[0084] In step S13, please refer to the step S13 in Figure 1 and Figure 6 , and the ion implantation is performed on the substrate 1 at the bottom of the initial trench 3 to form the ion implantation region 5.

[0085] Specifically, please refer to Figure 6 . Because the sidewall of the initial trench 3 does not need to be implanted with ions, the vertical ion implantation can be performed on the substrate 1 at the bottom of the initial trench 3 with an implantation angle of 0° to reduce the influence of the ion implantation on the sidewall of the initial trench 3. However, because particle collisions will occur between the implanted ions and the material of the substrate 1 when the ion implantation is performed on the substrate 1 at the bottom of the initial trench 3, a small part of the particles near the sidewall close to the bottom of the initial trench 3 will also be reflected into the sidewall, so the ion implantation region will also be formed on the sidewall close to the bottom of the initial trench 3.

[0086] The implantation angle of 0° refers to the angle between the ion implantation direction and the substrate 1 at the bottom of the initial trench 3.

[0087] In one embodiment, after the ion implantation is performed on the substrate 1 at the bottom of the initial trench 3, before the thermal oxidation treatment is performed on the substrate 1, the step of removing the covering sacrificial layer 4 at the bottom of the initial trench 3 is further included, and the obtained structure is as shown in Figure 7 .

[0088] Specifically, removing the cover sacrificial layer 4 at the bottom of the initial trench 3 while retaining the cover sacrificial layer 4 on the sidewall of the initial trench 3 before thermal oxidation of the ion implantation region 5 is to make it easier for oxygen to enter the ion implantation region 5 in the substrate 1 at the bottom of the initial trench 3 during the oxidation process, thereby accelerating the reaction rate between oxygen and the substrate 1 in the ion implantation region 5. As a result, the oxidation rate of the substrate 1 at the bottom of the initial trench 3 is much higher than the oxidation rate of the substrate 1 on the sidewall of the initial trench 3.

[0089] Specifically, a dry etching process can be used to remove the cover sacrificial layer 4 located at the bottom of the initial trench 3; more specifically, an anisotropic dry etching process can be used to remove the cover sacrificial layer 4 located at the bottom of the initial trench 3.

[0090] In one embodiment, see Figures 6-7 While removing the cover sacrificial layer 4 located at the bottom of the initial trench 3, the cover sacrificial layer 4 located on the surface of the mask layer 2 away from the substrate 1 is also removed.

[0091] Specifically, a dry etching process can be used to remove the cover sacrificial layer 4 located on the surface of the mask layer 2 away from the substrate 1; more specifically, an anisotropic dry etching process can be used to remove the cover sacrificial layer 4 located on the surface of the mask layer 2 away from the substrate 1.

[0092] In step S14, please refer to Figure 1 Step S14 in the middle and Figure 8 The substrate 1 is subjected to thermal oxidation treatment to form a bottom sacrificial layer 6 with an arc-shaped bottom at the bottom of the initial trench 3.

[0093] In this embodiment, a furnace tube oxidation process can be used for thermal oxidation. Specifically, a lower temperature can be used to thermally oxidize the ion implantation region 5. The lower temperature can be understood as the minimum temperature at which thermal oxidation can be achieved, approximately 800°C. This lower temperature allows for better control of the rate at which the amorphous region of the ion implantation region 5 reacts with oxygen to form an oxide layer, thereby controlling the oxidation depth. Furthermore, because ion implantation easily damages the lattice of the ion implantation region 5 at the bottom of the initial trench 3, oxygen can more easily reach the bottom of the initial trench 3 along the damaged lattice during thermal oxidation and react with the substrate to obtain the bottom sacrificial layer 6. Also, because ions implanted at both ends will sputter at the bottom corners during ion implantation, causing some ions to sputter to the sidewalls, the ion implantation depth in the middle region of the ion implantation region 5 is greater than that in the regions at both ends. Under the action of thermal oxidation, the formed bottom sacrificial layer 6 will further round out along the morphology of the ion implantation region, thus forming a bottom sacrificial layer 6 with an arc-shaped bottom at the bottom of the initial trench 3. The bottom sacrificial layer 6 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon oxycarbide layer.

[0094] It should be noted that, as mentioned above, when the ion implantation is performed on the substrate 1 at the bottom of the initial trench 3, the ion implantation region 5 is also formed on the part of the sidewall near the bottom of the initial trench 3. Therefore, when the thermal oxidation process is performed on the substrate 1 to form the bottom sacrificial layer 6 at the bottom of the initial trench 3, the sidewall oxide layer is also formed on the part of the sidewall near the bottom of the initial trench 3, and the sidewall oxide layer is formed between the sacrificial layer 4 and the substrate 1; further, when the bottom sacrificial layer 6 is removed, the sidewall oxide layer formed there is also removed, so that the width between the sidewalls near the bottom of the initial trench 3 is greater than the width between the sidewalls near the upper part of the initial trench 3.

[0095] In some embodiments, the thermal oxidation process on the ion implantation region 5 can be performed by using an in-situ steam generation (ISSG) process. The in-situ steam generation technology is a new type of low-pressure rapid thermal oxidation annealing technology (RTP, Rapid Thermal Process), which is currently mainly used for the growth of ultra-thin oxide films, the preparation of the bottom sacrificial layer 6 and the nitrogen-oxygen film.

[0096] In step S15, please refer to the S15 step in Figure 1 and Figure 9 , the bottom sacrificial layer 6 is removed to obtain the trench 7 with an arc-shaped bottom.

[0097] Specifically, the trench 7 with an arc-shaped bottom can avoid the problem of tip discharge caused by the existence of sharp corners at the bottom of the trench 7, and can better protect the gate when the trench 7 is used as a gate trench. Compared with the method of obtaining a trench by isotropic etching, the method for preparing the semiconductor structure of the present application can reduce the side push of the trench 7, and thus can ensure that the critical dimension of the structure obtained based on the subsequent process on the trench meets the requirements.

[0098] Further, the wet process can be used to remove the bottom sacrificial layer 6.

[0099] In one embodiment, the removal of the bottom sacrificial layer 6 also includes removing the covering sacrificial layer 4 located on the sidewall of the initial trench 3.

[0100] Specifically, the wet process can be used to remove the bottom sacrificial layer 6 and the covering sacrificial layer 4 located on the sidewall of the initial trench 3 at the same time. The removal of the bottom sacrificial layer 6 and the covering sacrificial layer 4 located on the sidewall of the initial trench 3 can empty the trench 7, which is convenient for forming the gate in the trench 7 subsequently.

[0101] In one embodiment, after the bottom sacrificial layer 6 and the covering sacrificial layer 4 are removed, the step of removing the mask layer 2 is further included, and the obtained structure is as shown inFigure 10 As shown.

[0102] Specifically, the mask layer 2 can be removed by a wet process. The mask layer 2 is reserved before the bottom sacrificial layer 6 and the covering sacrificial layer 4 are removed, so that the mask layer 2 can serve as a protective layer to protect the substrate 1 from being etched away when the bottom sacrificial layer 6 and the covering sacrificial layer 4 are removed.

[0103] In one embodiment, referring to Figure 9 or Figure 10 , after the bottom sacrificial layer 6 is removed to obtain the arc-shaped trench 7, a part of the ion implantation region 5 in the substrate 1 at the bottom of the trench 7 is reserved.

[0104] In one embodiment, after the bottom sacrificial layer 6 is removed to obtain the arc-shaped trench 7, the method can further include: forming a gate oxide layer 8 on the sidewall and the bottom of the trench 7, the thickness of the gate oxide layer 8 at the bottom of the trench 7 being greater than the thickness of the gate oxide layer 8 at the sidewall of the trench 7.

[0105] In other embodiments, after the bottom sacrificial layer 6 is removed to obtain the arc-shaped trench 7, the method can further include: S16: forming a gate oxide layer 8 on the sidewall and the bottom of the trench 7, and forming a gate conductive layer 9 in the trench 7; the thickness of the gate oxide layer 8 at the bottom of the trench 7 being greater than the thickness of the gate oxide layer 8 at the sidewall of the trench 7.

[0106] Specifically, the gate oxide layer 8 formed on the sidewall and the bottom of the trench 7 serves as a protective layer of the gate to reduce the risk of gate leakage.

[0107] In one embodiment, forming the gate oxide layer 8 on the sidewall and the bottom of the trench 7, and forming the gate conductive layer 9 in the trench 7 can include:

[0108] S161: forming a gate oxide material layer 81 on the sidewall of the trench 7, the bottom of the trench 7, and the substrate 1, as shown in Figure 11 ;

[0109] S162: forming a gate conductive material layer 91 in the trench 7 and on the substrate 1, as shown in Figure 12 ;

[0110] S163: removing the gate conductive material layer 91 on the substrate 1 and the gate oxide material layer 81 on the substrate 1 to obtain the gate conductive layer 9 and the gate oxide layer 8, as shown in Figure 13 .

[0111] In-situ oxidation can be used to oxidize the sidewalls, bottom, and substrate 1 of trench 7 to obtain gate oxide layer 81. The oxidation process can be carried out at high temperature. The thickness of the gate oxide layer 81 at the bottom of trench 7 is greater than the thickness of the gate oxide layer 81 at the sidewall of trench 7 to improve the withstand voltage of the device. The gate oxide layer 8 is used to isolate the gate conductive layer 9 from the substrate to isolate and protect the gate conductive layer 9 and reduce the risk of gate leakage.

[0112] It should be noted that, as mentioned above, after removing the bottom sacrificial layer 6 to obtain a trench 7 with an arc-shaped bottom, a portion of the ion implantation region 5 is retained in the substrate 1 at the bottom of the trench 7. Therefore, the process of oxidizing the sidewalls of the trench 7, the bottom of the trench 7, and the substrate 1 to obtain the gate oxide material layer 81 includes the oxidation of the ion implantation region 5 retained in the substrate 1, so that the thickness of the gate oxide material layer 81 at the bottom of the trench 7 is greater than the thickness of the gate oxide material layer 81 at the sidewalls of the trench 7. Consequently, the obtained gate oxide layer 8 also satisfies the condition that the thickness of the gate oxide layer 8 at the bottom of the trench 7 is greater than the thickness of the gate oxide layer 8 at the sidewalls of the trench 7.

[0113] In some examples, a low-step overlay process can be used to form the gate conductive material layer 91. Further, an N-type doped polysilicon material layer can be formed as the gate conductive material layer 91 using a low-step overlay process; that is, the gate conductive layer 91 can be an N-type doped polysilicon material, and the dopant ions can include, but are not limited to, at least one of phosphorus ions, arsenic ions, or antimony ions. The doping concentration of the dopant ions in the doped polysilicon material can be 10E20cm⁻¹. -3 ~20E20cm -3 Specifically, the doping concentration can be 10E20cm. -3 12E20cm -3 15E20cm -3 18E20cm -3 Or 20E20cm -3 It could also be another location located at 10E20cm -3 ~20E20cm -3 The concentration of dopant ions is not limited to the illustrated embodiments. By changing the concentration of dopant ions, the work function of the gate conductive layer 9 can be altered. Therefore, the work function can be reduced by controlling the concentration of dopant ions, thereby reducing the risk of gate leakage.

[0114] Specifically, the low-step coverage process can improve the film uniformity of the gate conductive layer 9, has the characteristics of extremely low spatter amount and high deposition rate in the process, can reduce material spatter in the process and increase the stability of the arc, and thus obtain a high-quality gate conductive layer 9. The N-type doped polysilicon material layer is deposited by the low-step coverage process, and the process is simple. Compared with the ions doped in the traditional process of forming the N-type doping, the doped ions can be supplemented in the scheme of the low-step coverage process for depositing the N-type doped polysilicon material, the doped N-type ions can play a good role in preventing leakage and improving the leakage current, improve the device performance, and the process is simple and can save costs.

[0115] In one embodiment, referring to Figure 13 , the upper surface of the gate conductive layer 9 can be lower than the top of the trench 7; after the gate conductive layer 9 is formed in the initial trench 3, the process further includes: forming an insulating isolation layer on the upper surface of the gate conductive layer 9, and the insulating isolation layer fills the gate trench 7. Specifically, the insulating isolation layer can include but is not limited to a silicon nitride layer or a silicon carbide layer, and the insulating isolation layer is used to insulate and protect the gate conductive layer 9, so as to reduce the risk of gate leakage.

[0116] In one embodiment, the method for manufacturing a semiconductor structure includes:

[0117] providing a substrate 1;

[0118] forming a mask layer 2 on the surface of the substrate 1, the mask layer 2 has an opening 21, and the opening 21 defines the shape and position of the initial trench 3;

[0119] etching the substrate 1 based on the mask layer 2 to form the initial trench 3 in the substrate 1;

[0120] forming a cover sacrifice layer 4 on the sidewall of the initial trench 3, the bottom of the initial trench 3, and the surface of the mask layer 2 away from the substrate 1;

[0121] performing ion implantation on the substrate 1 at the bottom of the initial trench 3 to form an ion implantation region 5;

[0122] removing the cover sacrifice layer 4 at the bottom of the initial trench 3 and the cover sacrifice layer 4 on the surface of the mask layer 2 away from the substrate 1;

[0123] performing thermal oxidation treatment on the substrate 1 to form a bottom sacrifice layer 6 with an arc-shaped bottom at the bottom of the initial trench 3;

[0124] removing the bottom sacrifice layer 6 and the cover sacrifice layer 4 on the sidewall of the initial trench 3 to obtain a trench 7 with an arc-shaped bottom, and part of the ion implantation region is reserved in the substrate 1 at the bottom of the trench 7;

[0125] Forming a gate oxide material layer 81 on the sidewall of the trench 7, the bottom of the trench 7 and the substrate 1;

[0126] Forming a gate conductive material layer 91 in the trench 7;

[0127] Removing the gate conductive material layer 91 on the substrate 1 and the gate oxide material layer 81 on the substrate 1 to obtain a gate conductive layer 9 and a gate oxide layer 8;

[0128] Forming an insulating isolation layer on the upper surface of the gate conductive layer 9, the insulating isolation layer filling the gate trench 7.

[0129] It should be understood that, although each step in the flowchart of each embodiment is shown in sequence according to the arrow, these steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, at least part of the steps in the flowchart of each embodiment can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0130] The present application also provides a semiconductor structure, which is prepared by the preparation method of the semiconductor structure of any one of the above-mentioned embodiments. As shown in Figure 10 The semiconductor structure includes a substrate 1 and a trench 7 in the substrate 1, and the bottom of the trench 7 is arc-shaped.

[0131] The semiconductor structure in the above-mentioned embodiments includes a trench 7 with an arc-shaped bottom, which can reduce the occurrence of device leakage and better protect the gate; and the size of the trench 7 is not affected by the preparation process, so as to ensure that the critical dimension of the structure obtained based on the trench 7 in the subsequent process meets the requirements.

[0132] Specifically, the substrate 1 can include but is not limited to at least one of a single crystal silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate; specifically, the substrate 1 can be any one of a single crystal silicon substrate, a germanium substrate, a silicon germanium substrate, a gallium arsenide substrate, a gallium nitride substrate and a silicon carbide substrate, or a composite substrate composed of two or more of them.

[0133] In other embodiments, the semiconductor structure can refer to the embodiments of Figures 1-13 and the corresponding text description, which will not be repeated here.

[0134] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as there is no conflict, any combination of the technical features should be considered within the scope of the present disclosure.

[0135] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; forming an initial trench in the substrate; performing ion implantation on the substrate at the bottom of the initial trench to form an ion implantation region; the ion implantation includes at least one of phosphorus ions, arsenic ions and antimony ions; performing thermal oxidation treatment on the substrate to form a bottom arc-shaped bottom sacrificial layer at the bottom of the initial trench; wherein the ion implantation damages the lattice of the ion implantation region at the bottom of the initial trench, and oxygen reaches the bottom of the initial trench and reacts with the substrate during the thermal oxidation treatment to obtain the bottom sacrificial layer; during the ion implantation, ions implanted at both ends are sputtered at the bottom corner, causing part of the ions to be sputtered to the sidewall, and the depth of ion implantation in the ion implantation region near the middle region is greater than that near the two end regions, and the bottom sacrificial layer formed during the thermal oxidation treatment is further rounded along the topography of the ion implantation region; removing the bottom sacrificial layer to obtain a bottom arc-shaped trench.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: After the initial trench is formed in the substrate, before the ion implantation is performed on the substrate at the bottom of the initial trench, the method further comprises the following steps: forming a cover sacrificial layer, the cover sacrificial layer covering at least the sidewall and the bottom of the initial trench; after the ion implantation is performed on the substrate at the bottom of the initial trench, before the thermal oxidation treatment is performed on the substrate, the method further comprises the following step: removing the cover sacrificial layer at the bottom of the initial trench.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: When the bottom sacrificial layer is removed, the method further comprises the following step: removing the cover sacrificial layer at the sidewall of the initial trench.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The method of forming the initial trench in the substrate comprises the following steps: forming a mask layer on the surface of the substrate, the mask layer having an opening, the opening defining the shape and position of the initial trench; etching the substrate based on the mask layer to form the initial trench in the substrate; wherein the cover sacrificial layer also covers the surface of the mask layer away from the substrate; When the cover sacrificial layer at the bottom of the initial trench is removed, the method further comprises the following step: removing the cover sacrificial layer on the surface of the mask layer away from the substrate; after the bottom sacrificial layer and the cover sacrificial layer are removed, the method further comprises the following step: removing the mask layer.

5. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The cover sacrificial layer is formed by a chemical vapor deposition process.

6. The method of producing a semiconductor structure according to any one of claims 1 to 5, wherein After the bottom sacrificial layer is removed to obtain a bottom arc-shaped trench, part of the ion implantation region remains in the substrate at the bottom of the trench.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: After the bottom sacrificial layer is removed to obtain a bottom arc-shaped trench, the method further comprises the following step: forming a gate oxide layer on the sidewall and the bottom of the trench, the thickness of the gate oxide layer at the bottom of the trench being greater than the thickness of the gate oxide layer at the sidewall of the trench.

8. The method of claim 6, wherein the step of forming the semiconductor structure is performed by a method comprising: After the bottom sacrificial layer is removed to obtain a bottom arc-shaped trench, the method further comprises the following step: forming a gate oxide layer on the sidewall and the bottom of the trench, and forming a gate conductive layer in the trench; the thickness of the gate oxide layer at the bottom of the trench being greater than the thickness of the gate oxide layer at the sidewall of the trench.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The method of forming a gate oxide layer on the sidewall and the bottom of the trench, and forming a gate conductive layer in the trench comprises the following steps: forming a gate oxide material layer on sidewalls of the trench, a bottom of the trench and the substrate; forming a gate conductive material layer in the trench and on a surface of the gate oxide material layer; removing the gate conductive material layer on the substrate and the gate oxide material layer on the substrate to obtain the gate conductive layer and the gate oxide layer.

10. A semiconductor structure, characterized by The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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