Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises the following steps: providing a substrate, and forming an initial groove on the substrate; depositing a first material, the first material filling the initial groove to form an initial filling layer, and an initial gap is formed in the initial filling layer; processing the first material by using a first process; and forming a first filling part, the first filling part comprising a second material, the first filling part covering part of the initial groove, and a top surface of the first filling part being provided with a gently U-shaped groove. In the present disclosure, the internal structure of the first material is destroyed, and then the internal structure of the first material is rearranged to form the second material. In the process of rearranging the internal structure of the first material, the structure of the initial gap is changed, so that the initial gap forms a gap with a gentler structure and a smaller volume, thereby reducing the influence of filling the vacancy on the conductive performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the improvement of semiconductor integration, the process line width of semiconductor manufacturing technology is continuously reduced. In order to ensure the capacitance requirement of semiconductor devices, semiconductor devices develop towards high aspect ratio, and more and more semiconductor devices have high aspect ratio trenches. However, in the process of filling the high aspect ratio trench, the filling material is prone to form voids in the trench due to the influence of edge effect caused by high aspect ratio structure, which affects the yield and conductivity of semiconductor devices. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure.

[0005] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] providing a substrate, and forming an initial trench on the substrate;

[0007] depositing a first material, the first material filling the initial trench to form an initial filling layer, and an initial gap being formed in the initial filling layer;

[0008] processing the first material by using a first process;

[0009] forming a first filling part, the first filling part comprising a second material, the first filling part covering part of the initial trench, and a top surface of the first filling part being provided with a gentle U-shaped groove.

[0010] According to some embodiments of the present disclosure, the first material comprises a first doping element; and the second material comprises the first doping element and a second doping element.

[0011] According to some embodiments of the present disclosure, the processing the first material by using a first process comprises:

[0012] injecting the second doping element into the initial filling layer, the second doping element diffusing in the initial filling layer, and the initial filling layer forming a crystalline defect layer;

[0013] The annealing process is performed on the crystalline defect layer, the first material and the second doping element are recrystallized to form the second material, the crystalline defect layer forms the second material layer, the initial gap forms a first gap, and a longitudinal section plane is perpendicular to the substrate and perpendicular to the extension direction of the second material layer, and a projection of the first gap on the longitudinal section plane is a circular or quasi-circular structure.

[0014] According to some embodiments of the present disclosure, the first filling part includes the second material, and the first filling part covers part of the initial groove. The method further comprises:

[0015] Part of the second material layer is removed to expose part of the sidewall of the initial groove, and the remaining second material layer forms the first filling part, and a top surface of the first filling part includes a gentle U-shaped groove.

[0016] According to some embodiments of the present disclosure, a projection of the U-shaped groove on the longitudinal section plane is an arc-shaped structure that is recessed from the top surface of the first filling part to the substrate direction.

[0017] A lowest point of the arc-shaped structure of the U-shaped groove is higher than a top surface of the first gap, and the first gap is enclosed in the first filling part.

[0018] According to some embodiments of the present disclosure, the manufacturing method further comprises:

[0019] Part of the initial filling layer is removed to expose part of the sidewall of the initial groove, and the first material around the initial gap is removed, and a first groove is formed in the remaining initial filling layer.

[0020] According to some embodiments of the present disclosure, a longitudinal section plane is perpendicular to the substrate and perpendicular to the extension direction of the initial groove, and a projection size of a top opening of the first groove on the longitudinal section plane is greater than a projection size of a bottom wall of the first groove on the longitudinal section plane.

[0021] According to some embodiments of the present disclosure, the first material is processed by using a first process, which comprises:

[0022] The second doping element is implanted into the first material, and the second doping element diffuses in the first material, and the remaining initial filling layer forms a crystalline defect layer.

[0023] The crystalline defect layer is subjected to an annealing process, the first material and the second doping element are recrystallized to form the second material, and the crystalline defect layer after the annealing process forms the first filling part.

[0024] The first groove forms the U-shaped groove, and a projection of the U-shaped groove on a longitudinal section plane perpendicular to the substrate and perpendicular to an extension direction of the first filling portion is an arc-shaped structure recessed from a top surface of the first filling portion toward the substrate.

[0025] According to some embodiments of the present disclosure, the method for manufacturing the semiconductor structure further includes:

[0026] forming a second filling portion covering a top surface of the first filling portion and filling a region in the initial groove not covered by the first filling portion.

[0027] According to some embodiments of the present disclosure, the method for manufacturing the semiconductor structure further includes:

[0028] forming a spacer structure disposed on the substrate, the initial groove being formed between adjacent spacer structures;

[0029] forming a barrier layer covering a sidewall and a top surface of the spacer structure.

[0030] A second aspect of the present disclosure provides a semiconductor structure, which includes:

[0031] a substrate;

[0032] an initial groove disposed on the substrate;

[0033] a first filling portion covering part of the initial groove, a top surface of the first filling portion being provided with a gently U-shaped groove;

[0034] the first filling portion includes a second material including a first doped element and a second doped element.

[0035] According to some embodiments of the present disclosure, a projection of the U-shaped groove on a longitudinal section plane perpendicular to the substrate and perpendicular to an extension direction of the first filling portion is an arc-shaped structure recessed from a top surface of the first filling portion toward the substrate.

[0036] According to some embodiments of the present disclosure, the first filling portion further includes a first gap, and a projection of the first gap on a longitudinal section plane perpendicular to the substrate and perpendicular to an extension direction of the first filling portion is a circular or quasi-circular structure.

[0037] a bottom surface of the U-shaped groove is higher than a top surface of the first gap, and the first gap is enclosed in the first filling portion.

[0038] According to some embodiments of the present disclosure, the semiconductor structure further includes:

[0039] a second filling part covering a top surface of the first filling part and filling a region in the initial trench not covered by the first filling part.

[0040] According to some embodiments of the present disclosure, the semiconductor structure further comprises:

[0041] a spacer structure disposed on the substrate, the initial trench being disposed between adjacent spacer structures;

[0042] a barrier structure covering a sidewall and a top surface of the spacer structure.

[0043] In the semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure, the internal structure of the first material is destroyed, and the internal structure of the first material is rearranged to form the second material. In the process of rearranging the internal structure of the first material, the structure of the initial gap is changed, so that the initial gap forms a gap with a more gentle structure and a smaller volume, thereby reducing the influence of filling the vacancy on the conductive performance of the semiconductor structure.

[0044] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings incorporated in and forming a part of the specification illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. Similar reference numerals in the drawings represent similar elements. The drawings in the following description are of some embodiments of the present disclosure, and not all embodiments. Other drawings can be derived from these drawings by a person of ordinary skill in the art without paying creative labor.

[0046] Figure 1 is a flowchart of a manufacturing method of a semiconductor structure according to an exemplary embodiment.

[0047] Figure 2 is a flowchart of a manufacturing method of a semiconductor structure according to an exemplary embodiment.

[0048] Figure 3 is a flowchart of a manufacturing method of a semiconductor structure according to an exemplary embodiment.

[0049] Figure 4 is a flowchart of a manufacturing method of a semiconductor structure according to an exemplary embodiment.

[0050] Figure 5 is a schematic diagram of filling a trench with a first filling material in a manufacturing method of a semiconductor structure according to an exemplary comparative example.

[0051] Figure 6 is a schematic view of etching back the first fill material in a method of fabricating a semiconductor structure according to an example comparative example.

[0052] Figure 7 is a schematic view of the first fill material and the second fill material co-filling the trench in a method of fabricating a semiconductor structure according to an example comparative example.

[0053] Figure 8 is a schematic view of an initial trench provided in a method of fabricating a semiconductor structure according to an example embodiment.

[0054] Figure 9 is a schematic view of an initial trench provided in a method of fabricating a semiconductor structure according to an example embodiment.

[0055] Figure 10 is a schematic view of an initial trench provided in a method of fabricating a semiconductor structure according to an example embodiment.

[0056] Figure 11 is a schematic view of forming a barrier layer in a method of fabricating a semiconductor structure according to an example embodiment.

[0057] Figure 12 is a schematic view of forming an initial fill layer in a method of fabricating a semiconductor structure according to an example embodiment.

[0058] Figure 13 is a schematic view of the initial fill layer forming a crystalline defect layer in a method of fabricating a semiconductor structure according to an example embodiment.

[0059] Figure 14 is a schematic view of the crystalline defect layer forming a second material layer in a method of fabricating a semiconductor structure according to an example embodiment.

[0060] Figure 15 is a schematic view of forming a first fill portion in a method of fabricating a semiconductor structure according to an example embodiment.

[0061] Figure 16 is a schematic view of forming a second fill portion in a method of fabricating a semiconductor structure according to an example embodiment.

[0062] Figure 17 is a schematic view of removing a portion of the first fill layer to expose the barrier layer at a top surface of the spacer structure in a method of fabricating a semiconductor structure according to an example embodiment.

[0063] Figure 18Fig. 6 is a schematic view showing a method for manufacturing a semiconductor structure according to an example embodiment, in which a first recess is formed by removing part of the first filling layer.

[0064] Figure 19 Fig. 7 is a schematic view showing a method for manufacturing a semiconductor structure according to an example embodiment, in which a crystalline defect layer is formed by the remaining initial filling layer.

[0065] Figure 20 Fig. 8 is a schematic view showing a method for manufacturing a semiconductor structure according to an example embodiment, in which a first filling part is formed by the crystalline defect layer.

[0066] Figure 21 Fig. 9 is a schematic view showing a method for manufacturing a semiconductor structure according to an example embodiment, in which a second filling part is formed.

[0067] Reference signs:

[0068] 110, substrate; 120, initial trench; 130, spacer structure; 140, barrier layer;

[0069] 200, first filling part; 201, U-shaped recess; 210, initial filling layer; 210a, remaining initial filling layer; 211, initial gap; 220, second material layer; 221, first gap; 230, crystalline defect layer; 240, first recess;

[0070] 101', trench; 102', void; 103', V-shaped groove; 104', natural oxide layer. DETAILED DESCRIPTION

[0071] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other at will.

[0072] With the development of integrated circuits in the direction of miniaturization, in order to ensure the capacitance requirement of semiconductor devices, the scheme commonly used in the related art is to increase the height of the semiconductor device, so that the trench of the semiconductor device gradually evolves in the direction of high aspect ratio.

[0073] In the process of the semiconductor structure, the filling of the trench is usually filled by a chemical vapor deposition (CVD) process or a low-pressure chemical vapor deposition (LPCVD) process. The filling process is affected by the trench edge effect caused by a high aspect ratio, and the filling material may not fill the trench, resulting in a gap in the formed semiconductor structure.

[0074] As shown in Figure 5 , Figure 6 , Figure 7 In the related art, multiple filling is usually used, that is, a first filling material is deposited to fill the trench 101', a gap 102' is formed in the first filling material, part of the first filling material is etched back to expose the gap 102' formed by filling, and the first filling material around the gap 102' is etched. The first filling material retained in the trench 101' forms a V-shaped groove 103', and a second filling material is filled in the formed V-shaped groove 103'. However, the first filling material on the top surface of the V-shaped groove 103' is easily oxidized to form a natural oxide layer 104', which is arranged between the first filling material and the second filling material, affecting the conductivity of the semiconductor structure.

[0075] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, as shown in Figure 1 , Figure 1 A flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown, Figures 7-21 is a schematic diagram of each stage of the method for manufacturing a semiconductor structure, and the method for manufacturing a semiconductor structure will be described below in conjunction with Figures 7-21 .

[0076] The semiconductor structure is not limited in the present embodiment, and a dynamic random access memory (DRAM) will be taken as an example for description below, but the present embodiment is not limited thereto. The semiconductor structure in the present embodiment can also be other structures.

[0077] As shown in Figure 1 , the method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure comprises the following steps:

[0078] Step S110: providing a substrate and forming an initial trench on the substrate.

[0079] As shown in Figure 11 , the substrate 110 can comprise a semiconductor material. The semiconductor material can be one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.

[0080] The initial trench 120 is a hole formed on the substrate 110 or a trench extending on the substrate 110. In this embodiment, the initial trench 120 can be a TSV hole, a bit line contact hole, a capacitor contact hole, a wiring hole, or other through-hole.

[0081] Step S120: Deposit a first material, the first material fills the initial trench to form an initial filling layer, and an initial gap is formed in the initial filling layer.

[0082] like Figure 12 As shown, refer to Figure 11 The first material can be deposited using a low-pressure chemical vapor deposition (LPCVD) process, and the first material fills the initial trench 120 to form an initial filling layer 210. During the deposition process, the first material is affected by the high aspect ratio structure of the initial trench 120, forming filling gaps and initial gaps 211 in the initial filling layer 210. The initial gaps 211 are irregular band-shaped structures extending along the height direction of the initial trench 120.

[0083] The first material is set according to the type of the initial trench 120 to be filled. The first material can be a semiconductor material, an insulating material, or a conductor material.

[0084] In this embodiment, the first material is doped with a first doping element. The first doping element can be added to the first material during the deposition process, or the first doping element can be added to the undoped material after the initial trench 120 has been filled with undoped material to form the first material.

[0085] Step S130: Process the first material using the first process.

[0086] In this embodiment, the first process is ion implantation technology (IMP), which implants dopant elements into a first material to change the properties of the first material, and implants a second dopant element to change the internal atomic arrangement or the internal lattice structure of the first material. For example... Figure 14 As shown, refer to Figure 12 This is done so that the first material forms the second material. The second material includes a first dopant element and a second dopant element, which may be the same or different.

[0087] In this embodiment, an ion implantation process can be used to implant a second dopant element into the first material once or multiple times, and the second dopant element implanted each time can be the same or different.

[0088] Step S140: forming a first filling part, the first filling part comprising the second material, the first filling part covering part of the initial trench, and a top surface of the first filling part being configured as a gentle U-shaped groove.

[0089] As shown in Figure 15 , referring to Figure 14 , part of the initial filling layer 210 can be removed by a dry etching process or a wet etching process to expose part of the sidewall of the initial trench 120, and a first filling part 200 is formed, and a top surface of the first filling part 200 is configured as a gentle U-shaped groove 201.

[0090] In this embodiment, during the process of forming the first material into the second material, the internal atoms of the first material are rearranged or the internal lattice structure of the first material is changed and rearranged, and part of the atoms or part of the lattice in the first material are arranged into the initial gap, changing the structure and position of the initial gap into a smaller gap structure with a gentler structure compared with the initial gap, so as to reduce the influence of the filling vacancy on the first filling part.

[0091] The semiconductor manufacturing method of this embodiment reduces the influence of the initial gap generated in the deposition process of the first material on the first filling part by changing the internal structure of the first material through an ion implantation process. At the same time, the first filling part fills part of the initial trench, reduces the aspect ratio of the part of the initial trench that is not filled, and the top surface of the first filling part is configured as a gentle U-shaped groove, reducing the difficulty of subsequent filling of the initial trench.

[0092] According to one exemplary embodiment, the semiconductor structure manufacturing method provided by this embodiment comprises the following steps, as shown in Figure 2 :

[0093] Step S210: providing a substrate and forming an initial trench on the substrate.

[0094] As shown in Figure 11 , the substrate 110 can comprise a semiconductor material. The semiconductor material can be one or more of silicon, germanium, silicon-germanium compound, and silicon-carbon compound.

[0095] In this embodiment, the initial trench 120 is formed on the substrate 110, comprising:

[0096] Step S211: forming a spacing structure, the spacing structure being arranged on the substrate, and the initial trench being formed between adjacent spacing structures.

[0097] As shown in Figure 8 , or Figure 9 , or Figure 10As shown, spacer structures 130 are formed on substrate 110. Two adjacent spacer structures 130 and the exposed substrate 110 between two adjacent spacer structures 130 together form an initial trench 120. The initial trench 120 can be a hole-type structure embedded between the spacer structures 130, or the adjacent spacer structures 130 can extend parallel to each other on the substrate 110, and the initial trench 120 is a trench extending between adjacent spacer structures 130.

[0098] For example, such as Figure 8 As shown, the projection of the top opening of the initial trench 120 onto the substrate 110 can cover the projection of the bottom surface of the initial trench 120 onto the substrate 110, and the initial trench 120 has a structure that is wider at the top and narrower at the bottom. Alternatively, as... Figure 9 As shown, the projection of the top opening of the initial trench 120 onto the substrate 110 can coincide with the projection of the bottom surface of the initial trench 120 onto the substrate 110, and the initial trench 120 has an equal width structure at the top and bottom. Alternatively, as... Figure 10 As shown, the projection of the top opening of the initial trench 120 onto the substrate 110 can fall within the projection range of the bottom surface of the initial trench 120 onto the substrate 110, and the initial trench 120 has a structure that is narrower at the top and wider at the bottom. In this embodiment, the initial trench 120 has a structure that is narrower at the top and wider at the bottom.

[0099] Step S212: Form a barrier layer that covers the sidewalls and top surface of the spacer structure.

[0100] like Figure 11 As shown, a barrier material can be deposited by atomic layer deposition (ALD) or low-pressure chemical vapor deposition (LPCVD). The barrier material covers the spacer structure 130 and the substrate 110 exposed by the spacer structure 130. Then, part of the barrier material is removed by dry or wet etching process to expose the substrate 110 covered by the barrier material. The retained barrier material forms a barrier layer 140, which covers the sidewalls and top surface of the spacer structure 130.

[0101] For example, the barrier material may include one or more of silicon nitride, silicon oxynitride, and silicon oxide. In this embodiment, the barrier material is silicon nitride.

[0102] Step S220: Deposit a first material, the first material fills the initial trench to form an initial filling layer, and an initial gap is formed in the initial filling layer.

[0103] In the embodiment, the first material is a semiconductor material doped with a first doping element. The first doping element can be an N-type doping ion or a P-type doping ion. Figure 12 As shown in FIG. 1A, referring to FIG. 1B, the first material fills the initial trench 120 to form an initial filling layer 210. Due to the characteristic that the semiconductor material is easy to be oxidized, a natural oxide layer (not shown in the figure) is formed on the top surface of the initial filling layer 210. Figure 11 As shown in FIG. 1A, referring to FIG. 1B, the first material fills the initial trench 120 to form an initial filling layer 210. Due to the characteristic that the semiconductor material is easy to be oxidized, a natural oxide layer (not shown in the figure) is formed on the top surface of the initial filling layer 210.

[0104] For example, the process of depositing the first material by low pressure chemical vapor deposition can be as follows: placing the semiconductor structure in a reaction chamber, providing a reaction source gas, a doping gas and a carrier gas into the reaction chamber, and depositing the first material by low pressure chemical vapor deposition process. The first material is a semiconductor material doped with a first doping element. The first material fills the initial trench 120 to form the initial filling layer 210. The process of filling the first material is affected by the edge effect, and an initial gap 211 is formed in the initial filling layer 210. The initial gap 211 is an irregular strip structure arranged in the initial filling layer 210.

[0105] The reaction source gas acts as a donor of the semiconductor material. For example, the first material can include a semiconductor material containing silicon or germanium. In this case, the reaction source gas can be one or more than two of a silicon source gas or a germanium source gas.

[0106] The doping gas acts as an ion injection source of the first doping element. For example, the first doping element can be a group V element in the periodic table. For example, the first doping element can be phosphorus, arsenic, antimony, etc. The doping gas can be phosphine (PH3) or hydrogen arsenide (AsH3), etc. The first doping element is doped into the first material as a donor impurity. The first material forms an N-type semiconductor doped material mainly conducting by electrons. Alternatively, the first doping element can also be a group III element in the periodic table. For example, the first doping element can be boron, aluminum, gallium, etc. The doping gas can be diborane boroethane (B2H6) or boron trichloride (BCl3), etc. The first doping element is doped into the first material as an acceptor impurity. The first material forms a P-type semiconductor doped material mainly conducting by holes.

[0107] In the embodiment, one or more doping gases and reaction source gases can be used to deposit the first material. When multiple doping gases are used to deposit the first material, the first doping elements provided by the multiple doping gases should be the same group elements to ensure the conductivity of the first material.

[0108] In the following, the process of depositing the first material in the embodiment is described by taking the first material as doped polysilicon.

[0109] For example, when the first material is N-type doped polycrystalline silicon, the semiconductor structure is placed in a reaction chamber, and silicon source gases such as silane (SiH4), disilene (Si2H4), or dichlorosilane (SiH2Cl) are introduced into the reaction chamber. Doping gases phosphine (PH3) and / or hydrogen arsenide (AsH3) are introduced into the reaction chamber, and hydrogen (H2) is introduced as a carrier gas. The deposition temperature is set to 350–700°C, and the deposition pressure is set to 0.2 Torr–4 Torr. N-type doped polycrystalline silicon is deposited using a low-pressure chemical vapor deposition process. When multiple silicon source gases are introduced, they can be introduced into the reaction chamber simultaneously or alternately. Similarly, when multiple doping gases are introduced, they can be introduced into the reaction chamber simultaneously or alternately.

[0110] For example, when the first material is P-type doped polycrystalline silicon, the doping gas is replaced with diboraneboroethane (B2H6) or boron trichloride (BCl3), and the remaining steps are the same as the operation of depositing N-type doped polycrystalline silicon.

[0111] Step S230: Inject a second dopant element into the initial filling layer. The second dopant element diffuses in the initial filling layer, and the initial filling layer forms a crystal defect layer.

[0112] like Figure 13 As shown, refer to Figure 12 A second dopant element is implanted into the initial filling layer 210 using an ion implantation process. When the second dopant element is implanted into the initial filling layer 210, the electrons and atomic nuclei of the first material are impacted by the second dopant element, causing the semiconductor lattice structure in the first material to break or be damaged, and a crystal defect layer 230 is formed in the initial filling layer 210.

[0113] In this embodiment, the second doping element is selected based on the conductivity type of the first material. When the first material is an N-type semiconductor doped material, P-type dopant ions are avoided as the second doping element, to prevent the holes provided by the P-type dopant ions from neutralizing the electrons in the N-type semiconductor doped material, thus affecting the conductivity of the first material. When the first material is a P-type semiconductor doped material, N-type dopant ions are avoided as the second doping element, to prevent the electrons provided by the N-type dopant ions from entering the holes in the P-type semiconductor doped material, thus affecting the conductivity of the first material.

[0114] The following description will continue with the first material being doped polycrystalline silicon.

[0115] When the first material is N-type doped polycrystalline silicon, the second dopant element can be one or more of germanium, phosphorus, and carbon. The energy for ion implantation of the second dopant element into the N-type doped polycrystalline silicon is set to 5–30 keV, and the dose of the second dopant element is set to 1E15–1E16 ion / cm³. 2 .

[0116] When the first material is P-type doped polycrystalline silicon, the second dopant can be one or more of germanium, boron, and carbon. The energy for ion implantation of the second dopant into the P-type doped polycrystalline silicon is set to 5–30 keV, and the dose of the second dopant is set to 1E15–1E16 ion / cm³. 2 .

[0117] Step S240: Annealing the crystal defect layer, recrystallizing the first material and the second dopant element to form the second material, the crystal defect layer to form the second material layer, and the initial gap to form the first gap.

[0118] High-temperature annealing processes are used to treat semiconductor structures, such as rapid thermal annealing (RTA) or furnace annealing. Figure 14 As shown, refer to Figure 13 The first material and the second dopant element in the crystal defect layer 230 recrystallize to form a new crystal lattice structure, forming the second material. During the recrystallization process, the recrystallized crystal lattice structure is rearranged, with some lattice elements arranging themselves in the initial gap 211, changing the shape of the initial gap 211 and filling part of it, thus forming the first gap 221. The first gap 221 is located in the second material layer 220. Compared to the initial gap 211, the first gap 221 is located lower in the second material layer 220 (closer to the substrate 110 direction), and the first gap 221 has a smaller volume and a more uniform structure.

[0119] like Figure 14 As shown, with a plane perpendicular to the substrate 110 and the extension direction of the second material layer 220 as the longitudinal section, the projection of the first gap 221 on the longitudinal section is a circular or near-circular structure.

[0120] For example, this embodiment will continue to be described using doped polycrystalline silicon as the first material.

[0121] Doped polycrystalline silicon with a second dopant element can be rapidly thermally annealed in a high-temperature environment of 900℃~1200℃. Alternatively, doped polycrystalline silicon with a second dopant element can be annealed in a furnace tube at a high-temperature environment of 600℃~800℃ for 10min~120min.

[0122] Step S250: removing part of the second material layer to expose part of the sidewall of the initial trench, the remaining second material layer forms a first filling part, and the top surface of the first filling part includes a gentle U-shaped groove.

[0123] As shown in Figure 15 , referring to Figure 14 , part of the second material layer 220 can be removed by a dry etching process or a wet etching process to expose part of the sidewall of the initial trench 120, and the remaining second material layer 220 forms a first filling part 200. In this step, the natural oxide layer formed on the top surface of the initial filling layer 210 is also removed. Then, the etching of the top surface of the first filling part 200 is continued to form a gentle U-shaped groove 201 on the top surface of the first filling part 200.

[0124] As shown in Figure 15 , the projection of the U-shaped groove 201 on the longitudinal section is an arc-shaped structure that is recessed from the top surface of the first filling part 200 to the substrate 110. The lowest point of the arc-shaped structure of the U-shaped groove 201 is higher than the top surface of the first gap 221, and the first gap 221 is enclosed in the first filling part 200.

[0125] The semiconductor structure formed in this embodiment changes the crystal structure of the semiconductor material by destroying the crystal structure of the first material in the initial filling layer through ion implantation and recrystallizing the first material and the second doping element to form the second material through an annealing process. The rearrangement of the crystal structure of the semiconductor material forms a first gap that is smaller and relatively uniform, reducing the impact of the gap filling vacancy on the first filling part. Moreover, after the first material is recrystallized to form the second material in this embodiment, the removal of part of the second material layer removes the natural oxide layer formed on the top surface of the initial filling layer. The top surface of the finally formed first filling part does not have a natural oxide layer, and the subsequent deposition of other materials to fill the initial trench can not only completely fill the remaining part of the initial trench, but also eliminate the natural oxide layer between the contact interface of the subsequent filling material and the first filling part, reducing the resistance of the conduction and improving the electrical performance of the semiconductor device.

[0126] According to an example embodiment, the present embodiment provides a method for manufacturing a semiconductor structure, as shown in Figure 3 , comprising the following steps:

[0127] Step S310: providing a substrate and forming an initial trench on the substrate.

[0128] Step S320: depositing a first material to fill the initial trench to form an initial filling layer, and forming an initial gap in the initial filling layer.

[0129] Step S330: removing part of the initial filling layer to expose part of the sidewall of the initial trench, and removing the first material around the initial gap to form a first recess in the remaining initial filling layer.

[0130] In this embodiment, the operation of forming the first recess 240 in the remaining initial filling layer 210a includes that part of the first material deposited in step S320 can cover the barrier layer 140 on the top surface of the spacer structure 130. As shown in FIG. 3B, with reference to FIG. 3A, first, the first material covering the top surface of the spacer structure 130 is removed to expose the barrier layer 140 on the top surface of the spacer structure 130 by a dry etching process or a wet etching process. At the same time, the natural oxide layer formed on the top surface of the initial filling layer 210 is also removed. Figure 17 Figure 12

[0131] As shown in FIG. 3C, with reference to FIG. 3B, the etching of part of the initial filling layer 210 in the initial trench 120 continues to expose the initial gap 211. Then, the first material around the initial gap 211 is removed to form the first recess 240 in the remaining initial filling layer 210a. Figure 18 Figure 17

[0132] As shown in FIG. 3D, with reference to FIG. 3C, in a longitudinal section with a plane perpendicular to the substrate 110 and perpendicular to the extension direction of the initial trench 120, the projection size of the top opening of the first recess 240 on the longitudinal section is greater than the projection size of the bottom wall of the first recess 240 on the longitudinal section. For example, the projection of the first recess 240 on the longitudinal section can be an inverted trapezoidal structure or an inverted triangular structure, etc. Figure 18

[0133] Step S340: implanting a second doping element into the first material, and the second doping element diffuses in the first material, and the remaining initial filling layer forms a crystalline defect layer.

[0134] Step S350: annealing the crystalline defect layer, and the first material and the second doping element recrystallize to form a second material, and the crystalline defect layer after the annealing forms a first filling part.

[0135] The operation of step S350 of this embodiment is the same as the operation of step S240 of the above embodiment. The difference is that the structure of the remaining initial filling layer 210a includes the first recess 240, and the first recess 240 is a wide-top-narrow-bottom structure. Therefore, as shown in FIG. 3E, with reference to FIG. 3D, in the recrystallization process of the first material and the second doping element, part of the lattice of the semiconductor material is rearranged and filled into the first recess 240, which changes the shape of the first recess 240. Figure 19 Figure 20 Figure 18 ​​​​​​​​

[0136] As shown in Figure 20 , the first groove 240 forms a U-shaped groove 201, and a projection of the U-shaped groove 201 on a longitudinal section of a plane perpendicular to the substrate 110 and perpendicular to an extension direction of the first filling part 200 is an arc-shaped structure recessed from a top surface of the first filling part 200 to the substrate 110.

[0137] The implementation manners of steps S310, S320, S340, S350 of the embodiment and steps S210-S240 of the above embodiment are the same, and thus details are not repeated here.

[0138] In the embodiment, the first material around the initial gap is removed by etching to form a first groove with a wide upper part and a narrow lower part in the retained initial filling layer, and then a second doping element is ion implanted into the retained initial filling layer. The first material and the second doping element are recrystallized to form the first filling part. The lattice rearrangement in the recrystallization process of the first material and the second doping element changes the structure of the first groove. The first groove is directly formed as a U-shaped groove. The top surface of the first filling part does not need to be etched to form a gentle U-shaped structure on the top surface of the first filling part, thereby reducing the process steps of forming the first filling part.

[0139] According to an example embodiment, the embodiment provides a method for manufacturing a semiconductor structure, as shown in Figure 4 , the method comprises the following steps:

[0140] Step S410: providing a substrate and forming an initial trench on the substrate.

[0141] Step S420: depositing a first material, the first material filling the initial trench to form an initial filling layer, and an initial gap is formed in the initial filling layer.

[0142] Step S430: processing the first material by using a first process.

[0143] Step S440: forming a first filling part, the first filling part comprising a second material, the first filling part covering part of the initial trench, and a top surface of the first filling part being provided with a gentle U-shaped groove.

[0144] Step S450: forming a second filling part, the second filling part covering the top surface of the first filling part and filling a region of the initial trench not covered by the first filling part.

[0145] The implementation manners of steps S410-S440 of the embodiment and steps S110-S140 of the above embodiment are the same, and thus details are not repeated here.

[0146] As shown in Figure 16 , referring to Figure 15 , or as shown in Figure 21 , referring toFigure 20 In step S450, the third material is deposited by atomic layer deposition (ALD) or low-pressure chemical vapor deposition (LPCVD) to fill the initial trench 120 not covered by the first filling part 200, forming a second filling part 300. Since the first filling part 200 has filled part of the initial trench 120, the aspect ratio of the initial trench 120 to be filled by the third material is reduced, and the influence of the edge effect on the third material is reduced. The third material filling the initial trench 120 will not cause filling vacancies, and the second filling part 300 formed will not have voids. Moreover, the third material also fills the U-shaped groove 201 on the top surface of the first filling part 200, and the bottom surface of the second filling part 300 can be closely combined with the top surface of the first filling part 200, reducing the contact resistance between the first filling part 200 and the second filling part 300 and increasing the electrical performance of the semiconductor device.

[0147] The third material can be the same as or different from the first material. The first material is a conductive doped semiconductor dopant material, and the third material is an N-type doped semiconductor material. The first filling part 200 and the second filling part 300 form a good conductive connection. Similarly, the first material is a P-type doped semiconductor material, and the third material can be a P-type doped semiconductor material or an undoped semiconductor material.

[0148] The semiconductor structure formed in the embodiment fills the area of the initial trench not covered by the first filling part with the second filling part, and the second filling part also fills the U-shaped groove on the top surface of the first filling part. The bottom surface of the second filling part and the top surface of the first filling part, and the contact resistance between the first filling part and the second filling part is small, improving the electrical performance of the semiconductor structure.

[0149] According to an exemplary embodiment, the semiconductor structure provided by the embodiment includes a substrate 110, an initial trench 120 disposed on the substrate 110, and a first filling part 200. The first filling part 200 covers part of the initial trench 120, and the top surface of the first filling part 200 is provided with a flat U-shaped groove 201. The first filling part 200 includes a second material, and the second material includes a first dopant element and a second dopant element. Figure 15 or as shown in Figure 20 The semiconductor structure includes a substrate 110, an initial trench 120 disposed on the substrate 110, and a first filling part 200. The first filling part 200 covers part of the initial trench 120, and the top surface of the first filling part 200 is provided with a flat U-shaped groove 201. The first filling part 200 includes a second material, and the second material includes a first dopant element and a second dopant element.

[0150] The second material can be a semiconductor material, an insulating material, or a conductive material, and the first dopant element and the second dopant element can be the same or different.

[0151] In the embodiment, the second material is a conductive doped semiconductor material, and the second material can be a semiconductor material containing silicon or germanium.

[0152] When the second material is an N-type doped semiconductor material, the first doping element can be an element of group V in the periodic table, for example, the first doping element can be phosphorus, arsenic, antimony. The second doping element can include one or more of germanium, phosphorus or carbon.

[0153] When the second material is a P-type doped semiconductor material, the first doping element can be an element of group III in the periodic table, for example, the first doping element can be boron, aluminum, gallium, etc. The second doping element can include one or more of germanium, boron or carbon.

[0154] In the semiconductor structure of the embodiment, the top surface of the first filling part 200 is a gentle U-shaped groove 201, and the first filling part 200 fills part of the initial groove 120, reducing the aspect ratio of the part of the initial groove 120 that is not filled, and reducing the difficulty of subsequent filling of the initial groove 120.

[0155] According to an example embodiment, most of the semiconductor structure of the embodiment is the same as the above-mentioned embodiments, and the difference between the embodiment and the above-mentioned embodiments is that, as shown in Figure 15 or as shown in Figure 20 , the projection of the U-shaped groove 201 on the longitudinal section is an arc-shaped structure that is recessed from the top surface of the first filling part 200 to the substrate 110.

[0156] According to an example embodiment, most of the semiconductor structure of the embodiment is the same as the above-mentioned embodiments, and the difference between the embodiment and the above-mentioned embodiments is that, as shown in Figure 15 , the first filling part 200 further includes a first gap 221, and the projection of the first gap 221 on the longitudinal section is a circular or quasi-circular structure; the arc-shaped bottom surface of the U-shaped groove 201 is higher than the top surface of the first gap 221, and the first gap 221 is enclosed in the first filling part 200.

[0157] In the embodiment, the structure of the first gap 221 is uniform and the volume is small, and the first gap 221 has little effect on the semiconductor structure.

[0158] According to an example embodiment, most of the semiconductor structure of the embodiment is the same as the above-mentioned embodiments, and the difference between the embodiment and the above-mentioned embodiments is that, as shown in Figure 16 or as shown in Figure 21As shown, the semiconductor structure further includes a second filling portion 300, which covers the top surface of the first filling portion 200 and fills the area in the initial trench 120 that is not covered by the first filling portion 200.

[0159] In the semiconductor structure of this embodiment, the second filling portion 300 fills the initial trench 120 and fills the U-shaped groove 201 on the top surface of the first filling portion 200. The contact resistance between the bottom surface of the second filling portion 300 and the top surface of the first filling portion 200, the contact surface of the first filling portion 200 and the second filling portion 300 is small, and there is no natural oxide layer at the contact interface of the first filling portion 200 and the second filling portion 300, which improves the conductivity of the semiconductor structure.

[0160] According to an exemplary embodiment, most of the semiconductor structure in this embodiment is the same as that in the above embodiments. The difference between this embodiment and the above embodiments is that, Figure 16 Or such as Figure 21 As shown, the semiconductor structure also includes: a spacer structure 130 disposed on the substrate 110 and a blocking structure covering the sidewalls and top surface of the spacer structure 130, and an initial trench 120 disposed between adjacent spacers 130.

[0161] Among them, reference Figure 8 The initial trench 120 can be a structure that is wider at the top and narrower at the bottom. The projection dimension of the top opening of the initial trench 120 on the longitudinal section is larger than the projection of the bottom surface of the initial trench 120 on the longitudinal section. (Refer to...) Figure 9 The initial trench 120 can also be a structure with equal width at the top and bottom, where the projected size of the top opening of the initial trench 120 on the longitudinal section is the same as the projected size of the bottom surface of the initial trench 120 on the longitudinal section. Alternatively, refer to... Figure 10 The initial groove 120 can also be a structure that is narrow at the top and wide at the bottom. The projection size of the top opening of the initial groove 120 on the longitudinal section is smaller than the projection formed by the bottom surface of the initial groove 120 on the longitudinal section.

[0162] The semiconductor structure fabrication method and semiconductor structure disclosed herein involve disrupting the internal structure of a first material and then rearranging the internal structure of the first material to form a second material. During the rearrangement of the internal structure of the first material, the structure of the initial gap is changed, so that the initial gap forms a more gently sloping and smaller void, thereby reducing the impact of filling the void on the conductivity of the semiconductor structure.

[0163] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0164] In the description of the specification, the description of the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0165] In the description of the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0166] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0167] It can be understood that the terms "first", "second", and the like used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

[0168] In one or more drawings, the same elements are denoted by similar reference numerals. For the sake of clarity, parts of the drawings are not drawn to scale. In addition, some well-known parts can not be shown. For the sake of simplicity, structures obtained after several steps can be described in one drawing. Many specific details of the present disclosure are described below, such as the structure, material, size, processing process and technique of the device, in order to make the present disclosure more clearly understood. But as those skilled in the art can understand, the present disclosure can be implemented without these specific details.

[0169] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, the method comprising: providing a substrate and forming an initial trench on the substrate; depositing a first material to fill the initial trench to form an initial fill layer, the initial fill layer having an initial gap therein; processing the first material using a first process; forming a first fill portion comprising a second material, the first fill portion covering a portion of the initial trench, a top surface of the first fill portion having a gently U-shaped recess; the first material comprising a first dopant element; the second material comprising the first dopant element and a second dopant element; the processing the first material using the first process comprising: implanting the second dopant element into the initial fill layer, the second dopant element diffusing in the initial fill layer to form a crystalline defect layer; and annealing the crystalline defect layer, the first material recrystallizing with the second dopant element to form the second material, the crystalline defect layer forming a second material layer, the initial gap forming a first gap, a longitudinal cross-section of the first gap being a plane perpendicular to the substrate and perpendicular to an extension direction of the second material layer, a projection of the first gap on the longitudinal cross-section being a circular or quasi-circular structure. 2.The method of claim 1, wherein the forming the first fill portion comprising the second material, the first fill portion covering a portion of the initial trench, further comprises: removing a portion of the second material layer to expose a portion of a sidewall of the initial trench, the second material layer remaining forming the first fill portion, a top surface of the first fill portion having the gently U-shaped recess. 3.The method of claim 2, wherein a projection of the U-shaped recess on the longitudinal cross-section is an arc-shaped structure concave from the top surface of the first fill portion to the substrate; and a lowest point of the arc-shaped structure of the U-shaped recess is higher than a top surface of the first gap, the first gap being enclosed in the first fill portion. 4.The method of claim 1, further comprising: removing a portion of the initial fill layer to expose a portion of a sidewall of the initial trench, and removing the first material around the initial gap to form a first recess in the initial fill layer remaining. 5.The method of claim 4, wherein a projection of a top opening of the first recess on a longitudinal cross-section being a plane perpendicular to the substrate and perpendicular to an extension direction of the initial trench has a size larger than a projection of a bottom wall of the first recess on the longitudinal cross-section. 6.The method of claim 5, wherein the processing the first material using the first process comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ injecting the second doping element into the first material, the second doping element diffusing in the first material, the retained initial fill layer forming a crystalline defect layer; annealing the crystalline defect layer, the first material and the second doping element recrystallizing to form the second material, the crystalline defect layer after the annealing forming the first fill portion; the first recess forms the U-shaped recess, a plane perpendicular to the substrate and perpendicular to an extension direction of the first fill portion being a longitudinal section plane, a projection of the U-shaped recess on the longitudinal section plane being an arc structure recessed from a top surface of the first fill portion toward the substrate.

7. The method of claim 1, wherein: the method of fabricating the semiconductor structure further comprises: forming a second fill portion covering a top surface of the first fill portion and filling a region of the initial trench not covered by the first fill portion.

8. The method of claim 1, wherein: the method of fabricating the semiconductor structure further comprises: forming a spacer structure disposed on the substrate, the initial trench being formed between adjacent spacer structures; forming a barrier layer covering a sidewall and a top surface of the spacer structure.

9. A semiconductor structure fabricated by the method of any one of claims 1-8, wherein: the semiconductor structure comprises: a substrate; an initial trench disposed on the substrate; a first fill portion covering a portion of the initial trench, a top surface of the first fill portion being disposed including a gentle U-shaped recess; the first fill portion comprises a second material, the second material comprising a first doping element and a second doping element.

10. The semiconductor structure of claim 9, wherein: a plane perpendicular to the substrate and perpendicular to an extension direction of the first fill portion is a longitudinal section plane, a projection of the U-shaped recess on the longitudinal section plane being an arc structure recessed from a top surface of the first fill portion toward the substrate.

11. The semiconductor structure of claim 10, wherein: the first fill portion further comprises a first gap, a plane perpendicular to the substrate and perpendicular to an extension direction of the first fill portion being a longitudinal section plane, a projection of the first gap on the longitudinal section plane being a circular or circular-like structure; a bottom surface of the U-shaped recess is higher than a top surface of the first gap, the first gap being enclosed in the first fill portion.

12. The semiconductor structure of claim 9, wherein: the semiconductor structure further comprises: a second fill portion covering a top surface of the first fill portion and filling a region of the initial trench not covered by the first fill portion.

13. The semiconductor structure of claim 9, wherein: the semiconductor structure further comprises: a spacer structure disposed on the substrate, the initial trench being disposed between adjacent spacer structures; a barrier structure covering the sidewalls and top surface of the spacer structure.

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