Semiconductor device and method of manufacturing mim capacitor device and semiconductor device

Abstract

The application discloses a semiconductor device and a manufacturing method of a MIM capacitor device and the semiconductor device, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor substrate; forming a multilayer amorphous dielectric layer on the semiconductor substrate; removing at least one layer of the multilayer amorphous dielectric layer in at least one preset area to form at least one removal space, wherein along the height direction of the semiconductor substrate, the upper surface and the lower surface of the removal space are distributed with corresponding amorphous dielectric layers, and the surface of the corresponding amorphous dielectric layer exposed through the removal space is an amorphous surface; and forming a metal layer in the removal space. The manufacturing method of the semiconductor device can reduce the surface roughness of the metal layer and the dielectric layer, and for the MIM capacitor, the surface roughness of the metal plate and the dielectric layer can be reduced, the TDDB characteristics of the capacitor device are effectively improved, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to methods for manufacturing semiconductor devices and MIM capacitors, as well as semiconductor devices in general. Background Technology

[0002] In the application of integrated circuits, the performance of various devices is affected by the roughness between the layers of materials. In order to reduce the roughness between the layers of materials, they are generally fabricated by stacking.

[0003] In practice, the inventors of this application have discovered that in current semiconductor device manufacturing processes, during the stacking of metal layers and dielectric layers, the metal layer, being a crystalline material during manufacturing, has a high surface roughness due to metal crystallization, which affects the performance of the semiconductor device. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a method for manufacturing a semiconductor device and a MIM capacitor, as well as a semiconductor device, which can reduce the surface roughness of the metal layer and the dielectric layer, improve the TDDB (Time Dependent Dielectric Breakdown) characteristic of the capacitor, and thus improve the performance of the semiconductor device.

[0005] To solve the above-mentioned technical problems, the present application adopts a technical solution as follows: providing a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; forming multiple amorphous dielectric layers on the semiconductor substrate; removing at least one amorphous dielectric layer in at least a predetermined region to form at least one removal space, wherein, along the height direction of the semiconductor substrate, the upper surface and / or lower surface of the removal space are provided with corresponding amorphous dielectric layers; and forming a metal layer in the removal space.

[0006] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a method for manufacturing a MIM capacitor; comprising: providing a semiconductor substrate; forming a first amorphous dielectric layer, a second amorphous dielectric layer, a third amorphous dielectric layer, a fourth amorphous dielectric layer, and a fifth amorphous dielectric layer on the semiconductor substrate; removing the second amorphous dielectric layer and the fourth amorphous dielectric layer in at least one of the predetermined regions to form a first removal space and a second removal space, wherein, along the height direction of the semiconductor substrate, the upper and lower surfaces of the first removal space are provided with corresponding first amorphous dielectric layers and the third amorphous dielectric layer. The upper and lower surfaces of the second removal space are respectively provided with the third amorphous dielectric layer and the fifth amorphous dielectric layer; the upper surface of the first amorphous dielectric layer and the lower surface of the third amorphous dielectric layer are exposed through the first removal space and are respectively amorphous surfaces; the upper surface of the third amorphous dielectric layer and the lower surface of the fifth amorphous dielectric layer are exposed through the second removal space and are respectively amorphous surfaces; a first metal layer is formed in the first removal space and a second metal layer is formed in the second removal space, wherein the first metal layer, the third amorphous dielectric layer and the second metal layer constitute a MIM capacitor device.

[0007] In one embodiment of this application, the materials of the second amorphous dielectric layer and the fourth amorphous dielectric layer are different from those of the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer; and / or for at least one etching process, the etching selectivity ratio of the second amorphous dielectric layer and the fourth amorphous dielectric layer is greater than that of the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer.

[0008] In one embodiment of this application, the second amorphous dielectric layer and the fourth amorphous dielectric layer are made of the same material, while the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer are made of another material.

[0009] In one embodiment of this application, removing the second amorphous dielectric layer and the fourth amorphous dielectric layer in the preset region to form a first removal space and a second removal space includes: forming an opening in the preset region of the MIM capacitor device, wherein the opening at least exposes the side surfaces of the second amorphous dielectric layer, the third amorphous dielectric layer, the fourth amorphous dielectric layer, and the fifth amorphous dielectric layer in the preset region of the MIM capacitor device; selecting at least one etching process to etch the second amorphous dielectric layer and the fourth amorphous dielectric layer, wherein the etching selectivity of the at least one etching process for the second amorphous dielectric layer and the fourth amorphous dielectric layer is greater than the etching selectivity of the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer, so as to retain the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer during the etching process, thereby forming the first removal space and the second removal space.

[0010] In one embodiment of this application, forming a first metal layer in the first removal space and forming a second metal layer in the second removal space includes: depositing metal material on the first removal space, the second removal space, the opening, and the fifth amorphous dielectric layer by atomic layer deposition or physical vapor deposition; removing excess metal material on the fifth amorphous dielectric layer; and forming the upper and lower plates of the MIM capacitor.

[0011] In one embodiment of this application, a sixth dielectric layer is formed on the upper and lower electrode plates, and a contact plug for the upper and lower electrode plates is formed on the sixth dielectric layer.

[0012] In one embodiment of this application, the first amorphous dielectric layer serves as a barrier layer with a thickness between 40-100 nm; the third amorphous dielectric layer serves as a dielectric layer of a MIM capacitor; and the fifth amorphous dielectric layer serves as a hard mask layer with a thickness between 35-100 nm.

[0013] In one embodiment of this application, the semiconductor substrate includes a substrate and a device structure, isolation structure, dielectric layer or interconnect structure disposed in or on the substrate.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a semiconductor device, comprising: a semiconductor substrate; multiple amorphous dielectric layers disposed on the semiconductor substrate; and at least one metal layer formed between two adjacent corresponding amorphous dielectric layers, wherein the surfaces of the two adjacent corresponding amorphous dielectric layers facing the metal layer are amorphous surfaces.

[0015] In one embodiment of this application, the multilayer amorphous dielectric layer includes a first amorphous dielectric layer, a third amorphous dielectric layer, and a fifth amorphous dielectric layer disposed sequentially; the at least one metal layer includes a first metal layer and a second metal layer, wherein the first metal layer is located between the first amorphous dielectric layer and the third amorphous dielectric layer, and the surfaces of the first amorphous dielectric layer and the third amorphous dielectric layer facing the first metal layer are amorphous surfaces; the second metal layer is located between the third amorphous dielectric layer and the fifth amorphous dielectric layer, and the surfaces of the third amorphous dielectric layer and the fifth amorphous dielectric layer facing the second metal layer are amorphous surfaces.

[0016] Unlike existing technologies, this application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; depositing multiple amorphous dielectric layers on the semiconductor substrate; removing at least one amorphous dielectric layer from the multiple amorphous dielectric layers in at least a predetermined region to form at least one removal space, wherein corresponding amorphous dielectric layers are distributed on the upper or lower surface of the removal space along the height direction of the semiconductor substrate, and the surface of the corresponding amorphous dielectric layer exposed through the removal space is an amorphous surface; and forming a metal layer in the removal space. That is, this application forms the removal space by first depositing multiple amorphous dielectric layers and then etching some of them. Because the removal space is composed of amorphous dielectric layers, the surface of the amorphous dielectric layers can make the surface of the subsequently formed metal layer smooth during the metal layer deposition process, thereby reducing the surface roughness of the metal layer and the dielectric layer. For MIM capacitors, this can reduce the surface roughness of the metal plates and the dielectric layer, improve the TDDB characteristics of the capacitor, and thus improve the performance of the semiconductor device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application;

[0019] Figure 2 This is a schematic diagram of the structure of an embodiment of the semiconductor substrate in this application;

[0020] Figure 3 This is a schematic diagram of the structure of forming multiple amorphous dielectric layers on a semiconductor substrate in this application;

[0021] Figure 4 This is a schematic diagram of a structure forming an etched region in a multilayer amorphous dielectric layer according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of a structure forming a removal space in a multilayer amorphous dielectric layer according to an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of a structure in which a metal layer is formed in a removal space according to an embodiment of this application;

[0024] Figure 7 This is a schematic flowchart of an embodiment of the manufacturing method of the MIM capacitor device in this application;

[0025] Figure 8 This is a schematic diagram of a structure for depositing multiple amorphous dielectric layers on a semiconductor substrate according to an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of a structure in which an opening is formed in a preset area, according to an embodiment of this application;

[0027] Figure 10 This is a schematic diagram of the structure forming the first removal space and the second removal space provided in an embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the structure for forming a first metal layer and a second metal layer according to an embodiment of this application;

[0029] Figure 12 This is a schematic diagram of a stepped structure provided in one embodiment of this application;

[0030] Figure 13 This is a schematic diagram of the structure of a MIM capacitor provided in one embodiment of this application;

[0031] Figure 14 This is a top view schematic diagram of a MIM capacitor device provided in an embodiment of this application.

[0032] Explanation of reference numerals in the attached figures:

[0033] Semiconductor substrate 100; preset region 110; opening 120; first amorphous dielectric layer 200; second amorphous dielectric layer 300; third amorphous dielectric layer 400; fourth amorphous dielectric layer 500; fifth amorphous dielectric layer 600; first removal space 310; second removal space 510; first metal layer 320; second metal layer 520; sixth dielectric layer 700; first conductive plug 820; second conductive plug 810; first connection terminal 920; second connection terminal 910; inner region 10 of MIM capacitor; outer region 11 of MIM capacitor. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0035] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] In current semiconductor device manufacturing processes, metal and dielectric layers are typically deposited sequentially to form a stacked structure. During this process, the metal layer exhibits high interface roughness due to metal crystallization, which in turn affects the roughness of the dielectric layers above it. This high interface roughness makes it easier for interface traps to form at the metal / dielectric interface, trapping electrons and significantly increasing the local electric field strength. MIM (Metal-Insulator-Metal) capacitors, consisting of a lower metal plate, an intermediate dielectric layer, and a top metal plate, are formed through sequential deposition. The high interface roughness of the metal layer in MIM capacitors leads to the degradation of dielectric molecules at the metal and dielectric layers, creating destructive conductive channels and causing capacitor breakdown. This also negatively impacts the performance of semiconductor devices that require high surface roughness in both metal and dielectric layers.

[0039] Therefore, a method for manufacturing semiconductor devices is proposed. This method involves first forming stacked amorphous dielectric layers, then removing some of these layers to create removal spaces. Since the removal spaces are topped and / or bottomed by amorphous dielectric layers, the surface of the amorphous dielectric layers can smooth the surface of the subsequently formed metal layers during metal deposition, thereby reducing the surface roughness of both the metal and dielectric layers. For MIM capacitors, this reduces the surface roughness of the metal plates and dielectric layers, improves the TDDB characteristics of the capacitor, and enhances the performance of the semiconductor device.

[0040] Please see Figure 1 , Figure 1 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method of this application. The semiconductor device manufacturing method of this application is generally used in semiconductor device manufacturing processes where the interface roughness of each layer material is critical. It can reduce the interface roughness between the metal layer and the dielectric layer. For MIM capacitors, this can improve the TDDB characteristics of the capacitor, thereby enhancing the performance of the semiconductor device.

[0041] like Figure 1 As shown, the method for manufacturing the semiconductor device of this application includes:

[0042] S11, Provide semiconductor substrate.

[0043] Specifically, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a semiconductor substrate according to an embodiment of this application. It can be understood that, as Figure 2As shown, the semiconductor substrate 100 includes a substrate. The substrate can be a silicon substrate, a germanium substrate, an SOI (Semiconductor on Insulator, such as silicon on insulator, germanium on insulator, or silicon-germanium on insulator) substrate, or various other substrates. Those skilled in the art will understand that the substrate is not limited in any way, but can be selected according to the actual application.

[0044] In other embodiments, the semiconductor substrate 100 may also include device structures (such as transistors), isolation structures, dielectric layers, or interconnect structures disposed in or on the substrate (not shown in the figures). Those skilled in the art will understand that the device structures, isolation structures, dielectric layers, or interconnect structures are not limited in any way, but can be selected according to the actual application.

[0045] S12. Forming multiple amorphous dielectric layers on a semiconductor substrate.

[0046] Please see Figure 3 , Figure 3 This is a schematic diagram of a structure in which multiple amorphous dielectric layers are formed on a semiconductor substrate, according to an embodiment of this application. Figure 3 As shown, the semiconductor device includes a semiconductor substrate 100 and at least two amorphous dielectric layers deposited on the semiconductor substrate 100. These at least two amorphous dielectric layers can be three, five, ten, etc., and can be configured according to the specific semiconductor device being described.

[0047] Specifically, in this embodiment, a three-layer amorphous dielectric layer is used as an example for illustration. A first amorphous dielectric layer 200, a second amorphous dielectric layer 300, and a third amorphous dielectric layer 400 are sequentially deposited on a semiconductor substrate 100. Since each dielectric layer is an amorphous dielectric layer, and there is no metal crystallization during the metal growth process between the amorphous dielectric layers, the surface of the amorphous dielectric layer is relatively flat.

[0048] S13. Remove at least one amorphous dielectric layer from the multilayer amorphous dielectric layers in at least one preset region to form at least one removal space.

[0049] Along the height direction of the semiconductor substrate, the upper and / or lower surfaces of the removal space are provided with corresponding amorphous dielectric layers, and the surfaces of the corresponding amorphous dielectric layers exposed through the removal space are amorphous surfaces.

[0050] Please see Figure 4 and Figure 5 , Figure 4 This is a schematic diagram of a structure forming an etched region in a multilayer amorphous dielectric layer according to an embodiment of this application. Figure 5This is a schematic diagram illustrating a structure forming a removal space in a multilayer amorphous dielectric layer according to an embodiment of this application. "Multilayer" means at least two layers; this embodiment uses a three-layer amorphous dielectric layer as an example. The at least one amorphous dielectric layer to be removed is, for example, a sacrificial dielectric layer. Figure 4 As shown, an opening 120 is formed in the semiconductor device, exposing at least the sidewalls of the sacrificial dielectric layer. A predetermined region 110 is selected in the height direction of the semiconductor device, and the predetermined region 110 is exposed, developed, and then etched to form an opening 120. Subsequently, as... Figure 5 As shown, the second amorphous dielectric layer is used as the sacrificial dielectric layer. The sacrificial dielectric layer is removed starting from the sidewall exposed by the opening 120. That is, the second amorphous dielectric layer 300 is etched away in the preset region 110 to form a first removal space 310 between the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400. The etching selectivity of the second amorphous dielectric layer is greater than that of the first amorphous dielectric layer and the third amorphous dielectric layer.

[0051] S14. Form a metal layer in the removal space.

[0052] Please see Figure 6 , Figure 6 This is a schematic diagram of a structure in which a metal layer is formed in a removal space, according to an embodiment of this application. Figure 6 As shown, after the first removal space 310 is formed, a metal material is deposited in the removal space 310 by atomic layer deposition or physical vapor deposition to form a first metal layer 320 in the removal space, thereby forming a semiconductor device.

[0053] The above technical solution provides a semiconductor device fabrication method, including: providing a semiconductor substrate 100; depositing multiple amorphous dielectric layers on the semiconductor substrate 100; removing at least one amorphous dielectric layer from the multiple amorphous dielectric layers in a predetermined region to form at least one removal space, wherein corresponding amorphous dielectric layers are distributed on the upper and / or lower surfaces of the removal space along the height direction of the semiconductor substrate 100; and forming a metal layer in the removal space. That is, this application forms the removal space by first depositing multiple amorphous dielectric layers and then etching some of the amorphous dielectric layers. Because the upper and / or lower surfaces of the removal space are distributed with amorphous dielectric layers, during the metal layer deposition process, the amorphous surface can make the surface of the metal layer smooth, reducing the surface roughness of the metal layer and the amorphous dielectric layer, thereby improving the performance of the semiconductor device.

[0054] Please see Figure 7 , Figure 7This is a schematic flowchart of an embodiment of the manufacturing method of the MIM capacitor device of this application. In this embodiment, the semiconductor device is a MIM capacitor device. The manufacturing method of the MIM capacitor device of this application can reduce the interface roughness between the metal plate and the dielectric layer, improve the TDDB characteristics of the capacitor device, and thus improve the performance of the semiconductor device.

[0055] S21, Provide semiconductor substrate.

[0056] See Figure 2 This will not be elaborated upon here.

[0057] S22. A first amorphous dielectric layer, a second amorphous dielectric layer, a third amorphous dielectric layer, a fourth amorphous dielectric layer and a fifth amorphous dielectric layer are formed on a semiconductor substrate;

[0058] The material of the second amorphous dielectric layer 300 is different from that of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600; the material of the fourth amorphous dielectric layer 500 is different from that of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600. The second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 can be made of the same material, while the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600 can be made of another material. For at least one etching process, the etching selectivity ratio of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 is greater than the etching selectivity ratio of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600, so that when etching the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500, the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600 can be preserved.

[0059] Please see Figure 8 , Figure 8 This is a schematic diagram of a structure in which multiple amorphous dielectric layers are deposited on a semiconductor substrate according to an embodiment of this application. Figure 8 As shown, the semiconductor device includes a semiconductor substrate 100 and a first amorphous dielectric layer 200, a second amorphous dielectric layer 300, a third amorphous dielectric layer 400, a fourth amorphous dielectric layer 500 and a fifth amorphous dielectric layer 600 deposited on the semiconductor substrate 100. Since each dielectric layer is an amorphous dielectric layer, metal crystallization does not occur during deposition. Therefore, the interface of the amorphous dielectric layer is relatively flat, so that the subsequently formed metal layer is also relatively flat, that is, the surface roughness of the metal layer is reduced.

[0060] Specifically, in this embodiment, the semiconductor substrate 100 includes a substrate, wherein, taking five amorphous dielectric layers as an example, a first amorphous dielectric layer 200, a second amorphous dielectric layer 300, a third amorphous dielectric layer 400, a fourth amorphous dielectric layer 500, and a fifth amorphous dielectric layer 600 are sequentially formed on the semiconductor substrate 100. For example, the above-mentioned amorphous dielectric layers are sequentially deposited using a CVD process. CVD is short for Chemical Vapor Deposition.

[0061] In other embodiments, the semiconductor substrate 100 may also include device structures (such as transistors), isolation structures, dielectric layers, or interconnect structures disposed in or on the substrate. Those skilled in the art will understand that the device structures, isolation structures, dielectric layers, or interconnect structures are not limited in any way, but can be selected according to the actual application.

[0062] The first amorphous dielectric layer 200 serves as a barrier layer, preventing the upward diffusion of certain materials in the semiconductor substrate 100, such as Cu. Its thickness is between 40-100 nm. The third amorphous dielectric layer 400 serves as the dielectric layer of the MIM capacitor. Its thickness is determined according to the capacitance value of the MIM capacitor. For example, a 32 nm third amorphous dielectric layer 400 corresponds to a capacitance value of 2 fF, and a 130 nm third amorphous dielectric layer 400 corresponds to a capacitance value of 0.5 fF. The fifth amorphous dielectric layer 600 serves as a hard mask layer. To ensure that windows can be opened in the fifth amorphous dielectric layer 600 later, its thickness is between 35-100 nm. Since a first metal layer 320 and a second metal layer 520 need to be fabricated at the locations of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 as the upper and lower metal plates of the subsequent MIM capacitor device, and the thickness of the metal plates determines the resistance of the plates, the thickness of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 is between 30-100nm.

[0063] In this embodiment, the material of the second amorphous dielectric layer 300 is different from the materials of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600; the material of the fourth amorphous dielectric layer 500 is different from the materials of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600. In one embodiment, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 may be made of the same material, while the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600 may be made of another material. In another embodiment, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 may also be made of different materials. For at least one etching process, the etching selectivity of the second amorphous dielectric layer 300 needs to be greater than the etching selectivity of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600, and the etching selectivity of the fourth amorphous dielectric layer 500 needs to be greater than the etching selectivity of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600, so that when etching the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500, the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600 can be preserved.

[0064] To ensure process stability, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are usually made of the same material, while the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 are usually made of another material.

[0065] The amorphous dielectric layer can be made of silicon dioxide and / or silicon nitride, and the appropriate material can be selected according to the manufacturing requirements of the semiconductor device.

[0066] S23. Remove the second amorphous dielectric layer and the fourth amorphous dielectric layer in at least one preset region to form a first removal space and a second removal space.

[0067] Along the height direction of the semiconductor substrate 100, a first amorphous dielectric layer 200 and a third amorphous dielectric layer 400 are distributed vertically in the first removal space 310, and a third amorphous dielectric layer 400 and a fifth amorphous dielectric layer 600 are distributed vertically in the second removal space 300. The upper surface of the first amorphous dielectric layer 200 and the lower surface of the third amorphous dielectric layer 400 are exposed through the first removal space 310 and are amorphous surfaces, respectively. The upper surface of the third amorphous dielectric layer 400 and the lower surface of the fifth amorphous dielectric layer 600 are exposed through the second removal space 510 and are amorphous surfaces, respectively.

[0068] Please see Figure 9 , Figure 9 This is a schematic diagram of a structure in which an opening is formed in a predetermined area, according to an embodiment of the present invention. Figure 9 As shown, an opening 120 is formed in a preset region 110 of the MIM capacitor, and at least the second amorphous dielectric layer 300, the third amorphous dielectric layer 400, the fourth amorphous dielectric layer 500 and the 600 side surface of the fifth amorphous dielectric layer are exposed through the opening 120.

[0069] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure forming the first removal space and the second removal space according to an embodiment of this application. Figure 10 As shown, in Figure 9 Based on this, a first removal space 310 and a second removal space 510 are formed by etching the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 within a predetermined region 130 of the MIM capacitor device. Specifically, for at least one etching process, the etching selectivity ratio of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 is greater than the etching selectivity ratio of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600. This ensures that when the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are etched during the etching process, the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600 are retained, thereby forming the first removal space 310 and the second removal space 510.

[0070] S24. A first metal layer is formed in the first removal space, and a second metal layer is formed in the second removal space, wherein the first metal layer, the third amorphous dielectric layer, and the second metal layer constitute a MIM capacitor device.

[0071] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure for forming a first metal layer and a second metal layer according to an embodiment of this application. Figure 11 As shown, in Figure 10 Based on this, metallic materials are deposited on the first removal space 310, the second removal space 510, the opening 140, and the fifth amorphous dielectric layer 600 using atomic layer deposition or physical vapor deposition. The metallic material remaining between the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400 serves as the first metal layer 320, and the metallic material remaining between the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 serves as the second metal layer 520. Excess metallic material on the fifth amorphous dielectric layer 600 is removed by etching or planarization processes.

[0072] Please see Figure 12 , Figure 12This is a schematic diagram of a stepped structure provided in an embodiment of this application.

[0073] In actual operation, Figure 11 Based on this, the upper and lower electrodes of the MIM capacitor device need to be formed through photolithography and etching processes. The second metal layer 520 is the upper electrode of the MIM capacitor device, and the first metal layer 320 is the lower electrode. Specifically, this involves etching portions of the fifth amorphous dielectric layer 600, portions of the metal material in the second removal space 510, portions of the third amorphous dielectric layer 400, portions of the metal material in the first removal space 310, and the metal material in the opening 120, to form a structure as described above. Figure 12 The structure is a stepped structure. The metal material between the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400 serves as the first metal layer 320, and the metal material between the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 serves as the second metal layer 520. At least a portion of the third amorphous dielectric layer 400 and the first metal layer 320 form a first step, and the fifth amorphous dielectric layer 600, the second metal layer 520, and / or the third amorphous dielectric layer 400 form a second step, with at least a portion of the first step exposed.

[0074] Please see Figure 13 , Figure 13 This is a schematic diagram of a MIM capacitor structure provided in an embodiment of this application. Figure 13 As shown, in Figure 12 Based on this, a sixth dielectric layer 700 is formed on the stepped structure, that is, a sixth dielectric layer 700 is formed on the upper electrode plate and the lower electrode plate, wherein the surface of the sixth dielectric layer 700 away from the stepped structure is a planarized surface.

[0075] Since the wafer surface is uneven after the MIM capacitor device is fabricated, the surface is planarized using CMP process after the sixth dielectric layer 700 is deposited. This planarization process makes the surface of the sixth dielectric layer 700 away from the stepped structure a planarized surface. Therefore, in order to meet the requirements of CMP process, the thickness of the sixth dielectric layer 700 is between 3000-5000nm.

[0076] After forming the sixth dielectric layer 700, contact plugs for the upper and lower metal plates are formed. Specifically, a first through-hole and a second through-hole (not shown in the figure) are formed on the upper and lower metal plates using photolithography and etching processes. Conductive material is filled into the first and second through-holes to form a first conductive plug 820 and a second conductive plug 810. A first connection terminal 920 and a second connection terminal 910 are formed on the surface of the sixth dielectric layer 700 away from the stepped structure. The first connection terminal 920 is connected to the first metal layer 320 through the first conductive plug 820, and the second connection terminal 910 is connected to the second metal layer 520 through the second conductive plug 810. The first metal layer 320, the third amorphous dielectric layer 400, and the second metal layer 520 constitute a MIM capacitor.

[0077] In one embodiment, the diameter of the first and second vias can be 45-150 nm, and their height is determined by the thickness of each amorphous dielectric layer, and can be set to between 2000-3000 nm.

[0078] Please see Figure 14 , Figure 14 This is a top view schematic diagram of a MIM capacitor device provided in an embodiment of this application. Figure 14 As shown, the MIM capacitor includes an inner region 10 and an outer region 11. The inner region 10 includes a second metal layer 520, a first metal layer 320, and a third amorphous dielectric layer 400 (not shown in the figure) between the second metal layer 520 and the first metal layer 320. The capacitor structure is formed by using the second metal layer 520 as the upper electrode and the first metal layer 320 as the lower electrode. The second conductive plug 810 in the second through hole on the second metal layer 520 is connected to the second connection terminal 910, and the first conductive plug 820 in the first through hole on the first metal layer 320 is connected to the first connection terminal 920, so that the MIM capacitor can be connected to an external circuit.

[0079] Additionally, please refer to... Figure 14 There can be multiple first through holes formed on the first step, that is, there can be multiple first through holes formed on the first metal layer 320, and there can be multiple corresponding first conductive plugs 820; there can be multiple second through holes formed on the second step, that is, there can be multiple second through holes formed on the second metal layer 520, and there can be multiple corresponding second conductive plugs 810.

[0080] The above technical solution, in the manufacturing method of a MIM capacitor, provides a semiconductor substrate 100, and deposits a first amorphous dielectric layer 200, a second amorphous dielectric layer 300, a third amorphous dielectric layer 400, a fourth amorphous dielectric layer 500, and a fifth amorphous dielectric layer 600 on the semiconductor substrate 100; removes the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 in a predetermined area of ​​the MIM capacitor to form a first removal space 310 and a second removal space 510, wherein, along the height direction of the semiconductor substrate, the upper and lower surfaces of the first removal space 310 are respectively distributed with the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400, and the second removal space 510 is ... The upper and lower surfaces of the space 510 are respectively provided with a third amorphous dielectric layer 400 and a fifth amorphous dielectric layer 600; the upper surface of the first amorphous dielectric layer 200 and the lower surface of the third amorphous dielectric layer 400 are exposed through the first removal space 310, and are respectively amorphous surfaces; the upper surface of the third amorphous dielectric layer 400 and the lower surface of the fifth amorphous dielectric layer 600 are exposed through the second removal space 510, and are respectively amorphous surfaces; a first metal layer 320 is formed in the first removal space 310, and a second metal layer 520 is formed in the second removal space 510, wherein the first metal layer 320, the third amorphous dielectric layer 400 and the second metal layer 520 constitute a MIM capacitor device. In other words, this application first deposits five amorphous dielectric layers, then selectively etches two of the amorphous dielectric layers, and deposits a metal layer in the removal space formed by the etching. Compared with the manufacturing process of directly depositing a metal layer on the dielectric layer, when the semiconductor device is a MIM capacitor, the manufacturing method of this application can reduce the surface roughness of the metal plate and the amorphous dielectric layer, thereby improving the TDDB characteristics of the capacitor and thus improving the performance of the semiconductor device.

[0081] This application provides a semiconductor device comprising: a semiconductor substrate, multiple amorphous dielectric layers formed on the semiconductor substrate, and at least one metal layer formed between two adjacent corresponding amorphous dielectric layers; wherein the surfaces of the two adjacent corresponding amorphous dielectric layers facing the metal layer are amorphous surfaces. Figure 6 As shown, the semiconductor device includes a semiconductor substrate 100 and a first amorphous dielectric layer 200, a first metal layer 320, and a third amorphous dielectric layer 400 sequentially formed on the semiconductor substrate 100. Because the surface of the amorphous dielectric layer facing the metal layer is an amorphous surface, the amorphous surface can make the surface of the metal layer smooth, reducing the surface roughness of the metal layer and the amorphous dielectric layer, thereby improving the performance of the semiconductor device.

[0082] In one embodiment, the multilayer amorphous dielectric layer includes a first amorphous dielectric layer, a third amorphous dielectric layer, and a fifth amorphous dielectric layer formed sequentially; at least one metal layer includes a first metal layer and a second metal layer. The first metal layer is located between the first and third amorphous dielectric layers, and the surfaces of the first and third amorphous dielectric layers facing the first metal layer are amorphous surfaces; the second metal layer is located between the third and fifth amorphous dielectric layers, and the surfaces of the third and fifth amorphous dielectric layers facing the second metal layer are amorphous surfaces.

[0083] like Figure 13 As shown, the semiconductor device is a MIM capacitor. The MIM capacitor includes a semiconductor substrate 100 and a first amorphous dielectric layer 200, a first metal layer 320, a third amorphous dielectric layer 400, a second metal layer 520, a fifth amorphous dielectric layer 600, and a sixth amorphous dielectric layer 700 sequentially formed on the semiconductor substrate 100. At least a portion of the third amorphous dielectric layer 400 and the first metal layer 320 form a first step. The fifth amorphous dielectric layer 600, the second metal layer 520, and / or the third amorphous dielectric layer 400 form a second step. The second step exposes at least a portion of the first step, forming a stepped structure. The sixth dielectric layer 700 is formed on the stepped structure. A sixth dielectric layer 700 is formed on the upper and lower electrodes; a first metal layer 320 serves as the lower electrode of the MIM capacitor, and a second metal layer 520 serves as the upper electrode; a first through-hole and a second through-hole (not shown in the figure) are formed on the upper and lower metal electrodes; conductive material is filled into the first and second through-holes to form a first conductive plug 820 and a second conductive plug 810, and a first connection end 920 and a second connection end 910 are formed on the surface of the sixth dielectric layer 700 away from the stepped structure, wherein the first connection end 920 is connected to the first metal layer 320 through the first conductive plug 820, and the second connection end 910 is connected to the second metal layer 520 through the second conductive plug 810. The first metal layer 320, the third amorphous dielectric layer 400, and the second metal layer 520 constitute the MIM capacitor. Because the surface of the amorphous dielectric layer in this application is relatively flat, the surface of the metal layer formed in the amorphous dielectric layer is also relatively flat. When the semiconductor device is a MIM capacitor, the surface roughness of the metal plate and the amorphous dielectric layer is reduced to improve the TDDB characteristics of the capacitor and thus improve the performance of the MIM capacitor.

[0084] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, include: Provide semiconductor substrates; A first amorphous dielectric layer, a second amorphous dielectric layer, a third amorphous dielectric layer, a fourth amorphous dielectric layer, and a fifth amorphous dielectric layer are formed on the semiconductor substrate; The second amorphous dielectric layer and the fourth amorphous dielectric layer are removed in at least one predetermined region to form a first removal space and a second removal space. Along the height direction of the semiconductor substrate, the upper and lower surfaces of the first removal space are respectively distributed with the first amorphous dielectric layer and the third amorphous dielectric layer, and the upper and lower surfaces of the second removal space are respectively distributed with the third amorphous dielectric layer and the fifth amorphous dielectric layer. The upper surface of the first amorphous dielectric layer and the lower surface of the third amorphous dielectric layer are exposed through the first removal space and are both amorphous surfaces. The upper surface of the third amorphous dielectric layer and the lower surface of the fifth amorphous dielectric layer are exposed through the second removal space and are both amorphous surfaces. A first metal layer is formed in the first removal space, and a second metal layer is formed in the second removal space. The first metal layer is in contact with the first amorphous dielectric layer and the third amorphous dielectric layer, respectively, and the second metal layer is in contact with the third amorphous dielectric layer and the fifth amorphous dielectric layer, respectively. The first metal layer, the third amorphous dielectric layer, and the second metal layer constitute a MIM capacitor. A sixth dielectric layer is formed on the first metal layer and the second metal layer, and a first conductive plug and a second conductive plug are formed in the sixth dielectric layer, respectively connecting the first metal layer and the second metal layer.

2. The manufacturing method according to claim 1, characterized in that, The materials of the second amorphous dielectric layer and the fourth amorphous dielectric layer are different from those of the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer; and / or For at least one etching process, the etching selectivity ratio of the second amorphous dielectric layer and the fourth amorphous dielectric layer is greater than the etching selectivity ratio of the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer.

3. The manufacturing method according to claim 1, characterized in that, The second amorphous dielectric layer and the fourth amorphous dielectric layer are made of the same material, while the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer are made of another material.

4. The manufacturing method according to claim 1, characterized in that, include: The step of removing the second amorphous dielectric layer and the fourth amorphous dielectric layer in the preset region to form a first removal space and a second removal space includes: An opening is formed in a predetermined region of the MIM capacitor device, wherein the opening exposes at least the side surfaces of the second amorphous dielectric layer, the third amorphous dielectric layer, the fourth amorphous dielectric layer and the fifth amorphous dielectric layer in the predetermined region of the MIM capacitor device; At least one etching process is selected to etch the second amorphous dielectric layer and the fourth amorphous dielectric layer, wherein the etching selectivity ratio of the at least one etching process for the second amorphous dielectric layer and the fourth amorphous dielectric layer is greater than the etching selectivity ratio of the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer, so that the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer are retained during the etching process, thereby forming the first removal space and the second removal space.

5. The manufacturing method according to claim 4, characterized in that, The step of forming a first metal layer in the first removal space and forming a second metal layer in the second removal space includes: Metallic materials are deposited on the first removal space, the second removal space, the opening, and the fifth amorphous dielectric layer by atomic layer deposition or physical vapor deposition. Remove excess metallic material from the fifth amorphous dielectric layer; The upper and lower plates of the MIM capacitor are formed.

6. The manufacturing method according to claim 1, characterized in that, The first amorphous dielectric layer serves as a barrier layer, and its thickness is between 40-100 nm. The third amorphous dielectric layer serves as the dielectric layer of the MIM capacitor. The fifth amorphous dielectric layer serves as a hard mask layer, with a thickness between 35-100 nm.

7. The manufacturing method according to claim 1, characterized in that, The semiconductor substrate includes a substrate and a device structure, isolation structure, dielectric layer or interconnect structure disposed in or on the substrate.

8. A semiconductor device, characterized in that, Obtained by the manufacturing method according to any one of claims 1-7, comprising: Semiconductor substrate; A multilayer amorphous dielectric layer is disposed on the semiconductor substrate; At least one metal layer is formed between two adjacent corresponding amorphous dielectric layers, the upper and lower surfaces of the metal layer being in contact with the two adjacent amorphous dielectric layers respectively, wherein the surfaces of the two adjacent corresponding amorphous dielectric layers facing the metal layer are amorphous surfaces; The multilayer amorphous dielectric layer includes a first amorphous dielectric layer, a third amorphous dielectric layer and a fifth amorphous dielectric layer arranged sequentially. The at least one metal layer includes a first metal layer and a second metal layer, wherein the first metal layer is located between the first amorphous dielectric layer and the third amorphous dielectric layer, and the surfaces of the first amorphous dielectric layer and the third amorphous dielectric layer facing the first metal layer are amorphous surfaces; the second metal layer is located between the third amorphous dielectric layer and the fifth amorphous dielectric layer, and the surfaces of the third amorphous dielectric layer and the fifth amorphous dielectric layer facing the second metal layer are amorphous surfaces; the first metal layer is in contact with the first amorphous dielectric layer and the third amorphous dielectric layer respectively, and the second metal layer is in contact with the third amorphous dielectric layer and the fifth amorphous dielectric layer respectively, wherein the first metal layer, the third amorphous dielectric layer, and the second metal layer constitute a MIM capacitor device; A sixth dielectric layer is formed on the first metal layer and the second metal layer; a first conductive plug and a second conductive plug are formed in the sixth dielectric layer and are respectively connected to the first metal layer and the second metal layer.

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