Method and apparatus for filling redundant metal in chip, chip and semiconductor device

Abstract

The present application relates to a method and device for filling redundant metal in a chip, a chip and a semiconductor device. The method comprises: dividing each metal layer of a chip comprising a plurality of metal layers into a plurality of regions; selecting, from the plurality of regions of each metal layer, a region requiring addition of redundant metal as a to-be-filled region based on a layout of each metal layer after routing; determining whether each to-be-filled region of an adjacent metal layer overlaps in a thickness direction of the metal layer; in response to no overlap, performing interdigital redundant metal filling on the to-be-filled region of each metal layer respectively; in response to an overlap, connecting the to-be-filled regions of adjacent layers by a via, and performing interdigital redundant metal filling on one of the plurality of to-be-filled regions having the overlap, and performing floating metal filling on the remaining to-be-filled regions of the plurality of to-be-filled regions having the overlap. The present application significantly improves the capacitance value and the utilization rate of redundant metal in a limited space.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method, apparatus, chip, and semiconductor device for filling redundant metal in a chip. Background Technology

[0002] In recent years, with the continuous advancement of process nodes and the shrinking of process dimensions in integrated circuit manufacturing, chip design and manufacturing processes have become increasingly complex, and process stability has deteriorated. For example, in the chip physical design process, after timing and functional convergence, the physical design enters the DFM (Design for Manufacturability) stage, which studies the relationship between the physical design of the product and the various parts of the manufacturing system, transforming the chip design to facilitate production. At this stage, the layout is uneven in terms of both metal density and linewidth, making it impossible to guarantee wafer surface flatness. This poses a significant challenge to CMP (Chemical Mechanical Polishing), a process where wafers typically have extremely uneven surfaces after a series of processes, which are planarized using grinding discs and abrasives. CMP is highly dependent on the pattern, and different pattern densities and gradients have a significant impact on the polishing results. At this point, redundant metals can be used to improve the uniformity of metal distribution in the layout without affecting the original circuit function, reducing dishing and erosion after CMP, thereby improving product yield and reliability. Redundancy fill is a layout pattern structure that does not affect the logic function of a chip. Its material can be polysilicon used in shallow trench isolation (STI) processes or copper used in copper chemical mechanical polishing processes; its shape can be a simple cube or a specially designed pattern; it can be grounded or floating.

[0003] Currently, most traditional redundant metal filling methods employ, for example... Figure 1A The floating metal filling method shown is relatively simple and direct. Generally, after selecting a redundant metal graphic shape, a buffer distance is set. Under the rule of the buffer distance, as much redundant metal of the shape as possible will be filled.

[0004] Furthermore, all electronic components on a chip can only operate stably when supplied with a sufficient and stable power supply. Their power comes from the power network, and the integrity of the power network includes voltage drop analysis and electromigration effect analysis. The voltage drop in the power network is caused by the resistance of the metal interconnects and vias within the chip's power network. When current flows from the power supply through interconnects and vias, a voltage drop occurs, causing the voltage of the electronic components to be lower than the power supply voltage. When too many interconnects and vias carry current, the voltage will be even lower. The lower the voltage, the weaker the performance of the electronic components, which will affect the chip's performance and lifespan. The electromigration effect is due to the high-density current in the metal interconnects. Large-scale atomic migration can form atomic flows, potentially causing metal breakage or adjacent metal interconnects to stick together. To reduce voltage drop and electromigration effects, designers often continuously increase the size of the power and ground networks, resulting in a large amount of signal routing resources being consumed, leading to a shortage of routing resources, congestion in signal routing, and consequently affecting the chip's design area and timing convergence. Therefore, increasing the stability of the power network to improve power supply capability is particularly important.

[0005] Currently, a common method to improve power supply stability is to add capacitors. Traditional methods use PIP capacitors or MIM capacitors to meet the chip's capacitance requirements. The main drawbacks are the need for additional photomask costs, complex manufacturing processes, and limited capacity additions. Previously, to address these issues, Chinese patent number CN 114220798 A disclosed an interdigitated redundant metal filling method. Please refer to... Figure 1B The interdigitated connection method shown connects redundant metal and power lines, forming a capacitor that replaces the capacitor structure that requires an additional photomask. This improves power network stability, reduces design costs for chip companies, and also increases yield. While the interdigitated redundant metal filling method increases the capacitance per unit area of ​​the power network, not all redundant metal can be connected to the power network, and it can also consume resources. Summary of the Invention

[0006] In view of this, in order to address the problem that when using interdigitated redundant metal filling, it may be difficult to find a suitable location to connect to the power ground, and in this case, the redundant metal can only be filled separately in a traditional way, the present invention provides a method, apparatus, chip and semiconductor device for filling redundant metal in a chip.

[0007] According to a first aspect of the present invention, a method for filling redundant metal in a chip is provided, the method comprising:

[0008] Each metal layer of a chip, which comprises multiple metal layers, is divided into multiple regions;

[0009] Based on the layout and routing of each metal layer, the regions that need to add redundant metal are selected from multiple regions of each metal layer as regions to be filled.

[0010] Determine whether each region to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer;

[0011] In response to the absence of overlap, interdigitated redundant metal filling is performed on the unfilled areas of each metal layer.

[0012] In response to the existence of overlap, the areas to be filled in adjacent layers are connected by through holes, and one of the areas to be filled with interdigitated redundant metal is filled, while the remaining areas to be filled with overlapping areas are filled with floating metal.

[0013] In some embodiments, each metal layer of a chip comprising multiple metal layers is divided into multiple regions, including;

[0014] Each metal layer is evenly divided into multiple panes of equal area.

[0015] In some embodiments, dividing each metal layer into multiple panes of equal area includes:

[0016] Each metal layer is divided into a first preset number of parts and a second preset number of parts along the length and width directions to form a window pane;

[0017] Wherein, the first preset number of portions and / or the second preset number of portions is greater than or equal to two.

[0018] In some embodiments, based on the layout after routing of each metal layer, regions requiring the addition of redundant metal are selected from multiple regions of each metal layer as areas to be filled, including:

[0019] Calculate the initial graphic density of each pane based on the layout after metal layer placement and routing;

[0020] To iterate through all panes, perform the following operations:

[0021] Calculate the difference between the initial graphic density of each adjacent pane of the target pane and the initial graphic density of the target pane;

[0022] Use the maximum value of the difference as the graphic gradient of the target pane;

[0023] If the graphic gradient of the target pane exceeds a preset graphic gradient, then the target pane is designated as the area to be filled.

[0024] In some embodiments, determining whether each region to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer includes:

[0025] If the metal layer is the bottom metal layer, then determine whether the corresponding window in the metal layer above the bottom metal layer for each target window is the target window.

[0026] In response to the metal layer being the top metal layer, determine whether the corresponding window in the next lower metal layer for each target window on the top metal layer is the target window.

[0027] In response to the metal layer being an intermediate metal layer, it is determined whether the corresponding panes of each target pane on the intermediate metal layer at the next lower and next upper metal layers are target panes.

[0028] In some embodiments, the method further includes:

[0029] If any target pane on the bottom metal layer has a corresponding pane on the next upper metal layer, then an overlap is confirmed.

[0030] If none of the target panes on the bottom metal layer have corresponding panes on the next upper metal layer, then it is confirmed that there is no overlap.

[0031] If any target pane on the top metal layer has a corresponding pane on the next lower metal layer, then an overlap is confirmed.

[0032] If none of the target panes on the top metal layer have corresponding panes on the next lower metal layer, then there is no overlap.

[0033] If any target pane on the intermediate metal layer has a corresponding pane on the next or previous metal layer that is also a target pane, then an overlap is confirmed.

[0034] If none of the target panes on the intermediate metal layer have corresponding panes on the next lower and next upper metal layers that are not target panes, then it is confirmed that there is no overlap.

[0035] In some embodiments, the preset graphic gradient is greater than or equal to 40% and less than 100%.

[0036] According to a second aspect of the present invention, a filling device for redundant metal in a chip is provided, the device comprising:

[0037] A partitioning module is configured to divide each metal layer of a chip, which includes multiple metal layers, into multiple regions.

[0038] The filtering module is configured to filter out areas that need to have redundant metal added as areas to be filled from multiple regions of each metal layer based on the layout after routing of each metal layer.

[0039] The judgment module is configured to determine whether each area to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer.

[0040] The first filling module is configured to perform interdigitated redundant metal filling on the unfilled area of ​​each metal layer in response to the absence of overlap.

[0041] The second filling module is configured to, in response to the existence of overlap, connect the areas to be filled in adjacent layers using through holes, perform interdigitated redundant metal filling on one of the multiple areas to be filled that overlap, and perform floating metal filling on the remaining areas to be filled that overlap.

[0042] According to a third aspect of the present invention, a chip is also provided, wherein redundant metal on the chip is filled according to the above-described method for filling redundant metal in a chip.

[0043] According to a fourth aspect of the present invention, a semiconductor device is also provided, the semiconductor device comprising the chip described above.

[0044] The aforementioned method for filling redundant metal in a chip is an improvement on the previous method, which uses capacitors made of redundant metal to replace the capacitor structure that requires additional photomasks. The redundant metal is formed by combining interdigitated arrangement of redundant metal connections with vias. That is, the parts that need to be filled with redundant metal in adjacent layers are connected by vias, which reduces the connection points between the redundant metal in adjacent layers and the power supply. The redundant metal can increase the capacitance and its position is more flexible and free. It significantly improves the capacitance value and the utilization rate of redundant metal in limited space.

[0045] In addition, the present invention also provides a filling device for redundant metal in a chip, a chip, and a semiconductor device, which can achieve the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0047] Figure 1A A schematic diagram of a traditional floating metal filling system;

[0048] Figure 1B A schematic diagram of existing interdigitated redundant metal filling;

[0049] Figure 2A flowchart illustrating a method for filling redundant metal in a chip according to an embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of an interdigitated redundant metal connection with added through holes according to an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of the initial graphic density and graphic gradient markings of each pane provided in an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of redundant metal markings in a pane of adjacent metal layers provided for another embodiment of the present invention;

[0053] Figure 6 A schematic diagram of adding through holes in adjacent metal layers according to an embodiment of the present invention;

[0054] Figure 7 This is a schematic diagram of a device for filling redundant metal in a chip, provided as another embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0056] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0058] In one embodiment, please refer to Figure 2 As shown, the present invention provides a method 100 for filling redundant metal in a chip. Specifically, the method includes the following steps:

[0059] Step 101: Divide each metal layer of the chip, which includes multiple metal layers, into multiple regions;

[0060] Step 102: Based on the layout after routing of each metal layer, select the areas where redundant metal needs to be added from multiple regions of each metal layer as the areas to be filled.

[0061] Step 103: Determine whether each area to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer;

[0062] Step 104: In response to the absence of overlap, perform interdigitated redundant metal filling on the unfilled areas of each metal layer.

[0063] Step 105: In response to the existence of overlap, the areas to be filled in adjacent layers are connected by through holes, and one of the areas to be filled with interdigitated redundant metal is filled, and the remaining areas to be filled with overlapping areas are filled with floating metal.

[0064] In this embodiment, the floating metal filling can be referred to Figure 1A The interdigitated redundant metal fill shown can be referenced. Figure 1B As shown. A via (or interconnect via) is used to connect different layers of metal interconnects on a chip. The function of a via is to connect these different metal layers. For structures with overlapping areas and redundant metal, refer to [reference needed]. Figure 3 As shown.

[0065] The aforementioned method for filling redundant metal in a chip is an improvement on the previous method, which uses capacitors made of redundant metal to replace the capacitor structure that requires additional photomasks. The redundant metal is formed by combining interdigitated arrangement of redundant metal connections with vias. That is, the parts that need to be filled with redundant metal in adjacent layers are connected by vias, which reduces the connection points between the redundant metal in adjacent layers and the power supply. The redundant metal can increase the capacitance and its position is more flexible and free. It significantly improves the capacitance value and the utilization rate of redundant metal in limited space.

[0066] In some embodiments, step 101 above divides each metal layer of a chip comprising multiple metal layers into multiple regions, including;

[0067] Each metal layer is evenly divided into multiple panes of equal area. In this embodiment, the panes can be regular shapes such as triangles, quadrilaterals, pentagons, etc. Of course, the panes can also be regular shapes, as long as each pane has the same area.

[0068] In some embodiments, dividing each metal layer into multiple panes of equal area includes:

[0069] Each metal layer is divided into a first preset number of parts and a second preset number of parts along the length and width directions to form a window pane;

[0070] Wherein, the first preset number of portions and / or the second preset number of portions is greater than or equal to two.

[0071] In some embodiments, step 102, which involves selecting regions from multiple regions of each metal layer that require the addition of redundant metal as regions to be filled based on the layout after routing of each metal layer, includes:

[0072] Calculate the initial graphic density of each pane based on the layout after metal layer placement and routing;

[0073] To iterate through all panes, perform the following operations:

[0074] Calculate the difference between the initial graphic density of each adjacent pane of the target pane and the initial graphic density of the target pane;

[0075] It should be noted that in this embodiment, adjacent panes refer to the four types of windows directly above, below, to the left, and to the right of the target pane. Diagonally opposite panes are not considered adjacent panes.

[0076] Use the maximum value of the difference as the graphic gradient of the target pane;

[0077] If the graphic gradient of the target pane exceeds a preset graphic gradient, then the target pane is designated as the area to be filled.

[0078] In some embodiments, step 103, which involves determining whether each region to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer, includes:

[0079] If the metal layer is the bottom metal layer, then determine whether the corresponding window in the metal layer above the bottom metal layer for each target window is the target window.

[0080] In response to the metal layer being the top metal layer, determine whether the corresponding window in the next lower metal layer for each target window on the top metal layer is the target window.

[0081] In response to the metal layer being an intermediate metal layer, it is determined whether the corresponding panes of each target pane on the intermediate metal layer at the next lower and next upper metal layers are target panes.

[0082] In some embodiments, the method further includes:

[0083] If any target pane on the bottom metal layer has a corresponding pane on the next upper metal layer, then an overlap is confirmed.

[0084] If none of the target panes on the bottom metal layer have corresponding panes on the next upper metal layer, then it is confirmed that there is no overlap.

[0085] If any target pane on the top metal layer has a corresponding pane on the next lower metal layer, then an overlap is confirmed.

[0086] If none of the target panes on the top metal layer have corresponding panes on the next lower metal layer, then there is no overlap.

[0087] If any target pane on the intermediate metal layer has a corresponding pane on the next or previous metal layer that is also a target pane, then an overlap is confirmed.

[0088] If none of the target panes on the intermediate metal layer have corresponding panes on the next lower and next upper metal layers that are not target panes, then it is confirmed that there is no overlap.

[0089] In some embodiments, the preset graphic gradient is greater than or equal to 40% and less than 100%.

[0090] In another embodiment, to facilitate understanding of the present invention, a chip containing two metal layers is used as an example for detailed description. This embodiment provides a method for filling redundant metal in a chip. The principle is to use vias between adjacent redundant metal layers. At locations where redundant metal needs to be added in both adjacent layers, only one layer needs to use an interdigitated redundant metal filling method to effectively solve the problem that interdigitated redundant metal filling may not find a suitable location to connect the power supply. The implementation process of this method is as follows:

[0091] Step 1: Check the layout and wiring according to the design rules, and mark the areas where redundant metal needs to be added. For easier understanding, we can take a 4x4 grid layout as an example.

[0092] Step two, please combine Figure 4 As shown, the entire map is divided into several panes, the initial graphic density of each pane is calculated, and the value is marked in the lower left corner of each pane.

[0093] Step 3, please combine again Figure 4 As shown, calculate the graphic density difference between each pane and its adjacent panes (top, bottom, left, right), and mark the maximum gradient with respect to adjacent panes at the top right corner of each pane; for example... Figure 4 The initial image density of the first pane in the first row and first column is 16%. The difference between the pane directly below it and the first pane to its right is 19%, and the difference between the pane directly to its right and the first pane to its left is 4%. Therefore, the maximum gradient is 19%. The calculation method for the other panes is the same as that of this pane, so it will not be described again.

[0094] Step four, please combine Figure 4 As shown, panes with a gradient difference exceeding 40% in the layout are marked in light gray;

[0095] Step 5: Calculate the maximum and minimum graphic density achievable for each pane. Based on the maximum, minimum, and maximum graphic gradient, determine whether to add redundant metal to that pane. If necessary, retain or add color markers; otherwise, remove color markers. In actual redundant metal filling, it is often impossible to achieve the target for all panes in one round. Therefore, it is necessary to repeat steps 4 and 5 multiple times, performing multiple cycles of density and gradient calculations to achieve the required graphic density and gradient.

[0096] Step six: After marking all metal layers, check the overlap of the marked panes on adjacent layers, and determine the gradient difference between the overlapping panes. Mark the panes with greater gradient differences as dark gray, such as... Figure 6 As shown;

[0097] Step 7: For marked panes in adjacent layers with no overlap, apply interdigitated redundant metal fill. For panes in overlapping areas of adjacent layers: apply interdigitated redundant metal fill to dark gray panes, and use traditional floating metal fill to light gray panes. Connection to the power ground is not a concern. Simultaneously, drill through holes in the redundant metal added to the dark gray panes to connect with the normal redundant metal in the light-colored panes of the adjacent layers. Figure 6 The location indicated by the middle arrow is where a through hole needs to be made. The adjacent layers here can also be two or more layers. For example, for three metal layers, assuming that the upper and lower three layers of a certain pane are all dark gray areas, a through hole can be made through the three layers to connect the panes.

[0098] The method for filling redundant metal in the chip in this embodiment determines the location of vias by using a gradient judgment method with adjacent layers. As long as the redundant metal in one layer is connected to the power line, the redundant metal in the other metal layers connected by vias can increase the capacitance even if they are not connected to the power line. This is more conducive to the flexibility of redundant metal filling and the increase of capacitance in the system-on-a-chip (SoC). It also increases the flexibility of the location of redundant metal, which is more conducive to the filling of redundant metal and the increase of power network stability.

[0099] In some embodiments, please refer to Figure 7 As shown, the present invention also provides a filling device 200 for redundant metal in a chip, the device comprising:

[0100] The partitioning module 201 is configured to divide each metal layer of a chip comprising multiple metal layers into multiple regions.

[0101] The filtering module 202 is configured to filter out areas that need to have redundant metal added as areas to be filled from multiple areas of each metal layer based on the layout after routing of each metal layer.

[0102] The judgment module 203 is configured to determine whether each area to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer;

[0103] The first filling module 204 is configured to perform interdigitated redundant metal filling on the unfilled area of ​​each metal layer in response to the absence of overlap.

[0104] The second filling module 205 is configured to, in response to the existence of overlap, connect the areas to be filled in adjacent layers using through holes, perform interdigitated redundant metal filling on one of the multiple areas to be filled that overlap, and perform floating metal filling on the remaining areas to be filled that overlap.

[0105] The aforementioned filling device for redundant metal in a chip is an improvement upon the existing method of using capacitors formed by redundant metal to replace the capacitor structure that requires additional photomasks. The redundant metal is formed by combining interdigitated arrangement of redundant metal connections with vias. That is, the redundant metal is connected by vias in the parts that need to be filled in adjacent layers, reducing the connection points between the redundant metal in adjacent layers and the power supply. The redundant metal can increase the capacitance and its position is more flexible and free. It significantly improves the capacitance value and the utilization rate of redundant metal in the limited space.

[0106] In some embodiments, the partitioning module 201 is further configured to;

[0107] Each metal layer is evenly divided into multiple panes of equal area.

[0108] In some embodiments, the partitioning module 201 is further configured to:

[0109] Each metal layer is divided into a first preset number of parts and a second preset number of parts along the length and width directions to form a window pane;

[0110] Wherein, the first preset number of portions and / or the second preset number of portions is greater than or equal to two.

[0111] In some embodiments, the filtering module 202 is further configured to:

[0112] Calculate the initial graphic density of each pane based on the layout after metal layer placement and routing;

[0113] To iterate through all panes, perform the following operations:

[0114] Calculate the difference between the initial graphic density of each adjacent pane of the target pane and the initial graphic density of the target pane;

[0115] Use the maximum value of the difference as the graphic gradient of the target pane;

[0116] If the graphic gradient of the target pane exceeds a preset graphic gradient, then the target pane is designated as the area to be filled.

[0117] In some embodiments, the determining module 203 is further configured to:

[0118] If the metal layer is the bottom metal layer, then determine whether the corresponding window in the metal layer above the bottom metal layer for each target window is the target window.

[0119] In response to the metal layer being the top metal layer, determine whether the corresponding window in the next lower metal layer for each target window on the top metal layer is the target window.

[0120] In response to the metal layer being an intermediate metal layer, it is determined whether the corresponding panes of each target pane on the intermediate metal layer at the next lower and next upper metal layers are target panes.

[0121] In some embodiments, the apparatus further includes a confirmation module, the confirmation module being configured to: confirm that there is overlap if any target pane on the bottom metal layer has a corresponding pane on the metal layer above it that is a target pane;

[0122] If none of the target panes on the bottom metal layer have corresponding panes on the next upper metal layer, then it is confirmed that there is no overlap.

[0123] If any target pane on the top metal layer has a corresponding pane on the next lower metal layer, then an overlap is confirmed.

[0124] If none of the target panes on the top metal layer have corresponding panes on the next lower metal layer, then there is no overlap.

[0125] If any target pane on the intermediate metal layer has a corresponding pane on the next or previous metal layer that is also a target pane, then an overlap is confirmed.

[0126] If none of the target panes on the intermediate metal layer have corresponding panes on the next lower and next upper metal layers that are not target panes, then it is confirmed that there is no overlap.

[0127] In some embodiments, the preset graphic gradient is greater than or equal to 40% and less than 100%.

[0128] It should be noted that the specific limitations regarding the filling device for redundant metal in the chip can be found in the limitations on the filling method for redundant metal in the chip mentioned above, and will not be repeated here. Each module in the aforementioned filling device for redundant metal in the chip can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0129] According to another aspect of the present invention, this embodiment provides a chip, wherein redundant metal on the chip is filled according to the redundant metal filling method of the chip described in the above embodiments.

[0130] According to another aspect of the present invention, this embodiment provides a semiconductor device, the semiconductor device comprising the chip described in the above embodiments.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for filling redundant metal in a chip, characterized in that, The method includes: Each metal layer of a chip, which comprises multiple metal layers, is divided into multiple regions; Based on the layout and routing of each metal layer, the regions that need to add redundant metal are selected from multiple regions of each metal layer as regions to be filled. Determine whether each region to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer; In response to the absence of overlap, interdigitated redundant metal filling is performed on the unfilled areas of each metal layer. In response to the existence of overlap, the areas to be filled in adjacent layers are connected by through holes, and one of the areas to be filled with interdigitated redundant metal is filled, while the remaining areas to be filled with overlapping areas are filled with floating metal.

2. The method for filling redundant metal in a chip according to claim 1, characterized in that, Each metal layer of a chip comprising multiple metal layers is divided into multiple regions, including; Each metal layer is evenly divided into multiple panes of equal area.

3. The method for filling redundant metal in a chip according to claim 2, characterized in that, Each metal layer is evenly divided into multiple panes of equal area, including: Each metal layer is divided into a first preset number of parts and a second preset number of parts along the length and width directions to form a window pane; Wherein, the first preset number of portions and / or the second preset number of portions is greater than or equal to two.

4. The method for filling redundant metal in a chip according to claim 3, characterized in that, Based on the layout and routing of each metal layer, the regions that need to have redundant metal added are selected from multiple regions of each metal layer as areas to be filled, including: Calculate the initial graphic density of each pane based on the layout after metal layer placement and routing; To iterate through all panes, perform the following operations: Calculate the difference between the initial graphic density of each adjacent pane of the target pane and the initial graphic density of the target pane; Use the maximum value of the difference as the graphic gradient of the target pane; If the graphic gradient of the target pane exceeds a preset graphic gradient, then the target pane is designated as the area to be filled.

5. The method for filling redundant metal in a chip according to claim 4, characterized in that, Determining whether each region to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer includes: If the metal layer is the bottom metal layer, then determine whether the corresponding window in the metal layer above the bottom metal layer for each target window is the target window. In response to the metal layer being the top metal layer, determine whether the corresponding window in the next lower metal layer for each target window on the top metal layer is the target window. In response to the metal layer being an intermediate metal layer, it is determined whether the corresponding panes of each target pane on the intermediate metal layer at the next lower and next upper metal layers are target panes.

6. The method for filling redundant metal in a chip according to claim 5, characterized in that, The method further includes: If any target pane on the bottom metal layer has a corresponding pane on the next upper metal layer, then an overlap is confirmed. If none of the target panes on the bottom metal layer have corresponding panes on the next upper metal layer, then it is confirmed that there is no overlap. If any target pane on the top metal layer has a corresponding pane on the next lower metal layer, then an overlap is confirmed. If none of the target panes on the top metal layer have corresponding panes on the next lower metal layer, then there is no overlap. If any target pane on the intermediate metal layer has a corresponding pane on the next or previous metal layer that is also a target pane, then an overlap is confirmed. If none of the target panes on the intermediate metal layer have corresponding panes on the next lower and next upper metal layers that are not target panes, then it is confirmed that there is no overlap.

7. The method for filling redundant metal according to claim 4, characterized in that, The preset graphic gradient is greater than or equal to 40% and less than 100%.

8. A filling device for redundant metal in a chip, characterized in that, The device includes: A partitioning module is configured to divide each metal layer of a chip, which includes multiple metal layers, into multiple regions. The filtering module is configured to filter out areas that need to have redundant metal added as areas to be filled from multiple regions of each metal layer based on the layout after routing of each metal layer. The judgment module is configured to determine whether each area to be filled in adjacent metal layers overlaps along the thickness direction of the metal layer. The first filling module is configured to perform interdigitated redundant metal filling on the unfilled area of ​​each metal layer in response to the absence of overlap. The second filling module is configured to, in response to the existence of overlap, connect the areas to be filled in adjacent layers using through holes, perform interdigitated redundant metal filling on one of the multiple areas to be filled that overlap, and perform floating metal filling on the remaining areas to be filled that overlap.

9. A chip, characterized in that, The redundant metal on the chip is filled according to the method for filling redundant metal in a chip as described in any one of claims 1 to 7.

10. A semiconductor device, characterized in that, The semiconductor device includes the chip as described in claim 9.

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