Semiconductor structure and methods for forming semiconductor structures

Abstract

A semiconductor structure and a method for forming the same are disclosed. The structure includes: a substrate and a fin structure on the substrate; a gate structure, source / drain doped regions within the fin structure, and a first dielectric layer located on the substrate, the gate structure spanning the fin structure and located within the first dielectric layer; a second dielectric layer located on the first dielectric layer, the second dielectric layer having a plurality of first openings; a first conductive structure located within the first openings, the first conductive structure including a barrier layer located on the sidewalls and bottom of the first openings and a conductive layer located on the surface of the barrier layer, the top surface of the barrier layer being lower than the top surface of the conductive layer; a third dielectric layer located on the second dielectric layer and the first conductive structure; a second opening located within the third dielectric layer exposing the top surface of the first conductive structure; a third opening located at the bottom of the second opening exposing the top surface of the barrier layer and part of the sidewall surface of the conductive layer; and an electrical connection layer located within the third opening and the second opening. The semiconductor structure exhibits improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] Metal interconnect structures are indispensable in semiconductor devices, used to interconnect active regions, transistors, or different layers of metal lines to achieve signal transmission and control. Therefore, the formation of metal interconnect structures has a significant impact on the performance and manufacturing cost of semiconductor devices during semiconductor manufacturing. To increase device density, the size of semiconductor devices in integrated circuits has been continuously reduced. To achieve electrical connections between these semiconductor devices, multi-layer interconnect structures are typically required.

[0003] Generally, in the back-end interconnect process of semiconductor device manufacturing, the first conductive layer (M1) needs to form an electrical connection with the underlying active device structure (including source / drain regions and gate structure regions). Therefore, before forming the first conductive layer, it is usually necessary to pre-form the local interconnect structure of the semiconductor device. The local interconnect structure includes: a zeroth conductive layer (MO) electrically connected to the underlying source / drain regions, and a zeroth gate conductive layer (MOG) electrically connected to the gate structure.

[0004] However, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs to be further improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate having a fin structure; a gate structure located on the substrate and source / drain doped regions located within the fin structures on both sides of the gate structure, the gate structure spanning the fin structures; a first dielectric layer located on the substrate, the gate structure located within the first dielectric layer; a second dielectric layer located on the first dielectric layer, the second dielectric layer and the first dielectric layer having a plurality of first openings, the first openings exposing a portion of the substrate surface; a first conductive structure located within the first openings, the first conductive structure comprising a barrier layer located on the sidewall surface and bottom surface of the first opening and a conductive layer located on the surface of the barrier layer, the top surface of the barrier layer being lower than the top surface of the conductive layer; a third dielectric layer located on the second dielectric layer and the first conductive structure; a second opening located within the third dielectric layer, the second opening exposing the top surface of the first conductive structure; a third opening located at the bottom of the second opening, the third opening exposing the top surface of the barrier layer and a portion of the sidewall surface of the conductive layer; and an electrical connection layer located within the third opening and the second opening, the electrical connection layer being located on the first conductive structure.

[0007] Optionally, the first conductive structure extends along a first direction parallel to the substrate surface, and the conductive layer has a first dimension along a second direction parallel to the substrate surface, wherein the first direction is perpendicular to the second direction.

[0008] Optionally, the top surface of the barrier layer to the top surface of the conductive layer has a second dimension in a direction perpendicular to the substrate surface, wherein the ratio of the second dimension to the first dimension ranges from 1:4 to 3:2.

[0009] Optionally, the aspect ratio of the second opening is in the range of 1 to 8; the aspect ratio of the third opening is in the range of 1 to 6.

[0010] Optionally, the material of the barrier layer includes a metal nitride, such as titanium nitride or tantalum nitride; the material of the conductive layer includes a metal, such as cobalt.

[0011] Optionally, the material of the electrical connection layer includes a metal, including tungsten.

[0012] Optionally, it may also include: a second conductive structure located within the second dielectric layer, the second conductive structure being located on the gate structure.

[0013] Optionally, it may also include: a first stop layer located between the first dielectric layer and the second dielectric layer; and a second stop layer located between the second dielectric layer and the third dielectric layer.

[0014] Optionally, it further includes: an isolation layer located on the substrate, the isolation layer being located on the sidewall of the fin structure and the top surface of the isolation layer being lower than the top surface of the fin structure; the gate structure being located on the isolation layer.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a fin structure; forming a gate structure, source / drain doped regions located within the fin structures on both sides of the gate structure, and a first dielectric layer on the substrate, the gate structure spanning the fin structure and located within the first dielectric layer; forming a second dielectric layer on the first dielectric layer, the second dielectric layer and the first dielectric layer having a plurality of first openings, the first openings exposing a portion of the surface of the source / drain doped regions; forming a first conductive structure within the first openings, the first conductive structure including an initial barrier layer located on the sidewall surface and bottom surface of the first opening and a conductive layer located on the surface of the initial barrier layer; forming a third dielectric layer on the second dielectric layer and the first conductive structure, the third dielectric layer having a second opening, the second opening exposing the top surface of the first conductive structure; removing a portion of the initial barrier layer exposed by the second opening to form a barrier layer, and forming a third opening connected to the second opening within the third dielectric layer, the top surface of the barrier layer being lower than the top surface of the conductive layer; and forming an initial electrical connection layer within the third opening and the second opening using a selective deposition process.

[0016] Optionally, the first conductive structure extends along a first direction parallel to the substrate surface, and the conductive layer has a first dimension along a second direction parallel to the substrate surface, wherein the first direction is perpendicular to the second direction.

[0017] Optionally, the top surface of the barrier layer to the top surface of the conductive layer has a second dimension in a direction perpendicular to the substrate surface, wherein the ratio of the second dimension to the first dimension ranges from 1:4 to 3:2.

[0018] Optionally, the aspect ratio of the second opening is in the range of 1 to 8; the aspect ratio of the third opening is in the range of 1 to 6.

[0019] Optionally, the material of the barrier layer includes a metal nitride, such as titanium nitride or tantalum nitride; the material of the conductive layer includes a metal, such as cobalt.

[0020] Optionally, the material of the initial electrical connection layer includes a metal, including tungsten.

[0021] Optionally, the process parameters for the selective deposition process that forms the initial electrical connection layer include: a temperature of 300°C to 400°C, and a reaction gas of a mixture of hydrogen and tungsten hexafluoride.

[0022] Optionally, after forming the initial electrical connection layer, the method further includes: forming a buffer layer on the third dielectric layer and the initial electrical connection layer; forming a pad layer on the buffer layer; and planarizing the pad layer, the buffer layer, and the initial electrical connection layer until the surface of the third dielectric layer is exposed to form the electrical connection layer.

[0023] Optionally, the padding layer and the initial electrical connection layer are made of the same material.

[0024] Optionally, the process for forming the liner layer includes chemical vapor deposition.

[0025] Optionally, the material of the buffer layer includes a metal nitride, such as titanium nitride or tantalum nitride.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] The technical solution of this invention removes a portion of the initial barrier layer exposed by the second opening to form a barrier layer, such that the top surface of the barrier layer is lower than the top surface of the conductive layer. This means the barrier layer exposes a portion of the sidewall surface of the conductive layer, increasing the surface area of ​​the exposed conductive layer. Consequently, when the initial electrical connection layer is subsequently formed within the third and second openings using a selective deposition process, the growth area of ​​the initial electrical connection layer on the conductive layer surface is increased. This increases the growth rate of the selective deposition process on the smaller conductive layer surface, improving the growth uniformity of the selective deposition process. This, in turn, helps to increase the uniformity of the initial electrical connection layer filling the second opening, thus improving the quality of the subsequently formed electrical connection layer.

[0028] Furthermore, along a direction perpendicular to the substrate surface, the top surface of the barrier layer to the top surface of the conductive layer has a second dimension, the ratio of the second dimension to the first dimension ranging from 1:4 to 3:2. This ensures that the area of ​​the conductive layer sidewalls exposed by the barrier layer is within a suitable range, maximizing the growth rate of the selective deposition process forming the initial electrical connection layer on the top and sidewall surfaces of the conductive layer. Attached Figure Description

[0029] Figure 1 and Figure 2 This is a schematic cross-sectional view of the semiconductor structure formation process in one embodiment;

[0030] Figures 3 to 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, the manufacturing process of semiconductor structures with local interconnect structures in the prior art is complex, and the performance of the resulting semiconductor structures needs further improvement. The following analysis and explanation will be provided with reference to specific embodiments.

[0032] Figure 1 and Figure 2 This is a cross-sectional schematic diagram of the semiconductor structure formation process in a disclosed embodiment.

[0033] Please refer to Figure 1 A substrate 100 is provided; a first dielectric layer 101 and a first conductive structure 102 and a second conductive structure 103 located within the first dielectric layer 101 are formed on the substrate 100. The first conductive structure 102 includes a barrier layer (not shown) and a conductive layer (not shown) located on the barrier layer. The second conductive structure 103 includes a barrier layer (not shown) and a conductive layer (not shown) located on the barrier layer. A stop layer (not shown) is formed on the first dielectric layer 101, the first conductive structure 102, and the second conductive structure 103. A second dielectric layer 104 is formed on the stop layer. A first opening (not shown) and a second opening (not shown) are formed within the second dielectric layer 104 and the stop layer. The first opening exposes the top surface of the first conductive structure 102, and the second opening exposes the top surface of the second conductive structure 103. A first initial electrical connection layer 105 is formed within the first opening, and a second initial electrical connection layer 106 is formed within the second opening.

[0034] Please refer to Figure 2 A fill layer (not shown) is formed on the first initial electrical connection layer 105 and the second initial electrical connection layer 106; the fill layer and the first initial electrical connection layer 105 are planarized to form a first electrical connection layer 109 and a second electrical connection layer 110.

[0035] During the formation of the semiconductor structure, the size of the conductive structure decreases as the device structure size shrinks. However, the process for forming smaller conductive structures is more complex, resulting in poor uniformity of the formed conductive structure size. Consequently, the first conductive structure 102 is larger than the second conductive structure 103. The process of forming the first initial electrical connection layer 105 within the first opening is a selective deposition process, and the process of forming the second initial electrical connection layer 106 within the second opening is also a selective deposition process, in order to obtain lower resistance. The surface of the conductive layer is the growth surface of the selective deposition process. Because the conductive structures vary in size, the selective deposition process results in a faster growth rate for the first initial conductive layer 105 on the surface of the larger first conductive structure 102, which can fill the opening. Conversely, the growth rate for the second initial electrical connection layer 106 on the surface of the smaller second conductive structure 103 is slower, and the formed second initial electrical connection layer 106 cannot fill the opening. Figure 1 As shown in the image.

[0036] When a filling layer is subsequently formed on the first initial electrical connection layer 105 and the second initial electrical connection layer 106, the filling layer also fills the opening in the second initial electrical connection layer 106. However, since the filling layer is formed by chemical vapor deposition, the opening has a large depth-to-width ratio. As a result, the chemical vapor deposition process causes voids in the filling layer material formed on the second initial electrical connection layer 106, which affects the performance of the subsequently formed second electrical connection layer 110. This results in a higher resistance in the second electrical connection layer 110, which in turn affects the performance of the semiconductor structure.

[0037] To address the aforementioned problems, the present invention provides a semiconductor structure and a method for forming the semiconductor structure. By removing a portion of the initial barrier layer exposed by the second opening, a barrier layer is formed, such that the top surface of the barrier layer is lower than the top surface of the conductive layer. This means the barrier layer exposes a portion of the sidewall surface of the conductive layer, increasing the surface area of ​​the exposed conductive layer. Consequently, when the initial electrical connection layer is subsequently formed within the third and second openings using a selective deposition process, the growth area of ​​the initial electrical connection layer on the conductive layer surface increases. This increases the growth rate of the selective deposition process on the smaller conductive layer surface, improving the growth uniformity of the selective deposition process. This, in turn, facilitates the uniformity of the initial electrical connection layer filling the second opening, thereby improving the quality of the subsequently formed electrical connection layer.

[0038] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the terms "upper," "lower," and "surface" in this specification are used to describe relative spatial positions and are not limited to whether there is direct contact.

[0039] Figures 3 to 9 This is a cross-sectional schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0040] Please refer to Figure 3 Substrate 200 is provided.

[0041] In this embodiment, the substrate 200 is made of silicon.

[0042] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0043] In this embodiment, the substrate 200 further includes a fin structure (not shown) and an isolation layer (not shown), the isolation layer being located on the sidewall of the fin structure and the top surface of the isolation layer being lower than the top surface of the fin structure.

[0044] In other embodiments, the substrate is a planar substrate.

[0045] Please continue to refer to this. Figure 3 A first dielectric layer (not shown) and a device structure located within the first dielectric layer are formed on the substrate 200; a first stop layer (not shown) is formed on the first dielectric layer.

[0046] In this embodiment, the device structure includes a gate structure (not shown) that spans the fin structure; it also includes source / drain doped regions (not shown) formed within the fin structures on both sides of the gate structure.

[0047] In other embodiments, the device structure includes a diode, transistor, capacitor, inductor, or conductive structure.

[0048] Please continue to refer to this. Figure 3 A second dielectric layer 201 is formed on the first stop layer, and a second stop layer (not shown) is formed on the second dielectric layer. The second dielectric layer 201 and the first dielectric layer have a plurality of first openings 202, and the first openings 202 expose a portion of the surface of the source and drain doped regions.

[0049] The materials of the first dielectric layer and the second dielectric layer 201 include dielectric materials, which include one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0050] In this embodiment, the materials of the first dielectric layer and the second dielectric layer 201 include silicon oxide.

[0051] Please refer to Figure 4 A first conductive structure is formed within the first opening 202. The first conductive structure includes an initial barrier layer 203 located on the sidewall surface and bottom surface of the first opening 202, and a conductive layer 204 located on the surface of the initial barrier layer 203.

[0052] The first conductive structure extends along a first direction parallel to the surface of the substrate 200, and the conductive layer 204 has a first dimension d1 along a second direction Y parallel to the surface of the substrate 200, wherein the first direction is perpendicular to the second direction Y.

[0053] The method for forming the first conductive structure includes: forming a barrier material layer (not shown) on the sidewall surface and bottom surface of the first opening 202 and on the second dielectric layer 201; forming a conductive material layer (not shown) on the barrier material layer; planarizing the conductive material layer, the barrier material layer and the second stop layer until the surface of the second dielectric layer 201 is exposed, thereby forming the initial barrier layer 203 and the conductive layer 204 located on the surface of the initial barrier layer 203.

[0054] The initial barrier layer 203 is made of a metal nitride, and the conductive layer 204 is made of a metal or a metal nitride, wherein the metal nitride includes titanium nitride or tantalum nitride, and the metal includes one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum.

[0055] In this embodiment, the initial barrier layer 203 is made of titanium nitride, and the conductive layer 204 is made of cobalt.

[0056] In this embodiment, the method further includes forming a second conductive structure (not shown) within the second dielectric layer 201, the second conductive structure being located on the gate structure.

[0057] Please refer to Figure 5 A third dielectric layer 205 is formed on the second dielectric layer 201 and the first conductive structure, the third dielectric layer 205 having a second opening 206 that exposes the top surface of the first conductive structure.

[0058] The material of the third dielectric layer 205 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0059] In this embodiment, the material of the third dielectric layer 205 includes silicon oxide.

[0060] The method for forming the third dielectric layer 205 and the second opening 206 includes: forming an initial third dielectric layer (not shown) on a second stop layer and a first conductive structure; forming a patterned layer (not shown) on the initial third dielectric layer, the patterned layer exposing a portion of the surface of the initial third dielectric layer; etching the initial third dielectric layer using the patterned layer as a mask until the surface of the first conductive structure is exposed, thereby forming the third dielectric layer 205 and the second opening 206 located within the third dielectric layer 205.

[0061] The aspect ratio of the second opening 206 is in the range of 1 to 8. The aspect ratio range of the second opening 206 facilitates the subsequent formation of an electrical connection layer within the second opening 206.

[0062] Please refer to Figure 6 The portion of the initial barrier layer 203 exposed by the second opening 206 is removed to form a barrier layer 207, and a third opening 208 communicating with the second opening 206 is formed in the third dielectric layer 205. The top surface of the barrier layer 207 is lower than the top surface of the conductive layer 204.

[0063] In this embodiment, the process of removing the portion of the initial barrier layer 203 exposed by the second opening 206 includes a dry etching process. The dry etching process can obtain a third opening 208 with good sidewall morphology, which is beneficial to the subsequent growth of the initial electrical connection layer in the third opening 208.

[0064] In this embodiment, the dry etching process that removes part of the initial barrier layer 203 also removes part of the third dielectric layer 205.

[0065] The top surface of the barrier layer 207 is lower than the top surface of the conductive layer 204, meaning that the barrier layer 207 exposes part of the sidewall surface of the conductive layer 204, thus increasing the exposed surface area of ​​the conductive layer 204. Consequently, when the initial electrical connection layer is subsequently formed within the third opening 208 and the second opening 206 using a selective deposition process, the growth area of ​​the initial electrical connection layer on the surface of the conductive layer 204 is increased. This increases the growth rate of the selective deposition process on the smaller-sized conductive layer 204 surface, improving the growth uniformity of the selective deposition process. This, in turn, helps to increase the uniformity of the formed initial electrical connection layer filling the second opening 206, thereby improving the quality of the subsequently formed electrical connection layer.

[0066] Along a direction perpendicular to the surface of the substrate 200, the top surface of the barrier layer 207 to the top surface of the conductive layer 204 has a second dimension d2. In this embodiment, the ratio of the second dimension d2 to the first dimension d1 ranges from 1:4 to 3:2.

[0067] If the ratio of the second dimension d2 to the first dimension d1 is too small, i.e., the second dimension d2 is too small, the area of ​​the exposed conductive layer 204 sidewall of the barrier layer 207 will also be small, and the effect on increasing the growth rate of the initial electrical connection layer formed on the top surface and sidewall surface of the conductive layer 204 by the subsequent selective deposition process will not be significant. If the ratio of the second dimension d2 to the first dimension d1 is too large, i.e., the second dimension d2 is too large, the exposed conductive layer 204 area will also be too large. When the initial electrical connection layer is formed on the top surface and sidewall surface of the conductive layer 204 by the subsequent selective deposition process, the excessively large area of ​​the conductive layer 204 cannot infinitely increase the growth rate on the top surface and sidewall surface of the conductive layer 204, thus causing process waste.

[0068] In this embodiment, the aspect ratio of the third opening 208 is in the range of 1 to 6. This ensures that the area of ​​the exposed sidewall of the conductive layer 204 by the barrier layer 207 is within a suitable range, thereby maximizing the growth rate of the selective deposition process forming the initial electrical connection layer on the top and sidewall surfaces of the conductive layer 204.

[0069] Please refer to Figure 7 An initial electrical connection layer 209 is formed in the third opening 208 and the second opening 206 using a selective deposition process.

[0070] The selective deposition process can form a dense initial electrical connection layer 209 within the third opening 208 and the second opening 206, which has a large aspect ratio, resulting in a lower resistance and better conductivity of the subsequently formed electrical connection layer.

[0071] The material of the initial electrical connection layer 209 includes metal, including tungsten.

[0072] The parameters of the selective deposition process for forming the initial electrical connection layer 209 include: a temperature of 300 degrees Celsius to 400 degrees Celsius and a reaction gas mixture of hydrogen and tungsten hexafluoride.

[0073] Because the top surface of the barrier layer 207 is lower than the top surface of the conductive layer 204, meaning the barrier layer 207 exposes part of the sidewall surface of the conductive layer 204, the exposed surface area of ​​the conductive layer 204 is increased. Therefore, when the initial electrical connection layer 209 is formed within the third opening 208 and the second opening 206 using a selective deposition process, the growth area of ​​the initial electrical connection layer 209 on the surface of the conductive layer 204 is increased. This increases the growth rate of the selective deposition process on the smaller-sized conductive layer 204 surface, improving the growth uniformity of the selective deposition process. This is beneficial for increasing the uniformity of the initial electrical connection layer 209 filling the second opening 206, and improving the quality of the subsequently formed electrical connection layer.

[0074] Please refer to Figure 8 A buffer layer 210 is formed on the third dielectric layer 205 and the initial electrical connection layer 209; a padding layer 211 is formed on the buffer layer 210.

[0075] The padding layer 211 and the initial electrical connection layer 209 are made of the same material.

[0076] The materials of the padding layer 211 and the initial electrical connection layer 209 include metals, including tungsten.

[0077] The process for forming the liner layer 211 includes a chemical vapor deposition process.

[0078] The material of the buffer layer 210 includes one or both of a metal and a metal compound; the metal includes titanium or tantalum; the metal compound includes titanium nitride or tantalum nitride.

[0079] In this embodiment, the material of the buffer layer 210 includes titanium nitride. The buffer layer 210 is used to form a pad layer 211 on the third dielectric layer 205, and also serves as a stop layer for subsequent planarization of the pad layer 211 and the initial electrical connection layer 209.

[0080] Please refer to Figure 9 The padding layer 211, the buffer layer 210 and the initial electrical connection layer 209 are planarized until the surface of the third dielectric layer 205 is exposed, forming the electrical connection layer 212.

[0081] The process of planarizing the pad layer 211, buffer layer 210 and initial electrical connection layer 209 includes a chemical mechanical polishing process, wherein the polishing solution of the chemical mechanical polishing process is an acidic solution.

[0082] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 9 ,include:

[0083] Substrate 200, wherein the substrate 200 has a fin structure;

[0084] A gate structure located on a substrate 200 and source / drain doped regions located in fin structures on both sides of the gate structure, the gate structure spanning the fin structures;

[0085] A first dielectric layer is located on substrate 200, and the gate structure is located within the first dielectric layer;

[0086] A second dielectric layer 201 is located on the first dielectric layer. The second dielectric layer 201 and the first dielectric layer have a plurality of first openings, and the first openings expose a portion of the surface of the source and drain doped regions.

[0087] A first conductive structure located within a first opening, the first conductive structure comprising a barrier layer 207 located on the sidewall surface and bottom surface of the first opening and a conductive layer 204 located on the surface of the barrier layer 207, wherein the top surface of the barrier layer 207 is lower than the top surface of the conductive layer 204;

[0088] A third dielectric layer 205 is located on the second dielectric layer 201 and the first conductive structure;

[0089] A second opening located within the third dielectric layer 205 exposes the top surface of the first conductive structure;

[0090] A third opening is located at the bottom of the second opening, and the third opening exposes the top surface of the barrier layer 207 and part of the sidewall surface of the conductive layer 204;

[0091] An electrical connection layer 212 is located within the third opening and the second opening, and the electrical connection layer is located on the first conductive structure.

[0092] In this embodiment, the first conductive structure extends along a first direction parallel to the surface of the substrate 200, and the conductive layer 204 has a first dimension d1 along a second direction Y parallel to the surface of the substrate 200, wherein the first direction is perpendicular to the second direction Y.

[0093] In this embodiment, the top surface of the barrier layer 207 to the top surface of the conductive layer 204 has a second dimension d2 along a direction perpendicular to the substrate surface, and the ratio of the second dimension d2 to the first dimension d1 ranges from 1:4 to 3:2.

[0094] In this embodiment, the aspect ratio of the second opening is in the range of 1 to 8; the aspect ratio of the third opening is in the range of 1 to 6.

[0095] In this embodiment, the material of the barrier layer 207 includes a metal nitride, which includes titanium nitride or tantalum nitride; the material of the conductive layer 204 includes a metal, which includes cobalt.

[0096] In this embodiment, the material of the electrical connection layer 212 includes metal, and the metal includes tungsten.

[0097] In this embodiment, it further includes a second conductive structure located within the second dielectric layer 201, the second conductive structure being located on the gate structure.

[0098] In this embodiment, it further includes: a first stop layer located between the first dielectric layer and the second dielectric layer 201; and a second stop layer located between the second dielectric layer and the third dielectric layer 205.

[0099] In this embodiment, it further includes: an isolation layer located on the substrate, the isolation layer being located on the sidewall of the fin structure and the top surface of the isolation layer being lower than the top surface of the fin structure; and the gate structure being located on the isolation layer.

[0100] In the semiconductor structure, because the top surface of the barrier layer 207 is lower than the top surface of the conductive layer 204, meaning the barrier layer 207 exposes part of the sidewall surface of the conductive layer 204, the exposed surface area of ​​the conductive layer 204 is increased. Therefore, when the initial electrical connection layer 209 is formed within the third opening 208 and the second opening 206 using a selective deposition process, the growth area of ​​the initial electrical connection layer 209 on the surface of the conductive layer 204 is increased. This increases the growth rate of the selective deposition process on the smaller-sized conductive layer 204 surface, improving the growth uniformity of the selective deposition process. This is beneficial for increasing the uniformity of the initial electrical connection layer 209 filling the second opening 206, and improving the quality of the subsequently formed electrical connection layer.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a fin structure; A gate structure located on a substrate and source / drain doped regions located within fin structures on both sides of the gate structure, the gate structure spanning the fin structures; A first dielectric layer is located on the substrate, and the gate structure is located within the first dielectric layer; A second dielectric layer is located on the first dielectric layer, and the second dielectric layer and the first dielectric layer have a plurality of first openings, the first openings exposing a portion of the surface of the source and drain doped regions; A first conductive structure located within a first opening, the first conductive structure comprising a barrier layer located on the sidewall surface and bottom surface of the first opening and a conductive layer located on the surface of the barrier layer, the top surface of the barrier layer being lower than the top surface of the conductive layer, and the barrier layer exposing a portion of the sidewall surface of the conductive layer; A third dielectric layer located on the second dielectric layer and the first conductive structure; A second opening located within the third dielectric layer exposes the top surface of the first conductive structure; A third opening is located at the bottom of the second opening, the third opening exposing the top surface of the barrier layer and part of the sidewall surface of the conductive layer; An electrical connection layer is located within the third opening and the second opening, and the electrical connection layer is located on the first conductive structure.

2. The semiconductor structure as described in claim 1, characterized in that, The first conductive structure extends along a first direction parallel to the substrate surface, and the conductive layer has a first dimension along a second direction parallel to the substrate surface, wherein the first direction is perpendicular to the second direction.

3. The semiconductor structure as described in claim 2, characterized in that, Along a direction perpendicular to the substrate surface, the top surface of the barrier layer to the top surface of the conductive layer has a second dimension, the ratio of the second dimension to the first dimension ranging from 1:4 to 3:

2.

4. The semiconductor structure as described in claim 1, characterized in that, The aspect ratio of the second opening is in the range of 1 to 8; the aspect ratio of the third opening is in the range of 1 to 6.

5. The semiconductor structure as described in claim 1, characterized in that, The barrier layer is made of a metal nitride, including titanium nitride or tantalum nitride; the conductive layer is made of a metal, including cobalt.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the electrical connection layer includes metal, including tungsten.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second conductive structure located within a second dielectric layer, the second conductive structure being located on a gate structure.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first stop layer located between a first dielectric layer and a second dielectric layer; The second stop layer is located between the second dielectric layer and the third dielectric layer.

9. The semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation layer located on a substrate, the isolation layer being located on the sidewall of the fin structure and the top surface of the isolation layer being lower than the top surface of the fin structure; The gate structure is located on the isolation layer.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a fin structure; A gate structure, source / drain doped regions located within fin structures on both sides of the gate structure, and a first dielectric layer are formed on a substrate. The gate structure spans the fin structures and is located within the first dielectric layer. A second dielectric layer is formed on a first dielectric layer, and the second dielectric layer and the first dielectric layer have a plurality of first openings, the first openings exposing a portion of the surface of the source and drain doped regions; A first conductive structure is formed within the first opening. The first conductive structure includes an initial barrier layer located on the sidewall surface and bottom surface of the first opening, and a conductive layer located on the surface of the initial barrier layer. A third dielectric layer is formed on the second dielectric layer and the first conductive structure, the third dielectric layer having a second opening that exposes the top surface of the first conductive structure; The portion of the initial barrier layer exposed by the second opening is removed to form a barrier layer, and a third opening communicating with the second opening is formed in the third dielectric layer, wherein the top surface of the barrier layer is lower than the top surface of the conductive layer; An initial electrical connection layer was formed in the third opening and the second opening using a selective deposition process.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first conductive structure extends along a first direction parallel to the substrate surface, and the conductive layer has a first dimension along a second direction parallel to the substrate surface, wherein the first direction is perpendicular to the second direction.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Along a direction perpendicular to the substrate surface, the top surface of the barrier layer to the top surface of the conductive layer has a second dimension, the ratio of the second dimension to the first dimension ranging from 1:4 to 3:

2.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The aspect ratio of the second opening is in the range of 1 to 8; the aspect ratio of the third opening is in the range of 1 to 6.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The barrier layer is made of a metal nitride, including titanium nitride or tantalum nitride; the conductive layer is made of a metal, including cobalt.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, The material of the initial electrical connection layer includes a metal, including tungsten.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process parameters for the selective deposition process that forms the initial electrical connection layer include: a temperature of 300°C to 400°C and a reaction gas mixture of hydrogen and tungsten hexafluoride.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the initial electrical connection layer, the process further includes: forming a buffer layer on the third dielectric layer and the initial electrical connection layer; forming a pad layer on the buffer layer; and planarizing the pad layer, the buffer layer, and the initial electrical connection layer until the surface of the third dielectric layer is exposed to form the electrical connection layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The padding layer and the initial electrical connection layer are made of the same material.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process for forming the liner layer includes chemical vapor deposition.

20. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the buffer layer includes metal nitrides, including titanium nitride or tantalum nitride.

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