A silicon-based silicon germanium heterojunction bipolar transistor and method of fabrication thereof

Abstract

This invention relates to a silicon-based silicon-germanium heterojunction bipolar transistor and its manufacturing method, belonging to the field of electronic technology. An N+BL buried layer is formed by ion implantation on a substrate; a silicon tetranitride stress layer is formed on the N+BL buried layer; an N- collector region is formed by ion implantation; a silicon dioxide masking layer is formed by oxidation; after etching out the collector region window, boron ion implantation is performed, followed by rapid annealing to eliminate lattice damage; an N+BL buried layer connectivity region is formed by ion implantation; and Si is selectively epitaxially grown in the strained base region. 1‑x Ge x Base region; in Si 1‑x Ge x A silicon cap layer is deposited above the base region; N-type polysilicon is deposited as the emitter; Si is etched and SiGe material is deposited together with the silicon tetranitride stress layer to form the collector stress region; the metals other than the collector, emitter, and base are photolithographically formed to create electrode leads. This invention can enhance carrier mobility, reduce the total carrier transit time, and improve transistor operating speed.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of electronic technology, and relates to a silicon-based silicon germanium heterojunction bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] With the continuous development of modern mobile communication and microwave communication, circuit technology is required to have faster working speed, higher working frequency and lower power consumption, and the market also increasingly demands low-cost and high-performance devices. However, due to the limitation of the physical properties of Si material, the conventional Si device is difficult to have a breakthrough in speed and frequency characteristics. In the 1980s, a heterojunction bipolar transistor made of III-V elements appeared, which marked a great breakthrough in the research of transistors. Compared with the ordinary homojunction bipolar junction transistor, the biggest advantage of the heterojunction bipolar transistor is that its frequency characteristic is more excellent, and the overall performance of the device breaks through to a new level without sacrificing the current gain. Although the III-V compound semiconductor device is much faster than the Si device, it is not compatible with the mature Si device process and has too high manufacturing cost.

[0003] The appearance of the silicon germanium heterojunction bipolar transistor (SiGe HBT) can effectively improve the speed and frequency of the device and reduce the manufacturing cost, and is easy to mass-produce. The silicon germanium heterojunction bipolar transistor is a silicon-based bipolar junction transistor with a small amount of Ge component added to the base region, and the base region adopts SiGe material, which significantly improves the performance of the device, so that the SiGe HBT becomes a standard bipolar transistor in high-speed applications. The heterojunction bipolar transistor based on the SiGe process developed on the basis of the mature silicon process utilizes the advantages of band engineering and solves the contradiction between improving the amplification factor and improving the frequency characteristic. However, there is a certain limit to improve the performance of the device only by relying on this technology.

[0004] With the development of SiGe HBT towards smaller feature size and higher integration, the combination of traditional SiGe HBT and strain Si technology can further improve the performance of SiGe HBT and expand its application range. The silicon-based strain technology can effectively improve the mobility of the transistor and thus improve the performance of the device, so the new SiGe HBT device structure combining the strain Si technology has important significance for the development of high-frequency / high-performance semiconductor devices and integrated circuits. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a silicon-based silicon germanium heterojunction bipolar transistor and a manufacturing method thereof, and realize a new strain transistor structure.

[0006] To achieve the above purpose, the present application provides the following technical solutions:

[0007] Scheme one, a silicon-based silicon germanium heterojunction bipolar transistor, the transistor comprising:

[0008] An N-type silicon-based substrate, a (100) crystal surface;

[0009] An N+BL buried layer for reducing series resistance;

[0010] An N- collector region;

[0011] A silicon nitride stress layer as a stress source for the collector region;

[0012] Si 1-x Ge x A stress region, forming a collector region stress region with the silicon nitride stress layer;

[0013] Si 1-x Ge x A base region, with a ladder-type distribution of Ge composition;

[0014] Si 1-x Ge x A silicon cap layer formed by depositing a single-crystal silicon thin layer on the base region;

[0015] A polysilicon emitter region, by depositing N-type polysilicon on the silicon cap layer as an emitter;

[0016] Silicon nitride and silicon dioxide stress barriers, providing a stress source for the emitter region.

[0017] Wherein the N-type silicon-based substrate, the N+BL buried layer, the N- collector region, the Si 1-x Ge x Base region, the silicon cap layer, and the polysilicon emitter region are arranged from bottom to top; the silicon nitride stress layer is located between the N+BL buried layer and the Si 1-x Ge x Stress region, and is in contact with the N- collector region; the silicon nitride and silicon dioxide stress barriers are arranged on both sides of the emitter region.

[0018] By etching and depositing SiGe material in the N+BL buried layer and the N- collector region, and simultaneously implanting a silicon nitride stress layer below the Si 1-x Ge x Stress region to introduce stress, the silicon nitride stress layer as a stress source for the collector region applies uniaxial compressive stress, improving the frequency characteristics of the device while reducing the maximum electric field strength of the collector region stress region to improve the breakdown voltage of the device; in the silicon nitride and silicon dioxide stress barriers, the silicon nitride as a stress source for the emitter region, the stress applied causes the energy band structure of the device to change, resulting in an increase in the mobility of the carriers.

[0019] Optionally, the transistor further comprises:

[0020] Si 1-x Ge x Si 1-x Ge x epi base region;

[0021] P+ connection region formed by ion implantation in N-collector region, P+ connection region located between N-collector region and silicon nitride stress layer and silicon dioxide stress layer;

[0022] N+BL buried layer communication region formed on N+BL buried layer;

[0023] and polycrystalline silicon collector region formed by depositing polycrystalline silicon on Si 1-x Ge x epi base region and N+BL buried layer communication region respectively.

[0024] Optionally, the transistor further comprises a metal electrode formed on the polycrystalline silicon emitter region, the polycrystalline silicon epi base region and the polycrystalline silicon collector region.

[0025] Scheme two, a method for manufacturing a silicon-based silicon germanium heterojunction bipolar transistor, the method steps as follows:

[0026] S1, selecting a single crystal N-type Si substrate with a (100) crystal face;

[0027] S2, growing an N+BL buried layer on the substrate by ion implantation;

[0028] S3, forming a silicon nitride stress layer on the N+BL buried layer by stress technology;

[0029] S4, forming an N-collector region by ion implantation;

[0030] S5, forming a silicon dioxide mask layer by oxidation at a position corresponding to the collector region of the base region window, performing boron ion implantation after etching the collector region window, and performing a rapid annealing operation to eliminate lattice damage to form a P+ connection region;

[0031] S6, forming an N+BL buried layer communication region by ion implantation to connect the N+BL buried layer;

[0032] S7, forming an emitter stress side wall by photolithography of silicon nitride and silicon dioxide;

[0033] S8, etching a silicon dioxide intermediate region in the strained base region and selectively epitaxially growing Si 1-x Ge x base region;

[0034] S9, depositing a silicon cap layer above the Si 1-x Ge x base region;

[0035] S10. Deposit N-type polysilicon as the emitter on the silicon cap layer of the emitter region;

[0036] S11. Etch Si in the stress region of the collector region and deposit SiGe material with a Ge composition of 25% and a silicon tetranitride stress layer to form the stress region of the device collector region.

[0037] S12, the metal other than the photolithographic collector, emitter and base, forms the electrode leads.

[0038] The beneficial effects of this invention are as follows: This invention organically combines "strain technology" with traditional SiGe HBTs. By implanting a silicon tetranitride stress layer in the N+BL buried layer and the N- collector region using stress technology, a stress source is generated in the collector region. At the same time, the silicon tetranitride and silicon dioxide stress sidewalls in the emitter region generate stress in the emitter region, thus forming a new strained silicon-based silicon-germanium heterojunction bipolar transistor structure. The collector and base regions of the bipolar part are subjected to stress, causing the valence band energy band to split. The heavy hole band leaves the top of the valence band, while the light hole band remains at the top of the valence band, thereby reducing the effective mass of hole conductance in this direction, enhancing the mobility of charge carriers, and reducing the total transit time of charge carriers. The silicon tetranitride stress layer, as a stress source, improves the frequency characteristics of the device while reducing the highest electric field strength in the stress region of the collector region, thus increasing the breakdown voltage of the device and improving the overall operating speed of the heterojunction transistor.

[0039] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0041] Figure 1 This invention relates to a silicon-based silicon-germanium heterojunction bipolar transistor;

[0042] Figures 2 to 7 This is a schematic diagram illustrating the manufacturing process of the silicon-based silicon-germanium heterojunction bipolar transistor of the present invention.

[0043] Figure reference numerals: 1-Substrate; 2-N+BL buried layer; 3-Trisilicon tetranitride stress layer; 4-N-Catcher region; 5-P+ Connector region; 6-Silicon dioxide sidewall; 7-N+BL buried layer interconnection region; 8-Trisilicon tetranitride and silicon dioxide stress barrier layer; 9-Si 1-x Ge xBase region; 10-Silicon cap layer; 11-Polycrystalline silicon emitter region; 12-Si 1-x Ge x Stress region; 13-Si 1-x Ge x 14 - Epitaxial base region; 15 - Polycrystalline silicon epitaxial base region; 16 - Polycrystalline silicon collector region; 17 - Aluminum metal electrode. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0045] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0046] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0047] Figure 1 This is a schematic diagram of the silicon-based silicon-germanium heterojunction bipolar transistor of the present invention. The transistor structure includes an N-type silicon substrate 1 with a (100) crystal plane; an N+BL buried layer 2 above the substrate; silicon dioxide sidewalls 6, a silicon tetranitride stress layer 3, an N-collector region 4, and an N+BL buried layer connectivity region 7 above the N+BL buried layer; and Si atoms sequentially formed above the silicon tetranitride stress layer. 1- x Ge x Stress region 12, Si 1-x Ge xEpitaxial base region 13, polysilicon epitaxial base region 14, and aluminum metal electrode 16 are symmetrically formed in this stacked structure on both sides of N-collector region 3; P+ connection region 5 is formed on the upper side of N-collector region 3; Si is formed sequentially above P+ connection region. 1-x Ge x The base region 9, the silicon cap layer 10, the polycrystalline silicon emitter region 11, and the aluminum metal electrode 16; the tetranitride and silicon dioxide stress isolation layer 8 formed on both sides of the emitter region; the polycrystalline silicon collector region 15 and the aluminum metal electrode 16 formed sequentially in the N+BL buried layer connecting region 7.

[0048] like Figures 2 to 7 The diagram shows the process flow of the silicon-based silicon-germanium heterojunction bipolar transistor manufacturing method of the present invention. The specific process is as follows:

[0049] S1. Prepare a single-crystal N-type Si substrate 1 with a crystal plane of (100) and a substrate thickness of 100 nm;

[0050] S2. Deposit Si material with a thickness of 180 nm on a substrate. The impurity is phosphorus, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 This forms an N+BL buried layer 2;

[0051] S3. A silicon tetranitride material with a thickness of 100 nm is grown on the buried layer to form a silicon tetranitride stress layer 3, which serves as a stress source for the collector region.

[0052] S4. A 100 nm thick Si material is deposited, with phosphorus as the dopant and a doping concentration of 5 × 10⁻⁶. 17 cm -3 , as N-collector region 4;

[0053] S5. A silicon dioxide masking layer is grown at the location corresponding to the base window in the collector region through oxidation, and the collector region window is etched out. Then, boron ion implantation is performed. After ion implantation, a rapid annealing operation is performed to eliminate lattice damage. Then, the silicon dioxide masking layer is etched flattened, forming the P+ connection region 5, in which the boron ion doping concentration is 1×10⁻⁶. 12 cm -3 ;

[0054] S6. Etch away the side area of ​​the N-collector region 4, and grow a silicon dioxide isolation layer 6 through thermal oxidation; then etch away part of the silicon dioxide to reserve the collector electrode area and deposit Si material, with phosphorus as the dopant impurity and a doping concentration of 1×10⁻⁶. 20 cm -3 This forms the N+BL buried layer connectivity region 7, which connects the N+BL buried layers; then, silicon dioxide is grown again to etch the excess portion, resulting in the structure shown below. Figure 2 As shown;

[0055] S7. Etch the emitter sidewall position, grow a layer of silicon tetranitride, etch out the emitter stress sidewall, and form a silicon tetranitride and silicon dioxide stress barrier layer 8.

[0056] S8. Etch silicon dioxide at the emitter region location and selectively epitaxially grow Si. 1-x Ge x Base region 9, in which the Ge composition has a stepped distribution of 18%–30%, and the dopant is boron with a doping concentration of 2.5 × 10⁻⁶. 18 cm -3 The thickness is 30nm;

[0057] S9, in Si 1-x Ge x A strained Si layer with a thickness of 20 nm was selectively epitaxially grown on the base region. The dopant was phosphorus with a doping concentration of 2.5 × 10⁻⁶. 18 cm -3 A silicon cap layer 10 is formed;

[0058] The structure at this time is as follows Figure 3 As shown;

[0059] S10. Polycrystalline silicon material is deposited on the silicon cap layer to form a polycrystalline silicon emitter region 11, which serves as the emitter electrode region. The dopant is arsenic, and the doping concentration is 3×10⁻⁶. 19 cm -3 Then, a layer of silicon dioxide is grown and excess oxide is etched away, resulting in a structure like this. Figure 4 As shown;

[0060] S11. Selectively etch silicon dioxide at the corresponding positions of the base region, and grow Si on the silicon tetranitride stress layer. 1- x Ge x Stress materials, forming Si 1-x Ge x Stress region 12, wherein the Ge composition is 25% and the doping concentration is 1×10⁻⁶. 19 cm -3 ;

[0061] S12, in Si 1-x Ge x Selective epitaxial growth of Si in stress region 1-x Ge x Epitaxial base region 13, wherein the Ge composition is 25% and the doping impurity is boron, with a doping concentration of 1×10⁻⁶. 20 cm -3 At this time, the structure is as follows Figure 5 As shown;

[0062] S13, in Si 1-x Ge xSelective epitaxial growth of polycrystalline silicon material on the epitaxial base region forms a polycrystalline silicon epitaxial base region 14, which serves as the base electrode region. The impurity in this region is boron, with a doping concentration of 1×10⁻⁶. 20 cm -3 ;

[0063] S14. Polycrystalline silicon material is deposited on the N+BL buried layer interconnection region 7 to form a polycrystalline silicon current collector region 15. The dopant is phosphorus, and the doping concentration is 1×10⁻⁶. 20 cm -3 The structure at this time is as follows Figure 6 As shown;

[0064] S15. Etch away excess silicon dioxide protective layer, but retain some silicon dioxide to form silicon dioxide sidewalls 6. Finally, form an aluminum film on the entire surface through vacuum evaporation. Then, use photolithography to remove any metal areas outside the electrode to form aluminum metal electrode 16. The structure at this point is as follows: Figure 7 As shown.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A silicon-based silicon-germanium heterojunction bipolar transistor, characterized in that: The transistor includes: N-type silicon substrate with (100) crystal plane; N+BL buried layer is used to reduce series resistance; N-collector region; A silicon tetranitride stress layer serves as a stress source for the collector region; Si 1-x Ge x The stress region forms a collector stress region with the tetranitride trisilicon stress layer; In the Si 1-x Ge x Si formed on the stress region 1-x Ge x Extensional base region; Si 1-x Ge x The base region contains a stepped distribution of Ge components; Si 1-x Ge x A silicon cap layer is formed by depositing a thin layer of single-crystal silicon on the base region; The polycrystalline silicon emitter region is formed by depositing N-type polycrystalline silicon on the silicon cap layer as the emitter. A stress-absorbing layer of silicon tetranitride and silicon dioxide provides a stress source for the emission region; The N-type silicon substrate, N+BL buried layer, N- collector region, Si 1-x Ge x The base region, silicon cap layer, and polycrystalline silicon emitter region are arranged sequentially from bottom to top; the tetranitride trisilicon stress layer is located between the N+BL buried layer and the Si. 1-x Ge x Between the stress regions and in contact with the N-collector region; the tetranitride and silicon dioxide stress isolation layers are disposed on both sides of the emitter region.

2. The silicon-based silicon-germanium heterojunction bipolar transistor according to claim 1, characterized in that: SiGe material was etched and deposited within the N+BL buried layer and the N- collector region, while stress technology was employed on the Si... 1-x Ge x A silicon tetranitride stress layer is implanted below the stress region to introduce stress. The silicon tetranitride stress layer acts as a stress source for the collector region, applying uniaxial compressive stress to the collector region. This improves the frequency characteristics of the device while reducing the highest electric field strength in the collector region stress region and improving the breakdown voltage of the device. In the silicon tetranitride and silicon dioxide stress barrier layer, silicon tetranitride acts as a stress source in the emitter region. The applied stress causes a change in the energy band structure of the device, thereby increasing the mobility of charge carriers.

3. The silicon-based silicon-germanium heterojunction bipolar transistor according to claim 1, characterized in that: The transistor also includes: The P+ connection region is formed by ion implantation in the N- collector region, and the P+ connection region is located between the N- collector region and the silicon tetranitride and silicon dioxide stress barrier layer; The N+BL buried layer connected region formed on the N+BL buried layer; and respectively in Si 1-x Ge x Polycrystalline silicon epitaxial base region and polycrystalline silicon collector region are formed by depositing polycrystalline silicon on the epitaxial base region and the N+BL buried layer connection region.

4. A silicon-based silicon-germanium heterojunction bipolar transistor according to claim 3, characterized in that: The transistor also includes metal electrodes formed on the polysilicon emitter region, the polysilicon epitaxial base region, and the polysilicon collector region.

5. A method for manufacturing a silicon-based silicon-germanium heterojunction bipolar transistor according to any one of claims 1 to 4, characterized in that: The method specifically includes the following steps: S1. Select a single-crystal N-type Si substrate with a crystal plane of (100); S2. An N+BL buried layer is grown on the substrate by ion implantation; S3. A tetranitride trisilicon stress layer is formed on the N+BL buried layer using stress technology; S4. Forming an N-collector region through ion implantation; S5. A silicon dioxide masking layer is formed at the position of the collector region corresponding to the base region window by oxidation. After etching out the collector region window, boron ion implantation is performed, and a rapid annealing operation is performed to eliminate lattice damage and form a P+ connection region. S6. Connect the N+BL buried layer by forming a connected region of the N+BL buried layer through ion implantation; S7. Photolithography of silicon tetranitride and silicon dioxide forms stress sidewalls in the emitter region; S8. Etch the intermediate region of silicon dioxide in the strained base region and selectively epitaxially grow Si. 1-x Ge x Base region; S9, in Si 1-x Ge x A silicon cap layer is deposited above the base region; S10. Deposit N-type polysilicon as the emitter on the silicon cap layer of the emitter region; S11. Etch Si in the stress region of the collector region and deposit SiGe material with a Ge composition of 25% and a silicon tetranitride stress layer to form the stress region of the device collector region. S12, the metal other than the photolithographic collector, emitter and base, forms the electrode leads.

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