Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof. In the semiconductor structure, a U-shaped channel layer is arranged in a vertical through hole in a gate conductive layer, and a first contact pad and a second contact pad are arranged at the bottom and the top of the U-shaped channel layer respectively, so that the semiconductor structure is arranged in a vertical manner as a whole, and the size is reduced. In addition, the U-shaped channel layer has a first channel layer and a second channel layer, the first channel layer can be used to cover a gate dielectric layer during preparation of the gate dielectric layer, so that the gate dielectric layer is prevented from being subjected to etching bombardment to cause etching damage, and the performance stability of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of semiconductor technology, semiconductor integrated circuits tend to be designed in smaller size and arranged in higher density. However, it is more difficult to further reduce the size of semiconductor structures for smaller and smaller semiconductor structures, which is often limited by the resolution of a lithography device. Specifically, in semiconductor manufacturing, the minimum size of a prepared pattern (such as line width and line spacing) depends on the resolution of the lithography device. Under the limitation of the minimum feature size that can be obtained by the lithography device, it is difficult to stably obtain a pattern smaller than the minimum feature size, thereby limiting the further reduction of the size of the semiconductor structure. Moreover, the performance of the prepared smaller semiconductor structure is also easily affected by the preparation process. SUMMARY

[0003] The present application aims to provide a semiconductor structure to reduce the size of the semiconductor structure and improve the stability of the device.

[0004] To this end, the present application provides a semiconductor structure, comprising: a substrate; a first contact pad and a first insulating structure formed on the substrate, the first insulating structure surrounding the outer periphery of the first contact pad; a gate conductive layer formed on the first insulating structure, and a vertical via hole is further formed in the center of the gate conductive layer, the via hole being located above the first contact pad; a gate dielectric layer arranged on the side wall of the gate conductive layer exposed to the via hole; a U-shaped channel layer formed in the via hole, the U-shaped channel layer comprising a first channel layer and a second channel layer, the first channel layer being arranged on the side wall of the gate dielectric layer exposed to the via hole, and the second channel layer being arranged on the side wall of the first channel layer and covering the first contact pad at the bottom of the via hole; and a second contact pad arranged at the top of the via hole and connected to the U-shaped channel layer.

[0005] Optionally, the materials of the first channel layer and the second channel layer both comprise polysilicon.

[0006] Optionally, the material of the U-shaped channel layer comprises polysilicon of a first doping type, and the materials of the first contact pad and the second contact pad comprise polysilicon of a second doping type.

[0007] Optionally, the semiconductor structure further comprises a second insulating structure, the second insulating structure being filled in the via hole, and the second contact pad being formed on the second insulating structure.

[0008] Optionally, a top position of the second insulating structure is lower than a top position of the via, and the second contact pad fills the via.

[0009] Optionally, the semiconductor structure further comprises a first wire and a second wire, the first wire is formed below the first contact pad and extends along a first direction, and the second wire is formed above the second contact pad and extends along a second direction.

[0010] The present application also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a first contact pad and a first insulating structure on the substrate, the first insulating structure surrounds an outer periphery of the first contact pad; forming a gate conductive layer on the first insulating structure, and forming a vertical via in a center of the gate conductive layer, the via is above the first contact pad; forming a gate dielectric layer and a U-shaped channel layer in the via, the gate dielectric layer covers sidewalls of the gate conductive layer exposed to the via, and the U-shaped channel layer comprises a first channel layer and a second channel layer, the first channel layer covers the gate dielectric layer, and the second channel layer covers the first channel layer and the first contact pad at a bottom of the via; and forming a second contact pad at a top of the via, the second contact pad connects the U-shaped channel layer.

[0011] Optionally, the method for forming the gate dielectric layer and the U-shaped channel layer comprises: sequentially depositing a dielectric material layer and a first channel material layer, the dielectric material layer and the first channel material layer cover sidewalls and a bottom of the via; performing an etching process to remove a portion of the first channel material layer covering the bottom of the via, and to retain a portion of the first channel material layer covering the sidewalls of the via to constitute the first channel layer; continuing to etch a portion of the dielectric material layer covering the bottom of the via and exposed, and to retain a portion of the dielectric material layer covering the sidewalls of the via to constitute the gate dielectric layer; and forming the second channel layer, the second channel layer covers the first channel layer and the first contact pad at the bottom of the via.

[0012] Optionally, after forming the U-shaped channel layer, the method further comprises: forming a second insulating structure in the via, and etching back the second insulating structure to reduce a height of the second insulating structure in the via; and the second contact pad fills the via and is formed on the second insulating structure.

[0013] Optionally, before forming the first contact pad, the method further comprises: forming a first wire on the substrate, and forming the first contact pad on the first wire; and after forming the second contact pad, the method further comprises: forming a second wire, the second wire is formed above the second contact pad and extends along a second direction.

[0014] The application further provides another semiconductor structure, comprising: a substrate; a first contact pad formed on the substrate and defined by a first insulating structure on the substrate; a third insulating structure formed on the substrate and above the first contact pad and the first insulating structure, and having a through hole in the third insulating structure, the through hole exposing a top of the first contact pad; a first channel layer formed at a sidewall position of the through hole and defining an inner sidewall of the through hole; a second channel layer formed on the inner sidewall of the through hole and contacting the top of the first contact pad; a second insulating structure filled in the through hole and contacting a bottom and a sidewall of the second channel layer; and a gate dielectric layer on an outer sidewall of the first channel layer away from the second channel layer.

[0015] Optionally, the semiconductor structure further comprises a second contact pad arranged at a top of the through hole and connected to the second channel layer.

[0016] Optionally, the semiconductor structure further comprises a spacer dielectric layer arranged above the first contact pad and the first insulating structure and below the third insulating structure, the through hole extending from the third insulating structure to the spacer dielectric layer to expose the first contact pad.

[0017] Optionally, the semiconductor structure further comprises a gate conductive layer formed on a sidewall of the gate dielectric layer away from the first channel layer.

[0018] In the semiconductor structure provided by the application, the U-shaped channel layer is arranged in the vertical through hole in the gate conductive layer, and the first contact pad and the second contact pad are arranged at the bottom and the top of the U-shaped channel layer respectively, so that the first contact pad and the second contact pad can be conducted to each other through the U-shaped channel layer. The semiconductor structure is arranged in a vertical manner as a whole, and the electrical signal transmission is realized in the vertical direction. Compared with the semiconductor structure arranged in a horizontal manner, the semiconductor structure arranged in a vertical manner can effectively utilize the upper space and achieve the purpose of size reduction.

[0019] In addition, in the semiconductor structure provided by the application, the U-shaped channel layer has the first channel layer and the second channel layer, the first channel layer can be used to cover the gate dielectric layer in the preparation process of the gate dielectric layer, so as to avoid the etching damage of the gate dielectric layer caused by etching bombardment, improve the film quality of the gate dielectric layer, and further improve the performance stability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 FIG. 1 is a schematic view of a semiconductor structure in an embodiment of the application.

[0021] Figure 2A flowchart of a method for manufacturing a semiconductor structure in an embodiment of the present application.

[0022] Figures 3-8 A structural diagram of a semiconductor structure in an embodiment of the present application during manufacturing.

[0023] Wherein, the reference signs are as follows:

[0024] 100 - substrate;

[0025] 210 - first contact pad;

[0026] 220 - second contact pad;

[0027] 310 - first insulating structure;

[0028] 320 - second insulating structure;

[0029] 330 - third insulating structure;

[0030] 410 - first wire;

[0031] 420 - second wire;

[0032] 421 - metal layer;

[0033] 422 - work function layer;

[0034] 500a - via hole;

[0035] 510 - gate conductive layer;

[0036] 520 - gate dielectric layer;

[0037] 600 - U-shaped channel layer;

[0038] 610 - first channel layer;

[0039] 620 - second channel layer;

[0040] 700 - spacer dielectric layer. DETAILED DESCRIPTION

[0041] The semiconductor structure and the method for manufacturing the same according to the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are very simplified and all use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. It should be recognized that the relative terms such as "above", "below", "top", "bottom", "upper" and "lower" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of the elements other than the orientation depicted in the drawings. For example, if the device is inverted with respect to the view in the drawings, the element described as "above" another element will now be "below" the other element.

[0042] With specific reference Figure 1 As shown, the semiconductor structure in the embodiment includes a substrate 100, which can be a silicon substrate or an insulating substrate silicon (Silicon-On-Insulator, SOI), for example. A first contact pad 210 and a first insulating structure 310 are formed on the substrate 100, and the first insulating structure 310 surrounds the outer periphery of the first contact pad 210. In the embodiment, a plurality of first contact pads 210 are formed on the substrate 100, and the first insulating structure 310 is used to isolate adjacent first contact pads 210. The material of the first contact pad 210 can include polysilicon, and the material of the first insulating structure 310 can include silicon oxide.

[0043] Further, a first wire 410 is also formed on the substrate 100, which can be formed below the first contact pad 210 and extend along a first direction (in the embodiment, the first wire 410 specifically extends along a direction perpendicular to the paper surface), and the first contact pad 210 is electrically connected to the first wire 410. In a specific example, the first wire 410 includes a metal layer and a work function layer stacked from bottom to top, the material of the metal layer includes tungsten (W) for example, and the material of the work function layer includes titanium nitride (TiN) for example.

[0044] With further reference Figure 1 As shown, a spacer dielectric layer 700 is also formed on the first contact pad 210 and the first insulating structure 310, and the material of the spacer dielectric layer 700 includes silicon oxide and / or silicon nitride, for example.

[0045] The semiconductor structure further includes a gate conductive layer 510 formed on the first insulating structure 310. In this embodiment, the gate conductive layer 510 is formed on the spacer dielectric layer 700 and above the first insulating structure 310. A vertical via is further formed in the center of the gate conductive layer 510, which is above the first contact pad 210, and at least a portion of the top surface of the first contact pad 210 is exposed to the via. In this embodiment, the via penetrates the gate conductive layer 510 and further penetrates the spacer dielectric layer 700, so that the bottom of the via extends to the first contact pad 210.

[0046] In this embodiment, the semiconductor structure further includes a third insulating structure 330 covering the gate conductive layer 510. The third insulating structure 330 can specifically cover the sidewall and top of the gate conductive layer 510. The via penetrates the third insulating structure 330 and the gate conductive layer 510.

[0047] Continuing to refer to Figure 1 As shown, the semiconductor structure further includes a gate dielectric layer 520 covering the sidewall of the gate conductive layer 510 exposed to the via, i.e., the gate dielectric layer 520 covers the sidewall of the via.

[0048] In this embodiment, the material of the gate dielectric layer 520 can include silicon oxide. Alternatively, the gate dielectric layer 520 specifically includes a silicon oxide layer covering the sidewall of the gate conductive layer 510 and a silicon nitride layer covering the sidewall of the silicon oxide layer, which is converted by nitriding the sidewall of the silicon oxide layer, for example. In this example, the silicon nitride layer is provided on the outer sidewall of the gate dielectric layer 520 to prevent the gate conductive layer 510 from being oxidized. Alternatively, in other examples, an aluminum oxide layer is provided on the sidewall of the gate dielectric layer 520, which can also be used to improve the problem of the gate conductive layer 510 being oxidized.

[0049] Alternatively, in other embodiments, the gate dielectric layer 520 can include an aluminum oxide layer, etc.

[0050] In a further aspect, a U-shaped channel layer 600 is further formed in the via, which is formed in the via. The U-shaped channel layer 600 includes a first channel layer 610 and a second channel layer 620. The first channel layer 610 covers the gate dielectric layer 520, i.e., the first channel layer 610 covers the sidewall of the via. The second channel layer 620 covers the first channel layer 610 and the first contact pad 210 at the bottom of the via. The thickness of the second channel layer 620 is greater than the thickness of the first channel layer 610.

[0051] In this embodiment, the first channel layer 610 and the second channel layer 620 can have the same material, for example, both include polysilicon. In other embodiments, the material of the first channel layer 610 can include silicon nitride and / or aluminum oxide. For example, the silicon nitride layer can be formed by nitriding the sidewall of the gate dielectric layer 520, and used to form the first channel layer 610; or the aluminum oxide layer can be formed on the sidewall of the gate dielectric layer 520 by deposition process, and used to form the first channel layer 610. The first channel layer 610 with silicon nitride and / or aluminum oxide can effectively improve the problem of oxidation of the gate conductive layer 510.

[0052] In a specific example, the semiconductor structure further includes a second insulating structure 320 filled in the via. The material of the second insulating structure 320 includes, for example, silicon oxide.

[0053] Continuing to refer to Figure 1 As shown, a second contact pad 220 is further formed on the top of the via, and the second contact pad 220 is connected to the top of the U-shaped channel layer 600. The first contact pad 210 and the second contact pad 220 are respectively connected to the bottom and the top of the U-shaped channel layer 600. The first contact pad 210 and the second contact pad 220 can be formed by the same material, for example, both can be formed by polysilicon.

[0054] Specifically, the second contact pad 220 is formed on the second insulating structure 320 and electrically connected to the top of the U-shaped channel layer 600. In this embodiment, the top of the second insulating structure 320 is lower than the top of the via, and the part of the U-shaped channel layer 600 covering the top of the via is exposed in the via. The second contact pad 220 fills the via, and is electrically connected to the part of the U-shaped channel layer exposed in the via. The contact area between the second contact pad 220 and the U-shaped channel layer 600 is increased, and the contact resistance is reduced.

[0055] In an optional solution, the second contact pad 220 can extend upward from the via and be higher than the top of the via, and can also extend laterally to the outer periphery of the via to completely cover the top of the U-shaped channel layer 600, and increase the area of the top surface of the second contact pad 220.

[0056] Furthermore, the semiconductor structure also includes a second conductive line 420, which is formed above the second contact pad 220 and extends along a second direction, and the second contact pad 220 is electrically connected to the second conductive line 420. Specifically, the second conductive line 420 covers the top surface of the second contact pad 220 along its extension path. The second conductive line 420 includes a work function layer 422 and a metal layer 421 stacked from bottom to top. The work function layer 422 is made of, for example, titanium nitride (TiN), and the metal layer 421 is made of, for example, tungsten (W).

[0057] In one specific application, the U-shaped channel layer 600 is a polysilicon layer of the first doping type, and the first contact pad 210 and the second contact pad 220 are polysilicon layers of the second doping type. By applying a predetermined voltage to the gate conductive layer 510, the U-shaped channel layer 600 is controlled to invert to form a conductive channel, thereby enabling the first contact pad 210 and the second contact pad 220 to conduct to each other through the conductive channel in the U-shaped channel layer 600.

[0058] For example, the fabrication method of the semiconductor structure described above. Figure 2 As shown, the specific steps may include the following.

[0059] Step S100: Provide a substrate.

[0060] Step S200: A first contact pad and a first insulating structure are formed on the substrate, the first insulating structure surrounding the outer periphery of the first contact pad.

[0061] In step S300, a gate conductive layer is formed on the first insulating structure, and a vertical through hole is formed at the center of the gate conductive layer, the through hole being located above the first contact pad.

[0062] Step S400: A gate dielectric layer and a U-shaped channel layer are formed within the via. The gate dielectric layer covers the gate conductive layer and is exposed on the sidewall of the via. The U-shaped channel layer includes a first channel layer and a second channel layer. The first channel layer covers the gate dielectric layer, and the second channel layer covers the first channel layer and a first contact pad at the bottom of the via.

[0063] In step S500, a second contact pad is formed on top of the through hole, and the second contact pad is connected to the U-shaped channel layer.

[0064] The following is combined Figures 3-8 The fabrication method of semiconductor structures is described in detail, including... Figures 3-8 This is a schematic diagram of the semiconductor structure in the fabrication process of an embodiment of the present invention.

[0065] In step S100, with reference to Figure 3 As shown in FIG. 1, a substrate 100 is provided, which can be a silicon substrate or an insulating substrate silicon (Silicon-On-Insulator, SOI) for example.

[0066] In step S200, with reference to Figure 3 As shown in FIG. 2, a first contact pad 210 and a first insulating structure 310 are formed on the substrate 100, the first insulating structure 310 surrounding an outer periphery of the first contact pad 210.

[0067] In this embodiment, before the first contact pad 210 is prepared, a first conductive line 410 is further formed on the substrate 100, the first conductive line 410 extending along a first direction, which in this embodiment is a direction perpendicular to the paper plane. In a specific example, the first conductive line 410 includes a metal layer and a work function layer stacked from bottom to top, the material of the metal layer including tungsten (W) for example, and the material of the work function layer including titanium nitride (TiN) for example.

[0068] Further, the first contact pad 210 is formed above the first conductive line 410 to be electrically connected with the first conductive line 410.

[0069] Further, after the first contact pad 210 and the first insulating structure 310 are prepared, a spacer medium layer 700 can be further formed on the first contact pad 210 and the first insulating structure 310.

[0070] In step S300, with reference to Figure 3 As shown in FIG. 3, a gate conductive layer 510 is formed on the first insulating structure 310, and a vertical via hole 500a is formed in the center of the gate conductive layer 510, the via hole 500a being located above the first contact pad 210.

[0071] Specifically, after the gate conductive layer 510 is formed, the gate conductive layer 510 can be etched to form the vertical via hole 500a. In this embodiment, before the gate conductive layer 510 is etched, a third insulating structure 330 is further formed, which covers the sidewall and top of the gate conductive layer 510, and then the third insulating structure 330 and the gate conductive layer 510 are etched to form the via hole 500a.

[0072] In step S400, with reference to Figures 4-6As shown, a gate dielectric layer 520 and a U-shaped channel layer 600 are formed in the via 500a. The gate dielectric layer 520 covers the sidewall of the gate conductive layer 510 exposed to the via 500a. The U-shaped channel layer 600 includes a first channel layer 610 and a second channel layer 620. The first channel layer 610 covers the gate dielectric layer 520. The second channel layer 620 covers the first channel layer 610 and the first contact pad 210 at the bottom of the via.

[0073] In this embodiment, the method for forming the gate dielectric layer 520 and the U-shaped channel layer 600 can include the following steps.

[0074] Step one, with reference to Figure 4 As shown, a dielectric material layer 520a and a first channel material layer 610a are sequentially deposited. The dielectric material layer 520a and the first channel material layer 610a both cover the sidewall and the bottom of the via 500a, and further cover the top surface of the third insulating structure 330.

[0075] Step two, with reference to Figure 5 As shown, an etching process is performed to remove the portion of the first channel material layer 610a covering the bottom of the via, and simultaneously remove the portion of the first channel material layer 610a covering the top surface of the third insulating structure 330, and retain the portion of the first channel material layer 610a covering the sidewall of the via to form the first channel layer 610. At this time, the portion of the dielectric material layer 520a covering the bottom of the via is retained.

[0076] Step three, with reference to Figure 5 As shown, the exposed portion of the dielectric material layer 520a covering the bottom of the via is continuously etched. In this embodiment, the portion of the dielectric material layer 520a covering the top surface of the third insulating structure 330 is also removed, and the portion of the dielectric material layer covering the sidewall of the via is retained to form the gate dielectric layer 520.

[0077] That is, in this embodiment, the gate dielectric layer 520 retained finally is formed by a patterning process under the mask of the first channel layer 610. Therefore, the gate dielectric layer 520 retained finally can be protected from etching in the patterning process, and the gate dielectric layer 520 can be free from etching damage. Thus, the performance of the semiconductor structure formed finally can be improved.

[0078] Step four, with reference to Figure 6 and Figure 8 As shown, a second channel layer 620 is formed. The second channel layer 620 covers the first channel layer 610 and the first contact pad 210 at the bottom of the via.

[0079] Specifically, the preparation method of the second channel layer 620 can include: first referring to Figure 6 As shown in FIG. 6B, a second channel material layer 620a is deposited, covering the first channel layer 610 and the first contact pad 210 at the bottom of the via, and also covering the top surface of the third insulating structure 330; then referring to Figure 8 As shown in FIG. 6C, the part of the second channel material layer 620a covering the top surface of the third insulating structure is removed.

[0080] In this embodiment, the dielectric material used to form the gate dielectric layer 520 can include silicon oxide. In a specific scheme, the silicon oxide material can be deposited by a deposition process (e.g., chemical vapor deposition process CVD or atomic layer deposition process ALD) to form a silicon oxide layer, and after the deposition of the silicon oxide layer, at least the sidewall part of the silicon oxide layer can be further subjected to a nitridation process, for example, the at least sidewall part of the silicon oxide layer can be subjected to a plasma treatment by using ammonia (NH3) or nitrogen (N2), so as to be converted into a silicon nitride layer, so that the formed dielectric material layer 520a further includes a silicon nitride layer. Alternatively, after the deposition of the silicon oxide layer, a silicon nitride layer can be directly deposited by a deposition process (e.g., chemical vapor deposition process CVD or atomic layer deposition process ALD). In addition, in other embodiments, after the formation of the dielectric material layer 520a, a metal oxide layer can be formed on the dielectric material layer 520a, and the metal oxide layer can specifically be an aluminum oxide layer. In this way, the outer sidewall of the formed gate dielectric layer 520 is provided with a silicon nitride layer or a metal oxide layer, so as to improve the problem of oxidation of the gate conductive layer 510.

[0081] Further, the materials of the first channel layer 610 and the second channel layer 620 can be the same, for example, both including polysilicon. In other embodiments, the material of the first channel layer 610 can include silicon nitride, at which time a silicon nitride layer can be directly deposited by a deposition process (e.g., chemical vapor deposition process CVD or atomic layer deposition process ALD); or the sidewall of the gate dielectric layer 520 can be subjected to a nitridation process, for example, the sidewall of the gate dielectric layer 520 can be subjected to a plasma treatment by using ammonia (NH3) or nitrogen (N2), so as to be converted into a silicon nitride layer, for constituting the first channel layer 610. Alternatively, in other embodiments, the material of the first channel layer 610 can include a metal oxide layer, and the metal oxide layer can specifically be an aluminum oxide layer, at which time an aluminum oxide layer can be formed on the sidewall of the gate dielectric layer 520 by a deposition process, for constituting the first channel layer 610. The first channel layer 610 having a silicon nitride layer and / or a metal oxide layer can effectively improve the problem of oxidation of the gate conductive layer 510.

[0082] In this embodiment, referring to Figure 7As shown, after the deposition of the second channel material layer 620a, a second insulating structure 320 is formed in the via 500a. Specifically, after the second insulating structure 320 fills the via 500a, the second insulating structure 320 can be further etched back to reduce the height of the second insulating structure 320 in the via 500a, so that the subsequently formed second contact pad 220 can at least partially fill the via 500a.

[0083] In step S500, continuing to refer to Figure 8 As shown, the second contact pad 220 is formed on the top of the via 500a, and the second contact pad 220 is connected to the U-shaped channel layer 600.

[0084] The preparation method of the second contact pad 220 can include: first, depositing a conductive material layer serving as the second contact pad 220, which fills the via 500a and covers the top of the third insulating structure; then, removing the part of the conductive material layer that is higher than the via 500a, and using the remaining conductive material layer to form the second contact pad 220. In this embodiment, after removing the part of the conductive material layer that is higher than the via 500a, the part of the second channel material layer 620a that covers the third insulating structure is further removed, so that the finally formed second channel layer 620 is located in the via 500a.

[0085] After the second contact pad 220 is formed, a second conductive line 420 is further formed, for example, which can be referred to Figure 1 As shown, the second conductive line 420 is formed on the top of the second contact pad 220 and extends along the second direction, and the second contact pad 220 is electrically connected to the second conductive line 420. The second conductive line 420 includes a work function layer 422 and a metal layer 421 stacked from bottom to top, the material of the work function layer 422 includes titanium nitride (TiN) for example, and the material of the metal layer 421 includes tungsten (W) for example.

[0086] In the semiconductor structure provided in this embodiment, the U-shaped channel layer can form a conductive channel by using the gate conductive layer to control the U-shaped channel layer, so that the first contact pad and the second contact pad at the bottom and the top of the U-shaped channel layer can be mutually conductive through the conductive channel, realizing electrical signal transmission. The U-shaped channel layer has a first channel layer and a second channel layer, and the first channel layer can be used to cover the gate dielectric layer during the preparation of the gate dielectric layer, avoiding the gate dielectric layer from being subjected to etching bombardment to cause etching damage, improving the film quality of the gate dielectric layer, and further facilitating the improvement of the performance of the semiconductor structure formed thereby.

[0087] Based on the semiconductor structure concept described above, this invention also provides another technical solution, in which the semiconductor structure specifically includes: a substrate; a first contact pad and a channel structure formed on the substrate. The channel structure enables the transmission of electrical signals from the first contact pad in the vertical direction.

[0088] Can be combined Figure 1 As shown, the first contact pad 210 is formed on the substrate 100 and defined by a first insulating structure 310 on the substrate 100. A third insulating structure 330 is also formed on the substrate 100, located above the first contact pad 210 and the first insulating structure 310, and has a through-hole in the third insulating structure 330 that exposes the top of the first contact pad 210.

[0089] Furthermore, the channel structure includes a first channel layer 610 and a second channel layer 620. The first channel layer 610 is formed on the sidewall of the through-hole and defines the inner sidewall of the through-hole; therefore, the inner sidewall of the first channel layer 610 can be considered as constituting the inner sidewall of the through-hole. The second channel layer 620 is formed on the inner sidewall of the through-hole and contacts the top of the first contact pad 210, thereby achieving electrical connection with the first contact pad 210.

[0090] The first channel layer 610 and the second channel layer 620 may be made of the same material, such as polysilicon. Alternatively, the material of the first channel layer 610 may include silicon nitride and / or aluminum oxide; for example, the film layer at the sidewall of the via may be nitrided to form a silicon nitride layer to constitute the first channel layer 610; or, for example, an aluminum oxide layer may be formed at the sidewall of the via using a deposition process to constitute the first channel layer 610.

[0091] In this embodiment, the second channel layer 620 covers the inner sidewall and bottom of the through hole and defines an inner groove in the through hole. The inner groove defined by the second channel layer 620 is also filled with a second insulating structure 320. The second insulating structure 320 is located on the second channel layer 620 and correspondingly contacts the bottom and sidewall of the second channel layer 620.

[0092] Further, the semiconductor structure further comprises a second contact pad 220, which is disposed on the top of the via and connected to the second channel layer 620. That is, the second contact pad 220 and the first contact pad 210 are respectively located above and below the channel structure, and thus can be connected to each other through the channel structure, and specifically, the second channel layer 620 can be used to realize the up-down connection. In a specific example, the top position of the second insulating structure 320 is lower than the top position of the via, and at this time, the second channel layer 620 covers the part of the top of the via, that is, is exposed in the via, and the second contact pad 220 fills the via, thereby being electrically connected to the part of the second channel layer 620 exposed in the via, increasing the contact area between the second contact pad 220 and the second channel layer 620, and reducing the contact resistance.

[0093] In a specific example, the semiconductor structure further comprises a spacer dielectric layer 700, which is located above the first contact pad 210 and the first insulating structure 310, and is located below the third insulating structure 330, and the via extends from the third insulating structure 330 to the spacer dielectric layer 700 to expose the first contact pad 210, that is, the spacer dielectric layer 700 is formed with an opening at the position of the via to expose the first contact pad 210. In this embodiment, the first channel layer 610 is located above the spacer dielectric layer 700, and the inner sidewall of the first channel layer 610 is aligned with the sidewall of the opening corresponding to the spacer dielectric layer 700.

[0094] Similar to the above embodiment, the first wire 410 can also be disposed on the substrate 100, and the first wire 410 can be formed below the first contact pad 210 and extend along the first direction (for example, the first wire 410 extends along the direction perpendicular to the paper surface as shown), and the first contact pad 210 is electrically connected to the first wire 410. Figure 1 In a specific example, the first wire 410 comprises a metal layer and a work function layer which are stacked from bottom to top, and the material of the metal layer comprises tungsten (W) for example, and the material of the work function layer comprises titanium nitride (TiN) for example.

[0095] In a specific example, the semiconductor structure further comprises a second wire 420, which is formed above the second contact pad 220 and extends along a second direction, and the second contact pad 220 is electrically connected to the second wire 420. Specifically, the second wire 420 covers the top surface of the second contact pad 220 on its extension path. The second wire 420 comprises a work function layer 422 and a metal layer 421 which are stacked from bottom to top, and the material of the work function layer 422 comprises titanium nitride (TiN) for example, and the material of the metal layer 421 comprises tungsten (W) for example.

[0096] In an alternative embodiment, the semiconductor structure further comprises a gate dielectric layer 520 disposed on the outer sidewall of the first channel layer 610 facing away from the second channel layer 620. Further, a gate conductive layer 510 is disposed on the gate dielectric layer 520 facing away from the first channel layer 610.

[0097] It should be noted that, although the present application has been described with reference to the preferred embodiments above, the above embodiments are not used to limit the technical solutions of the present application. Any modification, equivalent replacement, and modification of the above embodiments, or any simple modification, equivalent replacement, and modification of the technical essence of the present application, without departing from the technical solutions of the present application, can be made by those skilled in the art. Therefore, any simple modification, equivalent replacement, and modification of the above embodiments, without departing from the technical solutions of the present application, according to the technical essence of the present application, are still within the scope of protection of the technical solutions of the present application.

[0098] In addition, it should be recognized that the terms described herein are used only to describe specific embodiments and not to limit the scope of the present application. It should be noted that the singular forms "a" and "an" and "the" used herein include plural references unless the context clearly indicates the opposite. For example, the reference to "a step" or "a device" means the reference to one or more steps or devices, and can include secondary steps and secondary devices. All conjunctions used should be interpreted in the broadest sense. In addition, the word "or" should be interpreted as having the definition of logical "or", not the definition of logical "exclusive or", unless the context clearly indicates the opposite.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A first contact pad and a first insulating structure are formed on the substrate, the first insulating structure surrounding the outer periphery of the first contact pad; A gate conductive layer is formed on the first insulating structure, and a vertical through hole is formed at the center of the gate conductive layer, the through hole being located above the first contact pad; A gate dielectric layer is disposed on the sidewall of the gate conductive layer exposed in the via. A U-shaped channel layer is formed in the via. The U-shaped channel layer includes a first channel layer and a second channel layer. The first channel layer is disposed on the sidewall of the gate dielectric layer exposed to the via. The material of the first channel layer includes silicon nitride and / or aluminum oxide. The second channel layer is disposed on the sidewall of the first channel layer and covers the first contact pad at the bottom of the via. as well as, A second contact pad is disposed on top of the through hole and connected to the U-shaped channel layer; A second conductor is formed above the second contact pad, and the second conductor directly contacts the top surface of the first channel layer, the second channel layer, and the second contact pad.

2. The semiconductor structure as described in claim 1, characterized in that, The material of the second channel layer includes polycrystalline silicon.

3. The semiconductor structure as described in claim 1, characterized in that, The materials of the first contact pad and the second contact pad include polycrystalline silicon of the second doping type.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a second insulating structure that fills the through-hole, and a second contact pad that is formed on the second insulating structure.

5. The semiconductor structure as described in claim 4, characterized in that, The top of the second insulating structure is lower than the top of the through hole, and the second contact pad fills the through hole.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a first wire formed below the first contact pad and extending along a first direction.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first contact pad and a first insulating structure are formed on the substrate, the first insulating structure surrounding the outer periphery of the first contact pad; A gate conductive layer is formed on the first insulating structure, and a vertical through hole is formed at the center of the gate conductive layer, the through hole being located above the first contact pad; A gate dielectric layer and a U-shaped channel layer are formed within the via. The gate dielectric layer covers the gate conductive layer and is exposed on the sidewall of the via. The U-shaped channel layer includes a first channel layer and a second channel layer. The first channel layer covers the gate dielectric layer. The material of the first channel layer includes silicon nitride and / or aluminum oxide. The second channel layer covers the first channel layer and a first contact pad at the bottom of the via. as well as, A second contact pad is formed at the top of the through hole, and the second contact pad connects to the U-shaped channel layer; A second conductor is formed above the second contact pad, and the second conductor directly contacts the top surface of the first channel layer, the second channel layer, and the second contact pad.

8. The method for preparing a semiconductor structure as described in claim 7, characterized in that, The method of forming the gate dielectric layer and the U-shaped channel layer includes: A dielectric material layer and a first channel material layer are deposited sequentially, the dielectric material layer and the first channel material layer covering the sidewalls and bottom of the via; An etching process is performed to remove the portion of the first channel material layer covering the bottom of the via, while retaining the portion of the first channel material layer covering the sidewall of the via to form the first channel layer; Continue etching the portion of the dielectric material layer that covers the bottom of the via and is exposed, while retaining the portion of the dielectric material layer that covers the sidewalls of the via to form the gate dielectric layer; and, A second channel layer is formed, which covers the first channel layer and the first contact pad at the bottom of the through hole.

9. The method for preparing a semiconductor structure as described in claim 7, characterized in that, After forming the U-shaped channel layer, the method further includes: forming a second insulating structure in the via and etching back the second insulating structure to reduce the height of the second insulating structure in the via; Furthermore, the second contact pad fills the through-hole and is formed on the second insulating structure.

10. The method for preparing the semiconductor structure according to claim 7, characterized in that, Prior to forming the first contact pad, the method further includes: forming a first wire on the substrate, and forming the first contact pad on the first wire.

11. A semiconductor structure, characterized in that, include: Substrate; A first contact pad is formed on the substrate and defined by a first insulating structure on the substrate; A third insulating structure is formed on the substrate and located above the first contact pad and the first insulating structure, and the third insulating structure also has a through hole that exposes the top of the first contact pad; A first channel layer is formed at the sidewall position of the through hole and defines the inner sidewall of the through hole. The material of the first channel layer includes silicon nitride and / or aluminum oxide. A second channel layer is formed on the inner wall of the through hole and contacts the top of the first contact pad; A second insulating structure is filled in the through hole and is located on the second channel layer and in contact with the bottom and sidewalls of the second channel layer; as well as, A gate dielectric layer is located on the outer wall of the first channel layer away from the second channel layer; The second contact pad is disposed on top of the through hole and connects to the second channel layer; A second conductor is formed above the second contact pad, and the second conductor directly contacts the top surface of the first channel layer, the second channel layer, and the second contact pad.

12. The semiconductor structure as claimed in claim 11, characterized in that, It also includes a spacer layer located above the first contact pad and the first insulating structure, and below the third insulating structure, wherein the through-hole extends downward from the third insulating structure into the spacer layer to expose the first contact pad.

13. The semiconductor structure as described in claim 11, characterized in that, It also includes a gate conductive layer, which is formed on the sidewall of the gate dielectric layer away from the first channel layer.

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