A level shifting circuit and related electronic device

Abstract

This application provides a level shifting circuit and related electronic equipment. The circuit includes: a differential signal module, a voltage withstand module, a reset module, and a signal latch module. The first output terminal of the differential signal module is connected to the first input terminal of the voltage withstand module, and the second output terminal of the differential signal module is connected to the second input terminal of the voltage withstand module. The third input terminal of the voltage withstand module is connected to the first output terminal of the signal latch module, and the fourth input terminal of the voltage withstand module is connected to the second output terminal of the signal latch module. The first output terminal of the voltage withstand module is connected to the first input terminal of the signal latch module, and the second output terminal of the voltage withstand module is connected to the second input terminal of the signal latch module. The output terminal of the reset module is connected to the third and fourth input terminals of the signal latch module. The second output terminal of the signal latch module is the output terminal of the level shifting circuit. This application is capable of transmitting signals between two different voltage domains.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a level shifting circuit and related electronic equipment. Background Technology

[0002] In integrated circuits, it is common for a single IC to contain multiple voltage domains. For example, some logic circuits may operate with VCC1 = 5V and VSS1 = 0V, while other logic circuits may operate with VCC2 = 25V and VSS2 = 20V. Communication is required between logic circuits operating at different voltage levels, which necessitates level shifting circuits to transmit signals between these different voltage levels. Summary of the Invention

[0003] This application provides a level shifting circuit and related electronic equipment that can solve the problem of signals not being able to be transmitted between two different voltage domains.

[0004] In a first aspect, embodiments of this application provide a level shifting circuit, including: a differential signal module, a voltage withstand module, a reset module, and a signal latch module; the input terminal of the differential signal module is the input terminal of the level shifting circuit, the first output terminal of the differential signal module is connected to the first input terminal of the voltage withstand module, and the second output terminal of the differential signal module is connected to the second input terminal of the voltage withstand module; the third input terminal of the voltage withstand module is connected to the first output terminal of the signal latch module, the fourth input terminal of the voltage withstand module is connected to the second output terminal of the signal latch module, the first output terminal of the voltage withstand module is connected to the first input terminal of the signal latch module, and the second output terminal of the voltage withstand module is connected to the second input terminal of the signal latch module; the output terminal of the reset module is connected to the third and fourth input terminals of the signal latch module; the second output terminal of the signal latch module is the input terminal of the level shifting circuit. The output terminal of the level shifting circuit; the differential signal module, used to convert the input signal into a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal are a pair of differential-mode signals; the withstand voltage module, used to convert the first differential signal into a first withstand voltage signal through a first control signal of the signal latch module, and to convert the second differential signal into a second withstand voltage signal through a second control signal of the signal latch module; the reset module, used to generate a reset signal and output the reset signal to the signal latch module, the reset signal being used to control the reset state of the signal latch module during power-on or reset; the signal latch module, used to convert the first withstand voltage signal, the second withstand voltage signal and the reset signal into a first control signal and a second control signal, the second control signal being the output signal of the level shifting circuit.

[0005] Optionally, the reset module includes: a first resistor R1 and a first capacitor C1, a first end of the first resistor R1 is connected to a first power supply, a second end of the first resistor R1 is connected to a first end of the first capacitor C1, a second end of the first capacitor C1 is connected to a second power supply, and the second end of the first resistor R1 is the output terminal of the reset module.

[0006] Optionally, the differential signal module includes: a first inverting module and a second inverting module; the input terminal of the first inverting module is the input terminal of the differential signal module; the output terminal of the first inverting module is connected to the input terminal of the second inverting module and the first output terminal of the differential signal module; the output terminal of the second inverting module is connected to the second output terminal of the differential signal module.

[0007] Optionally, the first inverting module includes: a first switch M1 and a second switch M2; the source of the first switch M1 is connected to a third power supply; the gate of the first switch M1 is connected to the gate of the second switch M2 and the input terminal of the first inverting module; the drain of the first switch M1 is connected to the source of the second switch M2 and the output terminal of the first inverting module; and the drain of the second switch M2 is connected to a fourth power supply.

[0008] Optionally, the second inverting module includes: a third switch M3 and a fourth switch M4; the source of the third switch M3 is connected to a third power supply; the gate of the third switch M3 is connected to the gate of the fourth switch M4 and the input terminal of the second inverting module; the drain of the third switch M3 is connected to the source of the fourth switch M4 and the output terminal of the second inverting module; and the drain of the fourth switch M4 is connected to a fourth power supply.

[0009] Optionally, the withstand voltage module includes a second capacitor C2, a third capacitor C3, a fifth switching transistor M5, and a sixth switching transistor M6; the first end of the second capacitor C2 is connected to the first output terminal of the differential signal module, the second end of the second capacitor C2 is connected to the drain of the fifth switching transistor M5, the source of the fifth switching transistor M5 is connected to the first power supply, and the gate of the fifth switching transistor M5 is connected to the fourth input terminal of the withstand voltage module; the first end of the third capacitor C3 is connected to the second output terminal of the differential signal module, the second end of the third capacitor C3 is connected to the drain of the sixth switching transistor M6, the source of the sixth switching transistor M6 is connected to the first power supply, and the gate of the sixth switching transistor M6 is connected to the third input terminal of the withstand voltage module; the second end of the second capacitor C2 is connected to a first high-level point and the first output terminal of the withstand voltage module; the second end of the third capacitor C3 is connected to a second high-level point and the second output terminal of the withstand voltage module.

[0010] Optionally, the withstand voltage module further includes a first clamping diode D1 and a second clamping diode D2; the anode of the first clamping diode D1 is connected to the second power supply, and the cathode of the first clamping diode D1 is connected to the first high-level point; the anode of the second clamping diode D2 is connected to the second power supply, and the cathode of the first clamping diode D1 is connected to the second high-level point.

[0011] Optionally, the signal latch module includes a latch control module and an RS latch module; the first output terminal of the latch control module is connected to the first input terminal of the RS latch module, the second output terminal of the latch control module is connected to the second input terminal of the RS latch module, the first input terminal of the latch control module is the first input terminal of the signal latch module, the second input terminal of the latch control module is the second input terminal of the signal latch module, the third input terminal of the latch control module is the third input terminal of the signal latch module, the fourth input terminal of the latch control module is the fourth input terminal of the signal latch module, the first output terminal of the RS latch module is the first output terminal of the signal latch module, and the second output terminal of the RS latch module is the second output terminal of the signal latch module.

[0012] Optionally, the latch control module includes: inverter A1, inverter A2, inverter A3, AND gate AN1, and OR gate OR1; the input terminal of inverter A1 is connected to the first input terminal of the latch control module, the output terminal of inverter A1 is connected to the first input terminal of AND gate AN1, the second input terminal of AND gate AN1 is connected to the third input terminal of the latch control module, the output terminal of AND gate AN1 is connected to the first input terminal of the RS latch module, the input terminal of inverter A2 is connected to the second input terminal of the latch control module, the output terminal of inverter A2 is connected to the first input terminal of OR gate OR1, the second input terminal of OR gate OR1 is connected to the output terminal of inverter A3, the input terminal of inverter A3 is connected to the fourth input terminal of the latch control module, and the output terminal of OR gate OR1 is connected to the second output terminal of the latch control module.

[0013] Secondly, this application also provides an electronic device, which includes the level shifting circuit as described in the first aspect above.

[0014] This application provides a level shifting circuit and electronic device. The circuit includes a differential signal module, a voltage withstand module, a reset module, and a signal latch module. The input terminal of the differential signal module is the input terminal of the level shifting circuit. The first output terminal of the differential signal module is connected to the first input terminal of the voltage withstand module, and the second output terminal of the differential signal module is connected to the second input terminal of the voltage withstand module. The third input terminal of the voltage withstand module is connected to the first output terminal of the signal latch module, and the fourth input terminal of the voltage withstand module is connected to the second output terminal of the signal latch module. The first output terminal of the voltage withstand module is connected to the first input terminal of the signal latch module, and the second output terminal of the voltage withstand module is connected to the second input terminal of the signal latch module. The output terminal of the reset module is connected to the third and fourth input terminals of the signal latch module. The second output terminal of the signal latch module is the output terminal of the level shifting circuit. This application can transmit signals between two different voltage domains, realizing signal level conversion from a low-level signal at the signal input terminal to a high-level signal output by the signal latch module. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of a commonly used level conversion circuit provided in the embodiments of this application;

[0017] Figure 2A This is a schematic diagram of the module structure of one embodiment of the level shifting circuit of this application;

[0018] Figure 2B A circuit diagram of a reset module 130 provided in an embodiment of this application;

[0019] Figure 2C A circuit diagram of a differential signal module 110 provided for an embodiment of this application;

[0020] Figure 2D A circuit diagram of a withstand voltage module 120 provided in an embodiment of this application;

[0021] Figure 2E A circuit diagram of a withstand voltage module 120 provided in an embodiment of this application;

[0022] Figure 2F A circuit diagram of a signal latch module 140 provided in an embodiment of this application;

[0023] Figure 3This is a schematic diagram of another embodiment of the level shifting circuit of this application. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0025] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, system, product, or apparatus that comprises a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, products, or apparatuses.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] In integrated circuits, it is common for a single IC to contain multiple voltage domains. For example, some logic circuits may operate with VCC1 = 5V and VSS1 = 0V, while other logic circuits may operate with VCC2 = 25V and VSS2 = 20V. Communication is required between logic circuits operating at different voltage levels, which necessitates level shifting circuits to transmit signals between these different voltage levels.

[0028] To better illustrate the embodiments of this application, a level conversion circuit in the prior art will first be described. For example... Figure 1 As shown, Figure 1This is a schematic diagram of a commonly used level conversion circuit provided in an embodiment of this application. This circuit can use a level shifting circuit to transmit signals between different levels. When the level of the signal at point A is VCC1, the inverter composed of M11 and M22 turns off M33, and R11 pulls up the potentials of S and K to VCC2. At this time, the inverter composed of M55 and M66 outputs the signal at point B as VSS2. When the level of the signal at point A is VSS1, the inverter composed of M11 and M22 turns on M33, and M33 pulls down the potential of S to VSS1. The potential of K is limited by M44 to VSS2 + threshold voltage (VTH). At this time, the inverter composed of M55 and M66 converts the signal at point B to VCC2. Thus, this circuit realizes the level conversion (inversion) from point A level VCC1~VSS1 to point B level VCC2~VSS2.

[0029] However, in this circuit, when the voltage level at point A is VSS1, M33 is turned on, resulting in normally-on power consumption. In addition, the voltage range at point S is from VSS1 to VCC2. Since VCC1 = 5V, VSS1 = 0V, VCC2 = 30V, and VSS2 = 25V, the |VDS| withstand voltage of M33 and M44 must be greater than VCC2 - VSS1 = 30V. However, the VDS withstand voltage of ordinary transistors is usually 5V, so high-voltage transistors need to be selected, which increases the complexity and cost of device manufacturing.

[0030] To address the aforementioned problems, this application provides a level shifting circuit 100. (Refer to...) Figure 2A , Figure 2A This is a schematic diagram of a circuit module structure for a level shifting circuit 100 provided in an embodiment of this application. Figure 2A As shown, the above level shifting circuit includes: a differential signal module 110, a withstand voltage module 120, a reset module 130, and a signal latch module 140;

[0031] The input terminal of the differential signal module 110 is the input terminal of the level shifting circuit 100. The first output terminal of the differential signal module 110 is connected to the first input terminal of the withstand voltage module 120, and the second output terminal of the differential signal module 110 is connected to the second input terminal of the withstand voltage module 120.

[0032] The third input terminal of the withstand voltage module 120 is connected to the first output terminal of the signal latch module 140, the fourth input terminal of the withstand voltage module 120 is connected to the second output terminal of the signal latch module 140, the first output terminal of the withstand voltage module 120 is connected to the first input terminal of the signal latch module 140, and the second output terminal of the withstand voltage module 120 is connected to the second input terminal of the signal latch module 140.

[0033] The output of the reset module 130 is connected to the third and fourth inputs of the signal latch module 140;

[0034] The second output terminal of the signal latch module 140 is the output terminal of the level shifting circuit 100.

[0035] It needs to be further explained that the differential signal module 110 is used to convert the input signal into a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal are a pair of differential mode signals.

[0036] It needs to be further explained that the withstand voltage module 120 is used to convert the first differential signal into a first withstand voltage signal through the first control signal of the signal latch module 140, and to convert the second differential signal into a second withstand voltage signal through the second control signal of the signal latch module 140.

[0037] It needs to be further explained that the reset module 130 is used to generate a reset signal and output a reset signal to the signal latch module 140. The reset signal is used to control the reset state of the signal latch module 140 during power-on or reset.

[0038] It needs to be further explained that the signal latch module 140 is used to convert the first withstand voltage signal, the second withstand voltage signal and the reset signal into a first control signal and a second control signal, and the second control signal is the output signal of the level shifting circuit 100.

[0039] As can be seen, the level shifting circuit 100 described above realizes the signal level conversion from the low-level signal at signal input terminal A to the high-level signal output by the signal latching module 140, enabling the transmission of signals between two different voltage domains. The voltage withstand module 120 solves the voltage withstand problem of the switching transistor in the differential signal module 110, allowing the level shifting circuit 100 to achieve signal level shifting without the need for a high-voltage transistor.

[0040] In one possible example, refer to Figure 2B , Figure 2B The present invention provides a circuit diagram of a reset module 130, which includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is connected to a first power supply, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to a second power supply, and the second end of the first resistor R1 is the output terminal of the reset module 130.

[0041] In this embodiment, the first power supply is VCC2, which is a DC power supply corresponding to a preset voltage value; the second power supply is VSS2, which is a DC power supply corresponding to a preset voltage value.

[0042] The reset module 130 can also be other types of reset circuits. This is just an example, and there are no restrictions on the circuit of the reset module 130.

[0043] The resistance value of the first resistor R1 can be a preset resistance value determined based on experience, or it can be a resistance value obtained through calculation.

[0044] The output terminal of the reset module 130 outputs a reset signal to the signal latch module 140.

[0045] In one possible example, refer to Figure 2C , Figure 2C This is a circuit diagram of a differential signal module 110 provided in an embodiment of this application. The differential signal module 110 includes: a first inverting module 111 and a second inverting module 112; the input terminal of the first inverting module 111 is the input terminal of the differential signal module 110; the output terminal of the first inverting module 111 is connected to the input terminal of the second inverting module 112 and the first output terminal of the differential signal module 110; the output terminal of the second inverting module 112 is connected to the second output terminal of the differential signal module 110.

[0046] In one possible example, the first inverting module 111 includes: a first switching transistor M1 and a second switching transistor M2; the source of the first switching transistor M1 is connected to a third power supply; the gate of the first switching transistor M1 is connected to the gate of the second switching transistor M2 and the input terminal of the first inverting module 111; the drain of the first switching transistor M1 is connected to the source of the second switching transistor M2 and the output terminal of the first inverting module 111; and the drain of the second switching transistor M2 is connected to a fourth power supply.

[0047] The third power supply is VCC1, and the fourth power supply is VSS1. The first switching transistor M1 can be a junction field-effect transistor (JFET), an insulated field-effect transistor (IFET), or other switching transistors; no further restrictions are imposed here. The second switching transistor M2 can be a JFET, an IFET, or other switching transistors; no further restrictions are imposed here.

[0048] In one possible example, the second inverting module 112 includes: a third switch M3 and a fourth switch M4; the source of the third switch M3 is connected to a third power supply; the gate of the third switch M3 is connected to the gate of the fourth switch M4 and the input terminal of the second inverting module 112; the drain of the third switch M3 is connected to the source of the fourth switch M4 and the output terminal of the second inverting module 112; and the drain of the fourth switch M4 is connected to a fourth power supply.

[0049] The third power supply is VCC1, which is a DC power supply corresponding to a preset voltage value. The fourth power supply is VSS1, which is a DC power supply corresponding to a preset voltage value.

[0050] The third switch M3 can be a junction field-effect transistor (JFET), an insulated field-effect transistor (IFET), or other types of switch transistors; no further restrictions are imposed here. The fourth switch M4 can be a JFET, an IFET, or other types of switch transistors; no further restrictions are imposed here.

[0051] In one possible example, refer to Figure 2D , Figure 2D This is a circuit diagram of a voltage-resistant module 120 provided in an embodiment of this application. The voltage-resistant module 120 includes a second capacitor C2, a third capacitor C3, a fifth switch M5, and a sixth switch M6. The first end of the second capacitor C2 is connected to the first output terminal of the differential signal module 110, the second end of the second capacitor C2 is connected to the drain of the fifth switch M5, the source of the fifth switch M5 is connected to the first power supply, and the gate of the fifth switch M5 is connected to the fourth input terminal of the voltage-resistant module 120. The first end of the third capacitor C3 is connected to the second output terminal of the differential signal module 110, the second end of the third capacitor C3 is connected to the drain of the sixth switch M6, the source of the sixth switch M6 is connected to the first power supply, and the gate of the sixth switch M6 is connected to the third input terminal of the voltage-resistant module 120. The second end of the second capacitor C2 is connected to a first high-level point and the first output terminal of the voltage-resistant module. The second end of the third capacitor C3 is connected to a second high-level point and the second output terminal of the voltage-resistant module.

[0052] In this embodiment, the fifth switch M5 can be a junction field-effect transistor, an insulated field-effect transistor, or other switch transistors, without further restrictions. The sixth switch M6 in this embodiment can be a junction field-effect transistor, an insulated field-effect transistor, or other switch transistors, without further restrictions.

[0053] The first high-level point is Figure 2D The Q point in the middle, the second high level point is Figure 2D Point P in the diagram.

[0054] In one possible example, refer to Figure 2E , Figure 2E The circuit diagram of a withstand voltage module 120 provided in this application embodiment is shown. The withstand voltage module 120 further includes a first clamping diode D1 and a second clamping diode D2. The anode of the first clamping diode D1 is connected to a second power supply, and the cathode of the first clamping diode D1 is connected to a first high-level point. The anode of the second clamping diode D2 is connected to the second power supply, and the cathode of the first clamping diode D1 is connected to a second high-level point.

[0055] In this example, the second power supply is VSS2, which is a DC power supply corresponding to a preset voltage value. A clamping diode is a diode used to limit the potential at a certain point in a circuit. In this example, a clamping diode is used to protect the second power supply VSS2.

[0056] In one possible example, refer to Figure 2F , Figure 2F This is a circuit diagram of a signal latch module 140 provided in an embodiment of this application. The signal latch module 140 includes a latch control module 141 and an RS latch module 142. The first output terminal of the latch control module 141 is connected to the first input terminal of the RS latch module 142, and the second output terminal of the latch control module 141 is connected to the second input terminal of the RS latch module 142. The first input terminal of the latch control module 141 is the first input terminal of the signal latch module 140, the second input terminal of the latch control module 141 is the second input terminal of the signal latch module 140, the third input terminal of the latch control module 141 is the third input terminal of the signal latch module 140, the fourth input terminal of the latch control module 141 is the fourth input terminal of the signal latch module 140, the first output terminal of the RS latch module 142 is the first output terminal of the signal latch module 140, and the second output terminal of the RS latch module 142 is the second output terminal of the signal latch module 140.

[0057] The RS latch module 142 can be an RS latch composed of NAND gates ND1 and ND2, or an RS latch composed of two NOR gates, or other types of RS latches. This is just an example, and no restrictions are placed on the RS latch.

[0058] In one possible example, the latch control module 141 includes: a first inverter A1, a second inverter A2, a third inverter A3, an AND gate AN1, and an OR gate OR1; the input terminal of the first inverter A1 is connected to the first input terminal of the latch control module 141, the output terminal of the first inverter A1 is connected to the first input terminal of the AND gate AN1, the second input terminal of the AND gate AN1 is connected to the third input terminal of the latch control module 141, the output terminal of the AND gate AN1 is connected to the first input terminal of the RS latch module, the input terminal of the second inverter A2 is connected to the second input terminal of the latch control module 141, the output terminal of the second inverter A2 is connected to the first input terminal of the OR gate OR1, the second input terminal of the OR gate OR1 is connected to the output terminal of the third inverter A3, the input terminal of the third inverter A3 is connected to the fourth input terminal of the latch control module 141, and the output terminal of the OR gate OR1 is connected to the second output terminal of the latch control module 141.

[0059] In this application, the first inverter A1, the second inverter A2, and the third inverter A3 involved in the embodiments can all be NOT gates or other inverters, and no further restrictions are imposed here.

[0060] The working principle of the level shifting circuit in this application is as follows:

[0061] Reference Figure 3 , Figure 3 This is a circuit diagram of a level shifting circuit 100 provided in an embodiment of this application. Figure 3 The first inverter A1, the second inverter A2, the third inverter A3, the AND gate AN1, the OR gate OR1, the NAND gate ND1, and the NAND gate ND2 all operate within the voltage range between VCC2 and VSS2. The power supply signals of VCC1, VSS1, VCC2, and VSS2 are represented as Vc1, Vs1, Vc2, and Vs2, respectively.

[0062] The high level of the signal at input terminal A of level shift circuit 100 is VCC1, and the low level is VSS1; the high level of the signal at output terminal A of level shift circuit 100 is VCC2, and the low level is VSS2.

[0063] The first inverting module, consisting of M1 and M2, converts the input signal at point A into a first differential signal; the second inverting module, consisting of M3 and M4, converts the input signal at point A into a second differential signal.

[0064] C2 transmits the first differential signal output from the first output terminal of the differential signal module to the second terminal of C2 in the withstand voltage module; C3 transmits the second differential signal output from the second output terminal of the differential signal module to the second terminal of C3 in the withstand voltage module. C2 and C3 are withstand voltage devices.

[0065] R1 and C1 form a reset device that outputs a reset signal RST, which is 0 when powered on, ensuring that the system's default value is correct when powered on.

[0066] M5 and M6 are two transistors with high on-resistance, and their function is to maintain the voltage across capacitors C1 and C2.

[0067] D1 and D2 are both clamping diodes, which can prevent the voltage at points Q and P from being too low and exceeding the operating range of subsequent devices. A1, A2, AN1, OR1, ND1, and ND2 together constitute a signal latch module with a reset terminal (i.e., an RS latch) (the reset terminal is the output terminal RST of the reset module, R is the Q point, and S is the P point), which converts the differential signal transmitted from C1 and C2 into a single-ended signal at point B and latches it.

[0068] Assume that upon power-up, the input signal at point A of the level shift circuit 100 is Vs1 by default. The reset module (i.e., the reset circuit) composed of R1 and C1 briefly sets the output RST of the reset module to Vs2. Then, AN1 and OR1 make the level signal at the second output B of the RS latch composed of ND1 and ND2 Vs2. At the same time, the fifth switch M5 is turned on, and the sixth switch M6 is turned off. The first high-level point Q is Vc2, and the first output S of the differential signal module 110 is Vc1; the second high-level point P is Vs2, and the first high-level point Q is Vs1.

[0069] Once power-on is complete, R1 charges C1, and the output voltage of the reset module, RST, is Vc2. AN1 and OR1 no longer affect the RS latch formed by ND1 and ND2.

[0070] When the voltage at input point A of the level shift circuit 100 changes from Vs1 to Vc1, the first inverting module composed of M1 and M2 causes the voltage at the first output point S of the differential signal module 110 to change from Vc1 to Vs1. Since the voltage across the third capacitor C3 cannot change abruptly, and the on-resistance of the fifth switch M5 is designed to be sufficiently large, it cannot affect the voltage at the first high-level point Q during the transition. Therefore, the voltage at the first high-level point Q changes from Vc2 to Vs2. Simultaneously, the second inverting module composed of the third switch M3 and the fourth switch M4 causes the voltage at the second output point K of the differential signal module 110 to change from Vs1 to Vc1. Since the voltage across the third capacitor C3 cannot change abruptly, the voltage at the second high-level point P changes from Vs2 to Vc2.

[0071] The RSlatch, consisting of A1, A2, AN1, OR1, ND1, and ND2, flips the signal output point B to Vc2. At the same time, the fifth switch M5 is turned off, and the sixth switch M6 is turned on.

[0072] When the signal input point A changes from Vc1 to Vs1, the first inverter composed of M1 and M2 causes the voltage at the first output point S of the differential signal module 110 to change from Vs1 to Vc1. Since the voltage across the second capacitor C2 cannot change abruptly, the voltage at the first high-level point Q changes from Vs2 to Vc2. Simultaneously, the second inverter composed of M3 and M4 causes the voltage at the second output point K of the differential signal module 110 to change from Vs1 to Vc1. Because the voltage across the third capacitor C3 cannot change abruptly, and the on-resistance of the sixth switch M6 is designed to be sufficiently large, it cannot affect the voltage at point K during the transformation process. Therefore, the voltage at the second high-level point P changes from Vc2 to Vs2. The signal latch module 140, which consists of the first inverter A1, the second inverter A2, the third inverter A3, the AND gate AN1, the OR gate OR1, the NAND gate ND1, and the NAND gate ND2, flips the second output terminal B of the signal latch module 140 to Vs2. At the same time, the sixth switch M6 is turned off and the fifth switch M5 is turned on.

[0073] The above process achieves the signal level conversion from voltage Vc1 to Vs1 at point A to Vc2 to Vs2 at point B. By using high-voltage capacitors C2 and C3 in the level shifting circuit, high-voltage transistors are not required, saving manufacturing costs and complexity, and reducing the normally-on power consumption of the switching transistor during conduction.

[0074] Secondly, this application also provides an electronic device, which includes the level shifting circuit described above.

[0075] This embodiment of the application receives input signals by connecting a signal inverting module to the signal input terminal, thereby transmitting the electrical signals from the first low-level terminal and the second low-level terminal to the first high-level point and the second high-level point through the withstand voltage module. Then, the signal latching module outputs the first high-level signal or the second high-level signal under the action of the reset terminal. The first high-level signal corresponds to the first high-level point, and the second high-level signal corresponds to the second high-level point. This realizes the signal level conversion from the low-level signal at the signal input terminal A to the high-level signal at the signal output terminal B, and enables the transmission of signals between two different voltage domains.

[0076] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A level shifting circuit, characterized in that, The circuit includes: a differential signal circuit, a withstand voltage circuit, a reset circuit, and a signal latch circuit; The input terminal of the differential signal circuit is the input terminal of the level shifting circuit. The first output terminal of the differential signal circuit is connected to the first input terminal of the withstand voltage circuit, and the second output terminal of the differential signal circuit is connected to the second input terminal of the withstand voltage circuit. The differential signal circuit includes a switching transistor. The third input terminal of the withstand voltage circuit is connected to the first output terminal of the signal latch circuit, the fourth input terminal of the withstand voltage circuit is connected to the second output terminal of the signal latch circuit, the first output terminal of the withstand voltage circuit is connected to the first input terminal of the signal latch circuit, and the second output terminal of the withstand voltage circuit is connected to the second input terminal of the signal latch circuit; the output terminal of the reset circuit is connected to the third and fourth input terminals of the signal latch circuit. The second output terminal of the signal latching circuit is the output terminal of the level shifting circuit; The differential signal circuit is used to convert the input signal into a first differential signal and a second differential signal, wherein the first differential signal and the second differential signal are a pair of differential-mode signals; The withstand voltage circuit is used to convert the first differential signal into a first withstand voltage signal through a first control signal of the signal latch circuit, and to convert the second differential signal into a second withstand voltage signal through a second control signal of the signal latch circuit. The reset circuit is used to generate a reset signal and output the reset signal to the signal latch circuit, wherein the reset signal is used to control the reset state of the signal latch circuit during power-on or reset. The signal latching circuit is used to convert the first withstand voltage signal, the second withstand voltage signal and the reset signal into the first control signal and the second control signal, wherein the second control signal is the output signal of the level shifting circuit.

2. The level shifting circuit as described in claim 1, characterized in that, The reset circuit includes a first resistor R1 and a first capacitor C1. The first end of the first resistor R1 is connected to a first power supply, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to a second power supply, and the second end of the first resistor R1 is the output terminal of the reset circuit.

3. The level shifting circuit as described in claim 1, characterized in that, The differential signal circuit includes: a first inverting circuit and a second inverting circuit; The input terminal of the first inverting circuit is the input terminal of the differential signal circuit; The output terminal of the first inverting circuit is connected to the input terminal of the second inverting circuit and the first output terminal of the differential signal circuit; The output terminal of the second inverting circuit is connected to the second output terminal of the differential signal circuit.

4. The level shifting circuit as described in claim 3, characterized in that, The first inverting circuit includes: a first switching transistor M1 and a second switching transistor M2; The source of the first switching transistor M1 is connected to a third power supply; The gate of the first switching transistor M1 is connected to the gate of the second switching transistor M2 and the input terminal of the first inverting circuit; The drain of the first switching transistor M1 is connected to the source of the second switching transistor M2 and the output terminal of the first inverting circuit; The drain of the second switching transistor M2 is connected to the fourth power supply.

5. The level shifting circuit as described in claim 3, characterized in that, The second inverting circuit includes: a third switch M3 and a fourth switch M4; The source of the third switch M3 is connected to the third power supply; The gate of the third switch M3 is connected to the gate of the fourth switch M4 and the input terminal of the second inverting circuit. The drain of the third switch M3 is connected to the source of the fourth switch M4 and the output terminal of the second inverting circuit. The drain of the fourth switching transistor M4 is connected to the fourth power supply.

6. The level shifting circuit as described in any one of claims 1 to 5, characterized in that, The withstand voltage circuit includes a second capacitor C2, a third capacitor C3, a fifth switch M5, and a sixth switch M6; The first end of the second capacitor C2 is connected to the first output terminal of the differential signal circuit, the second end of the second capacitor C2 is connected to the drain of the fifth switching transistor M5, the source of the fifth switching transistor M5 is connected to the first power supply, and the gate of the fifth switching transistor M5 is connected to the fourth input terminal of the withstand voltage circuit. The first end of the third capacitor C3 is connected to the second output terminal of the differential signal circuit, the second end of the third capacitor C3 is connected to the drain of the sixth switch M6, the source of the sixth switch M6 is connected to the first power supply, and the gate of the sixth switch M6 is connected to the third input terminal of the withstand voltage circuit. The second terminal of the second capacitor C2 is connected to the first high-level point and the first output terminal of the withstand voltage circuit; The second terminal of the third capacitor C3 is connected to the second high-level point and the second output terminal of the withstand voltage circuit.

7. The level shifting circuit as described in claim 6, characterized in that, The withstand voltage circuit also includes a first clamping diode D1 and a second clamping diode D2; The anode of the first clamping diode D1 is connected to the second power supply, and the cathode of the first clamping diode D1 is connected to the first high-level point. The anode of the second clamping diode D2 is connected to the second power supply, and the cathode of the second clamping diode D2 is connected to the second high-level point.

8. The level shifting circuit as described in claim 5, characterized in that, The signal latching circuit includes a latching control circuit and an RS latching circuit; The first output terminal of the latch control circuit is connected to the first input terminal of the RS latch circuit. The second output terminal of the latch control circuit is connected to the second input terminal of the RS latch circuit. The first input terminal of the latch control circuit is the first input terminal of the signal latch circuit. The second input terminal of the latch control circuit is the second input terminal of the signal latch circuit. The third input terminal of the latch control circuit is the third input terminal of the signal latch circuit. The fourth input terminal of the latch control circuit is the fourth input terminal of the signal latch circuit. The first output terminal of the RS latch circuit is the first output terminal of the signal latch circuit. The second output terminal of the RS latch circuit is the second output terminal of the signal latch circuit.

9. The level shifting circuit as described in claim 8, characterized in that, The latch control circuit includes: a first inverter A1, a second inverter A2, a third inverter A3, an AND gate AN1, and an OR gate OR1; The input terminal of the first inverter A1 is connected to the first input terminal of the latch control circuit. The output of the first inverter A1 is connected to the first input of the AND gate AN1. The second input terminal of the AND gate AN1 is connected to the third input terminal of the latch control circuit. The output of AND gate AN1 is connected to the first input of the RS latch circuit. The input terminal of the second inverter A2 is connected to the second input terminal of the latch control circuit. The output of the second inverter A2 is connected to the first input of the OR gate OR1. The second input terminal of the OR gate OR1 is connected to the output terminal of the third inverter A3. The input terminal of the third inverter A3 is connected to the fourth input terminal of the latch control circuit. The output terminal of the third inverter A3 is connected to the second input terminal of the RS latch circuit. The output of the OR gate OR1 is connected to the second output of the latch control circuit.

10. An electronic device, characterized in that, The electronic device includes a level shifting circuit as described in any one of claims 1-9.

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