Semiconductor devices, their fabrication methods and semiconductor memory devices

Abstract

This disclosure discloses a semiconductor device, its fabrication method, and a semiconductor memory device, including: a semiconductor substrate, a plurality of word line trenches, and a word line structure; the word line trenches include a first word line trench and a second word line trench; the orthographic projection of the first word line trench onto the semiconductor substrate is located within the orthographic projection of the shallow channel isolation region onto the semiconductor substrate; the orthographic projection of the second word line trench onto the semiconductor substrate is located within the orthographic projection of the active region onto the semiconductor substrate; the word line structure includes a first word line structure portion and a second word line structure portion connected to each other; the first word line structure portion is formed in the first word line trench, and the second word line structure portion is formed in the second word line trench; wherein, the first word line structure portion has a clearance region, the top surface of the clearance region is flush with the top surface of the second word line structure portion, and the clearance region has an insulating material.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices, methods for their fabrication, and semiconductor memory devices. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, composed of many repeating semiconductor devices. Each semiconductor device typically includes a capacitor and a transistor; the transistor's gate is connected to the word line structure, its drain to the bit line, and its source to the capacitor; the voltage signal on the word line structure can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line. However, interference between word lines can affect the performance and reliability of the semiconductor device. Summary of the Invention

[0003] According to some embodiments, a first aspect of this disclosure provides a semiconductor device, including:

[0004] A semiconductor substrate includes: a shallow trench isolation region, and a plurality of spaced active regions defined by the shallow trench isolation region;

[0005] Multiple word line trenches are formed in the semiconductor substrate, and the word line trenches intersect with corresponding active regions; wherein, the word line trenches include a first word line trench and a second word line trench; the orthographic projection of the first word line trench on the semiconductor substrate is located within the orthographic projection of the shallow trench isolation region on the semiconductor substrate; the orthographic projection of the second word line trench on the semiconductor substrate is located within the orthographic projection of the active region on the semiconductor substrate;

[0006] A character line structure is embedded in the character line groove; wherein, the character line structure includes a first character line structure portion and a second character line structure portion connected to each other; the first character line structure portion is formed in the first character line groove, and the second character line structure portion is formed in the second character line groove;

[0007] The first character line structure has a clearance area, the top surface of which is flush with the top surface of the second character line structure, and the clearance area contains an insulating material.

[0008] In some possible embodiments, the second character line structure is a solid structure; and in the extension direction perpendicular to the character line structure, the cross-section of the first character line structure has a recessed area.

[0009] The avoidance area includes the recessed area.

[0010] In some possible embodiments, the top surface of the recessed region is flush with the top surface of the second word line structure in a direction perpendicular to the semiconductor substrate;

[0011] Furthermore, in a direction perpendicular to the semiconductor substrate, the bottom surface of the recessed region is higher than the bottom surface of the second word line structure portion, and the bottom surface of the first word line structure portion is lower than the bottom surface of the second word line structure portion.

[0012] In some possible embodiments, the word line structure includes: a gate oxide layer and a word line; wherein the gate oxide layer covers the sidewalls of the word line trench; and the gate oxide layer is located between the word line and the word line trench;

[0013] The recessed area is located within the character line in the first character line structure.

[0014] In some possible embodiments, the word line includes a first conductive film layer and a second conductive film layer; wherein the first conductive film layer is disposed on the sidewall of the word line trench, and the first conductive film layer is located between the second conductive film layer and the gate oxide layer;

[0015] The recessed area is located within the second conductive film layer of the first character line structure; or...

[0016] The second conductive film layer in the first character line structure is a solid structure; and in the first character line structure, the top surface of the second conductive film layer is lower than the top surface of the first conductive film layer, and the second conductive film layer serves as the bottom of the recessed area, while the first conductive film layer disposed on the sidewall of the character line groove serves as the sidewall of the recessed area.

[0017] In some possible embodiments, the word line structure includes: a gate oxide layer and a word line; wherein the gate oxide layer covers the sidewalls of the word line trench; and the gate oxide layer is located between the word line and the word line trench;

[0018] The character lines in the first character line structure section are solid structures;

[0019] In the first word line structure, the top surface of the word line is lower than the top surface of the gate oxide layer;

[0020] In the first word line structure, the word line serves as the bottom of the recessed region, and the gate oxide layer disposed on the sidewall of the word line trench serves as the sidewall of the recessed region.

[0021] In some possible embodiments, the gate oxide layer that contacts the second word line structure is in direct contact with the semiconductor substrate;

[0022] A shallow trench isolation layer is provided between the gate oxide layer in contact with the first word line structure and the semiconductor substrate.

[0023] In some possible embodiments, the insulating material includes at least one of air and inorganic insulating materials.

[0024] In some possible embodiments, the depth of the first word trench is greater than the depth of the second word trench in a direction perpendicular to the plane of the semiconductor substrate.

[0025] According to some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor device, including:

[0026] Provide semiconductor substrates;

[0027] A shallow trench isolation region is formed in the semiconductor substrate, and a plurality of spaced active regions are defined by the shallow trench isolation region.

[0028] A plurality of word line trenches are formed in the semiconductor substrate, intersecting with corresponding active regions; wherein the word line trenches include a first word line trench and a second word line trench; the orthographic projection of the first word line trench on the semiconductor substrate is located within the orthographic projection of the shallow trench isolation region on the semiconductor substrate; the orthographic projection of the second word line trench on the semiconductor substrate is located within the orthographic projection of the active region on the semiconductor substrate.

[0029] An embedded character line structure is formed in the character line groove; wherein the character line structure includes a first character line structure portion and a second character line structure portion electrically connected to each other; the first character line structure portion is formed in the first character line groove, and the second character line structure portion is formed in the second character line groove; the first character line structure portion has a clearance area, the top surface of the clearance area is flush with the top surface of the second character line structure portion, and the clearance area has an insulating material.

[0030] In some possible embodiments, forming a plurality of word line trenches in the semiconductor substrate that intersect with the corresponding active regions includes:

[0031] The first character-line groove is formed in the shallow channel isolation zone;

[0032] The second word line groove is formed in the active region.

[0033] In some possible embodiments, forming the embedded character line structure in the character line groove includes:

[0034] A gate oxide layer is applied to the sidewalls of the word line trench;

[0035] A conductive material is filled into the word line trench where the gate oxide layer is formed to form an initial word line structure;

[0036] The initial word line structure is etched so that the top surface of the initial word line structure is lower than the top surface of the semiconductor substrate, thereby forming a second word line structure portion and a first initial word line structure portion located in the first word line trench;

[0037] The first initial character line structure portion is etched to form an avoidance area, thereby forming the first character line structure portion;

[0038] After forming the embedded word line structure in the word line trench, the method further includes: forming an insulating barrier layer covering the entire semiconductor device, and filling the clearance area with an insulating material.

[0039] In some possible embodiments, forming an insulating barrier layer covering the entire semiconductor device and filling the clearance region with an insulating material includes:

[0040] An insulating barrier layer is formed covering the entire semiconductor device, and an air gap is formed in the clearance area of ​​the first word line structure.

[0041] In some possible embodiments, forming an insulating barrier layer covering the entire semiconductor device and filling the clearance region with an insulating material includes:

[0042] An insulating barrier layer is formed covering the entire semiconductor device, and the insulating barrier layer is filled in the clearance area of ​​the first word line structure.

[0043] According to some embodiments, a third aspect of this disclosure provides a semiconductor memory device, including the semiconductor device described above. Attached Figure Description

[0044] Figure 1 This is a top view of the semiconductor substrate structure in an embodiment of this disclosure;

[0045] Figure 2A for Figure 1 The diagram shows some cross-sectional views of the semiconductor substrate along the AA' direction.

[0046] Figure 2B for Figure 1 The diagram shows some cross-sectional views of the semiconductor substrate along the BB' direction.

[0047] Figure 3A These are some cross-sectional structural schematic diagrams illustrating the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0048] Figure 3BOther cross-sectional structural schematic diagrams of the semiconductor device fabrication process provided in the embodiments of this disclosure;

[0049] Figure 3C Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0050] Figure 3D Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0051] Figure 3E Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0052] Figure 3F Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0053] Figure 3G Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0054] Figure 3H Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0055] Figure 3I Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0056] Figure 3J Further cross-sectional structural schematic diagrams of the fabrication process of the semiconductor device provided in the embodiments of this disclosure;

[0057] Figure 4A for Figure 1 Schematic diagrams of other cross-sectional structures of the semiconductor substrate shown along the AA' direction;

[0058] Figure 4B for Figure 1 Schematic diagrams of other cross-sectional structures of the semiconductor substrate along the BB' direction are shown;

[0059] Figure 5 for Figure 1 The diagram shows some cross-sectional views of the semiconductor substrate along the AA' direction.

[0060] Figure 6 for Figure 1 The diagram shows some cross-sectional views of the semiconductor substrate along the AA' direction. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0063] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0064] See Figures 1-2B , Figure 1 This is a top view of the semiconductor device provided in an embodiment of the present disclosure. Figure 2A for Figure 1 The diagram shows a cross-sectional view of the semiconductor device along the AA' direction. Figure 2B for Figure 1 The diagram shows a cross-sectional view of the semiconductor device along the BB' direction. The semiconductor device provided in this embodiment may include a semiconductor substrate 10. Exemplarily, the semiconductor substrate 10 may be made of silicon, germanium, or silicon-on-insulator (SOI) semiconductors, or may include germanium-silicon compounds, silicon carbide, or other known materials, such as gallium arsenide and other Group III or V compounds. Dopant ions may also be implanted into the semiconductor substrate 10 to change electrical parameters according to design requirements. Exemplarily, the semiconductor substrate 10 may be a silicon substrate.

[0065] In this embodiment, the semiconductor substrate 10 may have an array region and a peripheral region. The array region may include memory cells, word line structures, and bit lines; the memory cells may include transistors and cylindrical capacitors. The peripheral region may include control circuits, protection circuits (e.g., fuse devices), etc.

[0066] In this embodiment of the disclosure, reference is made to Figures 1-2B The array region of the semiconductor substrate 10 may include a shallow trench isolation region 300 (STI), and a plurality of spaced active regions 100 defined by the shallow trench isolation region 300. In this embodiment, the shallow trench isolation region 300 may include shallow trenches and insulating material filling the shallow trenches, which serves to isolate shallow trench leakage current and reduce electrical coupling. Furthermore, the insulating material filling the shallow trenches may be silicon oxide, silicon nitride, or other materials. The depth of the shallow trenches can be set according to the needs of the actual application to control the degree of transistor isolation.

[0067] In this embodiment of the disclosure, reference is made to Figures 1-2B The array region of the semiconductor substrate 10 may include a plurality of word line structures 200 formed in the semiconductor substrate 10 and buried in word line trenches. The word line trenches intersect with the active regions 100 of the corresponding word line trenches; that is, the word line structures also intersect with the corresponding active regions 100. Furthermore, the word line trenches include a first word line trench 400A and a second word line trench 400B. The orthographic projection of the first word line trench 400A onto the semiconductor substrate 10 is located within the orthographic projection of the shallow channel isolation region 300 onto the semiconductor substrate 10. The orthographic projection of the second word line trench 400B onto the semiconductor substrate 10 is located within the orthographic projection of the active region 100 onto the semiconductor substrate 10. Furthermore, the word line structure 200 includes a first word line structure portion 200A and a second word line structure portion 200B that are electrically connected to each other; the first word line structure portion 200A is formed in a first word line groove 400A, and the second word line structure portion 200B is formed in a second word line groove 400B.

[0068] It should be noted that the second word line structure 200B, which is in direct contact with the active region 100, can be used as the gate of the corresponding transistor in the memory cell. During or after the formation of the word line structure, one source / drain region in the active region 100, such as the source / drain region 151 between the two word line structures, can be used as the source of the corresponding transistor; and another source / drain region, such as the source / drain regions 152 and 153 between the word line structure and the shallow channel isolation region 300, can be used as the drain of the corresponding transistor.

[0069] In this embodiment of the disclosure, reference is made to Figures 1-2BThe first word line structure 200A has a clearance region BR, the top surface of which is flush with the top surface of the second word line structure 200B (i.e., the top surface of the clearance region BR and the top surface of the second word line structure 200B are flush with plane S0), and the clearance region BR contains an insulating material. In this way, while allowing current to flow between the first word line structure 200A and the second word line structure 200B, by providing the clearance region BR in the first word line structure 200A, the charge is concentrated in the non-clearance region BRNBR of the first word line structure 200A. The charge at the clearance region BR of the first word line structure 200A is reduced, thereby reducing the coupling electric field between the clearance region BR of the first word line structure 200A and the adjacent second word line structure 200B, thus reducing interference between word line structures and improving the performance and reliability of the semiconductor device.

[0070] In this embodiment of the disclosure, reference is made to Figures 1-2B In the direction F0 perpendicular to the plane of the semiconductor substrate 10, the depth of the first word line trench 400A is greater than the depth of the second word line trench 400B. For example, the top surface of the first word line trench 400A is flush with the top surface of the second word line trench 400B, that is, the top surfaces of the first word line trench 400A and the second word line trench 400B are flush with plane S0. Here, plane S0 can be the plane containing the top surface of the active region 100 of the semiconductor substrate 10. In practical applications, the specific values ​​of the depth of the first word line trench 400A and the depth of the second word line trench 400B can be designed according to the requirements of the actual application, and are not limited here.

[0071] In this embodiment of the disclosure, reference is made to Figures 1-2B In the extension direction of the character line structure, within the same character line groove, the boundary of the first character line groove 400A coincides with the boundary of the second character line groove 400B. Furthermore, in the extension direction of the character line structure, within the same character line structure, the boundary of the first character line structure portion 200A coincides with the boundary of the first character line structure portion 200A.

[0072] In this embodiment of the disclosure, reference is made to Figures 1-2BThe second word line structure portion 200B is a solid structure. Furthermore, the cross-section of the first word line structure portion 200A has a recessed region AC0 in the direction perpendicular to the extension of the word line structure. That is, a groove is formed in the first word line structure portion 200A in the direction perpendicular to the semiconductor substrate 10. For example, the recessed region AC0 can be a clearance region BR. By creating a groove in the first word line structure portion 200A, the charge is concentrated mainly at the bottom of the groove, while the charge on the sidewalls of the groove is reduced. This lowers the coupling electric field between the sidewalls of the first word line structure portion 200A and the second word line structure portion 200B of the adjacent word line structure, thereby reducing interference between word line structures and improving the performance and reliability of the semiconductor device.

[0073] In this embodiment of the disclosure, reference is made to Figures 1-2B In the direction F0 perpendicular to the semiconductor substrate 10, the top surface of the recessed region AC0 is flush with the top surface of the second word line structure portion 200B, that is, both the top surface of the recessed region AC0 and the top surface of the second word line structure portion 200B are flush with the plane S1. In other words, in the direction F0 perpendicular to the semiconductor substrate 10, the plane S1 is lower than the plane S0, or the distance between the plane S1 and the bottom surface of the semiconductor substrate 10 (i.e., the side of the semiconductor substrate 10 facing away from the side where the word line trench is provided) is less than the distance between the plane S0 and the bottom surface of the semiconductor substrate 10 (i.e., the side of the semiconductor substrate 10 facing away from the side where the word line trench is provided).

[0074] In this embodiment of the disclosure, reference is made to Figures 1-2BIn the direction F0 perpendicular to the semiconductor substrate 10, the bottom surface AXS1 of the recessed region AC0 is higher than the bottom surface ZS2 of the second word line structure 200B, and the bottom surface ZS1 of the first word line structure 200A is lower than the bottom surface ZS2 of the second word line structure 200B. That is, the distance between the bottom surface AXS1 of the recessed region AC0 and the bottom surface of the semiconductor substrate 10 is greater than the distance between the bottom surface ZS2 of the second word line structure 200B and the bottom surface of the semiconductor substrate 10, and the distance between the bottom surface ZS1 of the first word line structure 200A and the bottom surface of the semiconductor substrate 10 is less than the distance between the bottom surface ZS2 of the second word line structure 200B and the bottom surface of the semiconductor substrate 10. This allows for better electrical connection between the first word line structure 200A and the second word line structure 200B within the same word line structure, facilitating signal transmission. Furthermore, since the charge concentration point is located at the bottom of the groove of the first word line structure portion 200A, and the facing area between the bottom of the groove of the first word line structure portion 200A and the second word line structure portion 200B of the adjacent word line structure is minimized as much as possible, the coupling electric field between the bottom of the groove of the first word line structure portion 200A and the second word line structure portion 200B of the adjacent word line structure can be minimized as much as possible, thereby further reducing interference between word line structures and improving the performance and reliability of semiconductor devices.

[0075] In this embodiment of the disclosure, reference is made to Figures 1-2B The word line structure may include a gate oxide layer 230 and a word line; wherein the gate oxide layer 230 covers the sidewalls of the word line trench; and the gate oxide layer 230 is located between the word line and the word line trench. Furthermore, exemplarily, the gate oxide layer 230 in contact with the second word line structure portion 200B is in direct contact with the semiconductor substrate 10. A shallow channel isolation layer 300 is provided between the gate oxide layer 230 in contact with the first word line structure portion 200A and the semiconductor substrate 10.

[0076] In this embodiment of the disclosure, reference is made to Figures 1-2B The recessed region AC0 can be located within the word line in the first word line structure portion 200A. Exemplarily, the word line includes a first conductive film layer 210 and a second conductive film layer 220; wherein the first conductive film layer 210 is disposed on the sidewall of the word line trench, and the first conductive film layer 210 is located between the second conductive film layer 220 and the gate oxide layer 230. Exemplarily, the recessed region AC0 can be located within the second conductive film layer 220 in the first word line structure portion 200A. For example, during fabrication, the second conductive film layer 220 in the first word line structure portion 200A can be vapor-etched to form the recessed region AC0 in the second conductive film layer 220 in the first word line structure portion 200A, serving as an avoidance region BR.

[0077] In this embodiment of the disclosure, reference is made to Figures 1-2BThe insulating material in the clearance area BR can be air. For example, an air gap can be formed in the first letter structure portion 200A using an air gap process.

[0078] by Figures 1 to 2B For example, see the semiconductor device shown. Figures 3A to 3J , Figures 3A to 3J These are cross-sectional structural diagrams showing the fabrication process of the semiconductor device provided in the embodiments of this disclosure.

[0079] The preparation method provided in this disclosure may include the following steps:

[0080] S10, providing a semiconductor substrate 10.

[0081] For example, the semiconductor substrate 10 may be made of silicon, germanium, or silicon-on-insulator (SOI) semiconductors, or may include germanium-silicon compounds, silicon carbide, or other known materials, such as gallium arsenide and other group III or V compounds. Dopant ions may also be implanted into the semiconductor substrate 10 to modify electrical parameters according to design requirements. For example, the semiconductor substrate 10 may be a silicon substrate.

[0082] S20. A shallow trench isolation region 300 is formed in the semiconductor substrate 10, and a plurality of spaced active regions 100 are defined by the shallow trench isolation region 300.

[0083] For example, step S20 may specifically involve: first, forming an STI mask on the semiconductor substrate 10, wherein the area of ​​the semiconductor substrate 10 covered by the STI mask is the active region 100. Then, using the STI mask as an etching mask, a vapor phase etching process is employed. The etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, etching the exposed semiconductor substrate 10 to form shallow trench isolation trenches, thus preserving the area of ​​the semiconductor substrate 10 where the active region 100 will be formed. Afterwards, the STI mask is removed, forming... Figure 3A The semiconductor substrate 10 shown has a shallow trench isolation trench ST0.

[0084] See afterward. Figure 3B SiN is filled in the shallow trench isolation trench ST0 as a shallow trench isolation layer 300, thereby forming a shallow trench isolation region 300, and a plurality of spaced active regions 100 are defined by the shallow trench isolation region 300 on the semiconductor substrate 10.

[0085] S30. A plurality of word line trenches are formed in the semiconductor substrate 10, which are intersected with the corresponding active regions 100.

[0086] In this embodiment of the disclosure, step S30, for example, may specifically be:

[0087] First, a first word line trench 400A can be formed in the shallow trench isolation region 300 using photolithography and etching processes. For example, a photolithography process is used to form a mask for the first word line trench 400A, exposing the area in the shallow trench isolation region 300 where the first word line trench 400A will be formed. Using the first word line trench 400A mask as an etching mask, a vapor phase etching process is employed. The etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, etching the exposed SiN in the shallow trench isolation region 300 to form the first word line trench 400A in the SiN in the shallow trench isolation region 300. Then, vapor phase etching is used to remove the first word line trench 400A mask, thereby forming... Figure 3C The structure of the semiconductor device shown is that a first word line trench 400A is formed in SiN in the shallow trench isolation region 300.

[0088] Subsequently, a second word line trench 400B can be formed in the active region 100 using photolithography and etching processes. For example, a second word line trench 400B mask is formed using photolithography, exposing the area in the active region 100 of the semiconductor substrate 10 where the second word line trench 400B will be formed. Using the second word line trench 400B mask as an etching mask, a vapor phase etching process is employed. The etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, etching the exposed active region 100 to form the second word line trench 400B in the active region 100. Then, the second word line trench 400B mask is removed using vapor phase etching, thereby forming... Figure 3D The structure of the semiconductor device shown is such that a second word line trench 400B is formed in the active region 100.

[0089] It should be noted that, along the extension direction of the character line structure, the first character line groove 400A and the second character line groove 400B in the same character line groove are arranged alternately.

[0090] S40. An embedded character line structure is formed in the character line groove.

[0091] In this embodiment of the disclosure, step S40, for example, may specifically be:

[0092] First, a gate oxide layer 230 can be deposited on the sidewalls of the word line trench. For example, see... Figure 3EThe gate oxide layer 230 is formed on the sidewall of the word line trench. For example, the material of the gate oxide layer 230 may include one or more of silicon oxide, silicon nitride, oxide nitride, silicon nitride, and oxide / nitride / oxide (ONO). The gate oxide layer 230 may be formed by a wet or dry thermal oxidation process, such as in an environment including oxides, water vapor, nitric oxide, or combinations thereof, or by an in-situ vapor generation (ISSG) process in an environment including oxygen, water vapor, nitric oxide, or combinations thereof, or by a chemical vapor deposition (CVD) technique using tetraethyl orthosilicate (TEOS) and oxygen as precursors.

[0093] Subsequently, conductive material can be filled into the word line trench where the gate oxide layer 230 is formed to form an initial word line structure. Exemplarily, the material of the word line structure may include one or more of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN. Exemplarily, the word line structure may be a single-layer structure. For example, it may be formed using one of Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN. Alternatively, the word line structure may also be a multi-layer structure. For example, see [link to documentation]. Figure 3F At a set deposition rate, a TiN layer 210 is deposited on the sidewalls of the word line trench having a gate oxide layer 230 as the first conductive film layer 210 in the word line structure. See then... Figure 3G A W layer 220 is deposited at a set deposition rate within the word line trench containing the TiN layer 210, serving as the second conductive film layer 220 in the word line structure. The first conductive film layer 210 is located between the second conductive film layer 220 and the gate oxide layer 230. This allows the TiN layer 210 and the W layer 220 to form a single unit, creating the initial word line structure. It should be noted that those skilled in the art can select from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes for the above deposition method; this disclosure is not limited thereto. Furthermore, the deposition rate can be designed and determined according to the needs of the actual application, and is not limited herein.

[0094] Subsequently, the initial word line structure is etched so that the top surface of the initial word line structure is lower than the top surface of the semiconductor substrate 10, thereby forming the second word line structure portion 200B and the first initial word line structure portion located in the first word line trench 400A. For example, see... Figure 3HA vapor phase etching process can be used, and the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2 and Ar to achieve a certain etching selectivity ratio to etch the initial word line structure so that the top surface S01 of the initial word line structure is lower than the top surface S02 of the semiconductor substrate 10, thereby forming a word line structure buried in the semiconductor substrate 10.

[0095] Subsequently, the first initial word line structure portion is etched to form an avoidance region BR, thereby forming the first word line structure portion 200A. Exemplarily, photolithography and etching processes can be used to etch the first initial word line structure portion to form the avoidance region BR, thereby forming the first word line structure portion 200A. For example, see... Figure 3I A photolithography process is used to form an avoidance mask (BRM), which exposes the portion of the first initial word line structure where the avoidance region (BR) is to be formed. See then... Figure 3J Using the avoidance mask BRM as the etching mask, a vapor phase etching process is adopted. The etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2 and Ar to achieve a certain etching selectivity. The exposed W layer in the first initial word line structure is etched by vapor phase etching to form a recessed region AC0 in the W layer of the first initial word line structure as an avoidance region BR.

[0096] After step S40, an insulating barrier layer covering the entire semiconductor device can be formed, and the clearance region BR is filled with an insulating material. For example, see... Figure 2A An air gap forming process can be employed to form an air gap in the clearance region BR of the first word line structure 200A while simultaneously forming an insulating barrier layer covering the entire semiconductor device. Exemplarily, the material of the insulating barrier layer may include one or more of silicon oxide, silicon nitride, oxide oxynitride, silicon nitride, and oxide / nitride / oxide (ONO). For example, an air gap forming process can be employed to form an air gap in the clearance region BR of the first word line structure 200A while simultaneously forming a SiN layer covering the entire semiconductor device as an insulating barrier layer.

[0097] It should be noted that in actual preparation processes, due to limitations in process conditions or other factors, the aforementioned flushing may not be perfectly flush and may have some deviations. Therefore, as long as the aforementioned flushing relationship roughly meets the above conditions, it falls within the protection scope of this disclosure. For example, the aforementioned flushing can be a flushing that is permissible within the allowable error range.

[0098] This disclosure provides schematic diagrams of the structures of other semiconductor devices, such as... Figure 4A and Figure 4BAs shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0099] See Figure 4A and Figure 4B , Figure 4A for Figure 1 Schematic diagrams of other cross-sectional structures of the semiconductor substrate shown along the AA' direction; Figure 4B for Figure 1 The diagram shows other cross-sectional views of the semiconductor substrate along the BB' direction. In the embodiments of this disclosure, in the fabrication method, the first initial word line structure portion is etched to form a clearance region BR, thereby forming the first word line structure portion 200A. Exemplarily, when the word line structure adopts a stacked structure of, for example, TiN layer 210 and W layer 220, after forming the W layer in the word line trench with the TiN layer, the W layer formed in the first word line trench 400A can be vapor-phase etched to remove a certain distance (which can be designed and determined according to the actual application) of the W layer, so that the W layer in the first word line trench 400A is a solid structure, thereby allowing the remaining W layer and the TiN layer to form a recessed region AC0. The W layer in the first word line trench 400A and the TiN layer below the W layer serve as the bottom of the recessed region AC0, and the TiN layer on the sidewall of the word line trench serves as the sidewall of the recessed region AC0. It should be noted that the remaining steps of the semiconductor device fabrication method in this embodiment are basically the same as the remaining steps in the above-described fabrication method, and will not be repeated here.

[0100] In the embodiments disclosed herein, such as Figure 4A and Figure 4B As shown, the second conductive film layer 220 (e.g., W layer) in the first word line structure portion 200A is a solid structure. Furthermore, in the first word line structure portion 200A, the top surface AXS2 of the second conductive film layer 220 (e.g., W layer) is lower than the top surface AXS3 of the first conductive film layer 210 (e.g., TiN layer), and the second conductive film layer 220 (e.g., W layer) serves as the bottom of the recessed region AC0, while the first conductive film layer 210 (e.g., TiN layer) disposed on the sidewall of the word line groove serves as the sidewall of the recessed region AC0.

[0101] This disclosure provides schematic diagrams of the structures of other semiconductor devices, such as... Figure 5 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0102] See Figure 5 , Figure 5 for Figure 1The diagram shows further cross-sectional views of the semiconductor substrate along the AA' direction. In the embodiments of this disclosure, in the fabrication method, the first initial word line structure is etched to form a clearance region BR, thereby forming the first word line structure 200A. Exemplarily, when the word line structure adopts a stacked structure of, for example, TiN layer 210 and W layer 220, after forming the W layer in the word line trench with the TiN layer, both the W layer and the TiN layer formed in the first word line trench 400A are vapor-phase etched to remove a certain distance (which can be designed and determined according to the actual application) of the W layer and TiN layer, so that the W layer and TiN layer in the first word line trench 400A form a solid structure as a whole, thereby allowing the remaining W layer, TiN layer and gate oxide layer 230 to form a recessed region AC0. In this embodiment, the W layer in the first word trench 400A and the TiN layer below the W layer can serve as the bottom of the recessed region AC0, and the gate oxide layer 230 on the sidewall of the word trench serves as the sidewall of the recessed sidewall. It should be noted that the remaining steps of the semiconductor device fabrication method in this embodiment are basically the same as the remaining steps in the above-described fabrication method, and will not be repeated here.

[0103] In the embodiments disclosed herein, such as Figure 5 As shown, the top surface AXS2 of the W layer 220 in the first word line structure section 200A can be higher than the bottom surface of the TiN layer in the second word line structure section 200B, and the bottom surface of the TiN layer in the first word line structure section 200A can be lower than the bottom surface of the TiN layer in the second word line structure section 200B.

[0104] In the embodiments disclosed herein, such as Figure 5 As shown, the word lines in the first word line structure 200A are solid structures. Furthermore, in the first word line structure 200A, the top surface AXS4 of the word line is lower than the top surface AXS5 of the gate oxide layer 230 (for example, it could be an S0 plane). Also, in the first word line structure 200A, the word line serves as the bottom of the recessed region AC0, and the gate oxide layer 230 disposed on the sidewall of the word line trench serves as the sidewall of the recessed region AC0.

[0105] This disclosure provides schematic diagrams of the structures of other semiconductor devices, such as... Figure 6 As shown, this embodiment is a variation of the implementation described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0106] In the embodiments disclosed herein, such as Figure 6 As shown, the insulating material in the avoidance area BR can also be an inorganic insulating material. For example, the inorganic insulating material may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, and oxide / nitride / oxide (ONO).

[0107] See Figure 6 , Figure 6 for Figure 1 The diagram shows further cross-sectional views of the semiconductor substrate along the AA' direction. In this embodiment, during the fabrication method, a SiN layer is deposited over the entire semiconductor device at a predetermined deposition rate as an insulating barrier layer, and simultaneously, a filling SiN layer is deposited in the clearance region BR of the first word line structure portion 200A. It should be noted that the remaining steps of the semiconductor device fabrication method in this embodiment are substantially the same as those in the aforementioned fabrication method, and will not be described in detail here.

[0108] This disclosure also provides some semiconductor memory devices. These semiconductor memory devices may include the semiconductor devices described above. The principle by which these semiconductor memory devices solve the problem is similar to that of the aforementioned semiconductor devices; therefore, the implementation of these semiconductor memory devices can refer to the implementation of the aforementioned semiconductor devices, and repeated details will not be described here.

[0109] In specific implementations, in the embodiments of this disclosure, the semiconductor device is, for example, DRAM. A semiconductor memory device may include a semiconductor device. Furthermore, the semiconductor memory device may be a product or component with storage functionality. Other essential components of the semiconductor memory device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0110] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate includes: a shallow trench isolation region, and a plurality of spaced active regions defined by the shallow trench isolation region; Multiple word line trenches are formed in the semiconductor substrate, and the word line trenches intersect with corresponding active regions; wherein, the word line trenches include a first word line trench and a second word line trench; the orthographic projection of the first word line trench on the semiconductor substrate is located within the orthographic projection of the shallow trench isolation region on the semiconductor substrate; the orthographic projection of the second word line trench on the semiconductor substrate is located within the orthographic projection of the active region on the semiconductor substrate; A character line structure is embedded in the character line groove; wherein, the character line structure includes a first character line structure portion and a second character line structure portion connected to each other; the first character line structure portion is formed in the first character line groove, and the second character line structure portion is formed in the second character line groove; The first character line structure has a clearance area, the top surface of which is flush with the top surface of the second character line structure, and the clearance area contains an insulating material. In the extension direction perpendicular to the word line structure, the cross-section of the first word line structure portion has a recessed region; the word line structure includes: a gate oxide layer and a word line, the word line including a first conductive film layer and a second conductive film layer; wherein, the first conductive film layer is disposed on the sidewall of the word line trench, and the first conductive film layer is located between the second conductive film layer and the gate oxide layer; The recessed area is located within the second conductive film layer of the first character line structure; or... The second conductive film layer in the first character line structure is a solid structure; and in the first character line structure, the top surface of the second conductive film layer is lower than the top surface of the first conductive film layer, and the second conductive film layer serves as the bottom of the recessed area, while the first conductive film layer disposed on the sidewall of the character line groove serves as the sidewall of the recessed area.

2. The semiconductor device as claimed in claim 1, characterized in that, The second character line structure is a solid structure; The avoidance area includes the recessed area.

3. The semiconductor device as described in claim 2, characterized in that, In a direction perpendicular to the semiconductor substrate, the top surface of the recessed region is flush with the top surface of the second word line structure portion; Furthermore, in a direction perpendicular to the semiconductor substrate, the bottom surface of the recessed region is higher than the bottom surface of the second word line structure portion, and the bottom surface of the first word line structure portion is lower than the bottom surface of the second word line structure portion.

4. The semiconductor device as described in claim 3, characterized in that, The gate oxide layer covers the sidewall of the word line trench; and the gate oxide layer is located between the word line and the word line trench; The recessed area is located within the character line in the first character line structure.

5. The semiconductor device as described in claim 3, characterized in that, The gate oxide layer covers the sidewall of the word line trench; and the gate oxide layer is located between the word line and the word line trench; The character lines in the first character line structure section are solid structures; In the first word line structure, the top surface of the word line is lower than the top surface of the gate oxide layer; In the first word line structure, the word line serves as the bottom of the recessed region, and the gate oxide layer disposed on the sidewall of the word line trench serves as the sidewall of the recessed region.

6. The semiconductor device as claimed in claim 4 or 5, characterized in that, The gate oxide layer that contacts the second word line structure is in direct contact with the semiconductor substrate; A shallow trench isolation layer is provided between the gate oxide layer in contact with the first word line structure and the semiconductor substrate.

7. The semiconductor device according to any one of claims 1-5, characterized in that, The insulating material includes at least one of air and inorganic insulating materials.

8. The semiconductor device according to any one of claims 1-5, characterized in that, In a direction perpendicular to the plane of the semiconductor substrate, the depth of the first word line trench is greater than the depth of the second word line trench.

9. A method for fabricating a semiconductor device as described in any one of claims 1-8, characterized in that, include: Provide semiconductor substrates; A shallow trench isolation region is formed in the semiconductor substrate, and a plurality of spaced active regions are defined by the shallow trench isolation region. A plurality of word line trenches are formed in the semiconductor substrate, intersecting with corresponding active regions; wherein the word line trenches include a first word line trench and a second word line trench; the orthographic projection of the first word line trench on the semiconductor substrate is located within the orthographic projection of the shallow trench isolation region on the semiconductor substrate; the orthographic projection of the second word line trench on the semiconductor substrate is located within the orthographic projection of the active region on the semiconductor substrate. An embedded character line structure is formed in the character line groove; wherein the character line structure includes a first character line structure portion and a second character line structure portion electrically connected to each other; the first character line structure portion is formed in the first character line groove, and the second character line structure portion is formed in the second character line groove; the first character line structure portion has a clearance area, the top surface of the clearance area is flush with the top surface of the second character line structure portion, and the clearance area has an insulating material.

10. The preparation method according to claim 9, characterized in that, The formation of a plurality of word line trenches in the semiconductor substrate, intersecting with the corresponding active regions, includes: The first character-line groove is formed in the shallow channel isolation zone; The second word line groove is formed in the active region.

11. The preparation method according to claim 10, characterized in that, The process of forming an embedded character line structure in the character line groove includes: A gate oxide layer is applied to the sidewalls of the word line trench; A conductive material is filled into the word line trench where the gate oxide layer is formed to form an initial word line structure; The initial word line structure is etched so that the top surface of the initial word line structure is lower than the top surface of the semiconductor substrate, thereby forming a second word line structure portion and a first initial word line structure portion located in the first word line trench; The first initial character line structure portion is etched to form an avoidance area, thereby forming the first character line structure portion; After forming the embedded word line structure in the word line trench, the method further includes: forming an insulating barrier layer covering the entire semiconductor device, and filling the clearance area with an insulating material.

12. The preparation method according to claim 11, characterized in that, The formation of an insulating barrier layer covering the entire semiconductor device and filling the clearance area with an insulating material includes: An insulating barrier layer is formed covering the entire semiconductor device, and an air gap is formed in the clearance area of ​​the first word line structure.

13. The preparation method according to claim 11, characterized in that, The formation of an insulating barrier layer covering the entire semiconductor device and filling the clearance area with an insulating material includes: An insulating barrier layer is formed covering the entire semiconductor device, and the insulating barrier layer is filled in the clearance area of ​​the first word line structure.

14. A semiconductor memory device, characterized in that, Includes the semiconductor device as described in any one of claims 1-8.

Images