Techniques for command sequence adjustment

Abstract

This application is directed to techniques for command sequence adjustment. A memory system or a host system can adjust an order of a set of commands in a queue, for example, by determining whether each command of a subset of the commands corresponds to a same size of data, if the memory system or host system determines that the subset of commands is part of a test pattern. The set of commands can be reordered such that the subset of commands associated with the test pattern are contiguous or back-to-back. In certain cases, the subset of commands associated with a test pattern can be reordered such that logical addresses (e.g., logical block addresses) of the subset of commands are contiguous.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 497,610, filed October 8, 2021, entitled "Technologies for Command Sequence Adjustment," which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to techniques for command sequence adjustment. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to the corresponding state.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Unless periodically refreshed by an external power supply, volatile memory cells (e.g., DRAM cells) may lose their programmed state over time. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured to cause the apparatus to: receive a set of commands at a memory system; store the set of commands in a queue based on a first sequence of the received set of commands; determine whether a subset of commands in the set of commands is associated with a test mode; configure a second sequence of the set of commands in the queue based on the determination that the subset of commands is associated with the test mode, the second sequence being based on a corresponding logical address associated with each command of the subset of commands; and execute the subset of commands according to the second sequence as part of the test mode.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a set of commands at a memory system; store the set of commands in a queue according to a first sequence based on the received set of commands; determine whether a subset of commands in the set of commands is associated with a test mode; configure a second sequence of the set of commands in the queue based on the determination that the subset of commands is associated with the test mode, the second sequence being based on a corresponding logical address associated with each command of the subset of commands; and execute the subset of commands according to the second sequence as part of the test mode.

[0008] Describe a method. The method may include: receiving a set of commands at a memory system; storing the set of commands in a queue based on a first sequence of the received set of commands; determining whether a subset of commands in the set of commands is associated with a test mode; configuring a second sequence of the set of commands in the queue based on the determination that the subset of commands is associated with the test mode, the second sequence being based on a corresponding logical address associated with each command in the subset of commands; and executing the subset of commands according to the second sequence as part of the test mode. Attached Figure Description

[0009] Figure 1 Examples of systems that support techniques for command sequence adjustment based on examples disclosed herein are shown.

[0010] Figure 2 Examples of systems that support techniques for command sequence adjustment based on examples disclosed herein are shown.

[0011] Figure 3 Examples of process flows supporting techniques for command sequence adjustment, as disclosed herein, are shown.

[0012] Figure 4Examples of process flows supporting techniques for command sequence adjustment, as disclosed herein, are shown.

[0013] Figure 5 A block diagram of a memory system that supports techniques for command sequence adjustment based on examples disclosed herein is shown.

[0014] Figure 6 A block diagram of a host system that supports techniques for command sequence tuning based on examples disclosed herein is shown.

[0015] Figure 7 and 8 The flowcharts shown are based on examples disclosed herein, illustrating one or more methods that support techniques for command sequence adjustment. Detailed Implementation

[0016] A memory system can measure system performance (e.g., read performance, write performance) by receiving and executing a set of commands from the host system as part of a test mode. For example, a test mode might include executing a number of write commands to write a target test file to a newly opened memory block, reading back the target test file one or more times (e.g., three times) to calculate average sequential read performance, and rewriting (e.g., overwriting) the target test file one or more times (e.g., three times) to calculate average sequential write performance. However, in some cases, the host system may also issue commands from a background task (e.g., commands not part of the test mode) during the test mode. In some cases, commands associated with a background task can be executed between commands associated with the test mode, which may degrade system performance by causing the memory system to switch between executing test mode commands and background task commands.

[0017] This disclosure describes techniques for reordering a subset of command sets in a queue (e.g., a queue at the memory system or a queue at the host system) that is associated with a test mode. For example, the memory system or host system may reorder the sequence or order of command sets such that commands associated with a test mode are consecutive (e.g., each of the test mode commands is executed sequentially or back-to-back). Furthermore, the memory system or host system may reorder the command sets such that the logical addresses (each of which may be referred to as a logical block address (LBA)) of the test mode commands are consecutive. In a non-limiting example, the first command in the reordered set of commands may correspond to an LBA of 0 to 127, the second command in the reordered set of commands may correspond to an LBA of 128 to 255, and so on. Reordering the command sequence as described herein can, for example, improve test mode performance by allowing the memory system to execute test modes consecutively.

[0018] First refer to Figures 1 to 2 Features of this disclosure are described in the context of systems, devices, and circuits. References Figure 3 and 4 The features of this disclosure are described in the context of a process flow. References Figure 5-8 These and other features of this disclosure are further illustrated by device diagrams and flowcharts relating to techniques for command sequence adjustment, and described in the context of said device diagrams and flowcharts.

[0019] Figure 1 An example of a system 100 supporting techniques for command sequence adjustment, as disclosed herein, is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0022] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations as described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses or physical page addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a circuit system having dedicated (e.g., hard-decoded) logic for performing the operations attributed to the memory system controller 115 herein. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, in the case of reading from or writing to memory device 130, data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., in the case of reduced latency relative to memory device 130).

[0029] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on external controllers (e.g., implemented by host system 105) or one or more local controllers 135 within memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 managed at least partially by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual blocks 170 may be referred to as physical blocks, and virtual blocks 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual blocks 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may also be called a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0037] System 100 may include any number of non-transitory computer-readable media that support techniques for command sequence adjustment. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), these instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0038] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] In some cases, memory system 110 or host system 105 may support adjusting the order of a subset of command sets associated with a test mode when memory system 110 or host system 105 determines a queue (e.g., a queue at memory system 110 containing commands issued by host system 105, or a queue at host system 105 containing commands to be issued to memory system 110) in which a test mode is associated. For example, memory system 110 or host system 105 may adjust the sequence or order of command sets such that commands associated with a test mode are consecutive (e.g., each of the test mode commands is executed sequentially or back-to-back). Furthermore, memory system 110 or host system 105 may adjust the order of command sets such that the LBAs of the test mode commands are consecutive. Adjusting the sequence of commands as described herein can, for example, improve test mode performance by allowing memory system 110 to execute test modes consecutively.

[0040] Figure 2 An example of a system 200 supporting techniques for command sequence adjustment, as disclosed herein, is shown. System 200 may be as described in the references... Figure 1 An example of system 100 as described in the preceding description. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may be implemented as described in the reference. Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0041] As described herein, memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205. Memory device 240 may include, as referenced... Figure 1 The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0042] Memory system 210 may include memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. Memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, memory controller 230 may be implemented as described in reference [reference missing]. Figure 1 The aspects of the local controller 135 described.

[0043] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 may be used, for example, by translating data between the host system 205 and the memory device 240 as shown by the data path 250, and may be collectively referred to as the data path components.

[0044] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or emitted (or both). Buffer 225 may contain relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators, or both, to allow for rapid storage of data into and from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0045] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 can be a non-cached buffer. That is, the host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0046] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0047] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) may be located anywhere within the memory system 210.

[0048] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0049] If host system 205 issues an access command to memory system 210, interface 220 may receive the command, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 may transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command may be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0050] The memory system controller 215 may determine that an access command has been received based on (e.g., using) communication from interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving a command from command queue 260. After, for example, the command has been retrieved from command queue 260 by memory system controller 215, the command may be removed from command queue 260. In some cases, the memory system controller 215 may cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0051] After confirming that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0052] In either case, the memory system controller 215 may use the buffer 225 (in particular) for temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered as an intermediate end of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0053] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0054] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0055] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to deliver" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to deliver the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data delivery to buffer 225 has been completed.

[0056] Once written data has been stored in buffer 225 via interface 220, the data can be transferred out of buffer 225 and stored in memory device 240. This can be done using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0057] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain an entry for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is obtained, from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the locations within memory device 240 used to store data (e.g., perform wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, via the storage controller 230 or the memory system controller 215.

[0058] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0059] In some cases, buffer queue 265 can be used to assist in the buffered storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0060] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data to be retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data to be stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of data to be stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0061] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transmit the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that data transmission to host system 205 has been completed.

[0062] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in, first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moving into and stored in buffer 225, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been passed out of buffer 225), the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0063] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control operations (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses or physical page addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more adjacent LBAs may correspond to non-adjacent physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0064] In some cases, host system 205 may include command queue 261. Command queue 261 may store commands, such as access commands, and then issue the commands to memory system 210 (e.g., command queue 260 of memory system 210). In some cases, host system 205 may issue commands from command queue 261 to interface 220 of memory system 210.

[0065] In certain circumstances, memory system 210 or host system 205 may support adjusting the order of command sets when a subset of command sets in a queue (e.g., command queue 260 at memory system 210 containing commands issued by host system 205 from command queue 261, or command queue 261 at host system 205 containing commands to be issued to memory system 210) is associated with a test mode. For example, memory system 210 or host system 205 may adjust the sequence or order of command sets in command queue 260 or command queue 261 such that commands associated with a test mode are consecutive (e.g., each of the test mode commands is executed sequentially or back-to-back). In certain circumstances, the order of commands may be adjusted by memory system controller 215 or a controller associated with host system 205. In the case where the controller associated with host system 205 adjusts the order of commands, the controller associated with host system 205 may adjust the order of commands stored in command queue 261.

[0066] Furthermore, the memory system 210 or the host system 205 can adjust the order of the command set so that the LBAs of the test mode commands are sequential. As described herein, adjusting the sequence of commands can, for example, improve test mode performance by allowing the memory system 210 to execute test modes sequentially.

[0067] Figure 3 An example of process flow 300 supporting techniques for command sequence adjustment, as disclosed herein, is shown. Process flow 300 may be provided by a memory system (e.g., reference Memory System). Figure 1 and 2 The process flow 300 is executed by components of the memory system 110 described herein. For example, the process flow 300 may be executed by a controller of the memory system or memory device (or both), such as memory system controller 115 or local controller 135, as described in reference [reference needed]. Figure 1 As described. Process flow 300 can be implemented to reduce latency and power consumption and increase system performance, as well as achieve other benefits. Aspects of process flow 300 can be implemented by a controller and other components. Alternatively or additionally, aspects of process flow 300 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system controller 115 or local controller 135). For example, if the instructions are executed by a controller (e.g., memory system controller 115, local controller 135), they can cause the controller to perform the operation of process flow 300. In the following description of process flow 300, operations can be performed in a different order than those shown. For example, specific operations can be omitted from process flow 300, or other operations can be added to process flow 300.

[0068] At position 305, a command set can be received. For example, the memory system can receive a command set from the host system. In some instances, the command set may contain access commands, such as read commands, write commands, or erase commands, stored in blocks of one or more memory devices within the memory device, and other instances.

[0069] At position 310, a command set can be stored. For example, the memory system can use a first sequence in a queue to store the command set, such as command queue 260, buffer queue 265, storage queue 270, or a combination thereof, as referenced. Figure 2 As described. For example, if a command set contains six commands (i.e., commands one through six), the first sequence may indicate that the first command will be executed, followed by the second command (e.g., after the first command has been completed), then the third command, and so on, until every command in the command set has been executed. In some cases, the first sequence may reflect the order in which each command in the command set was received from the host system.

[0070] At point 315, it can be determined whether a subset of commands in the command set is part of a test mode. For example, the memory system can determine whether a subset of commands is a write command associated with a test mode (e.g., a benchmarking mode) used to measure the performance of the memory system, such as write speed or read performance, and other instances. A test mode may include executing a number of write commands to write a target test file to a newly opened memory block, reading back the target test file one or more times (e.g., three times) to calculate average sequential read performance, and rewriting (e.g., overwriting) the target test file one or more times (e.g., three times) to calculate average sequential write performance.

[0071] In some cases, a memory system can determine whether a subset of commands is part of a test pattern by determining whether each command in the subset is a write command associated with data of the same size. In a non-limiting instance, as part of writing to a target test file, the host system may issue one or more write commands to write to the target test file using a common block size (e.g., a 512 kilobyte (KB) block size). Therefore, if the memory system detects that each command in the subset indicates data of the same size to be written, the memory system can determine that the subset of commands is part of a test pattern.

[0072] In some cases, it can be determined at 315 that commands in a subset of the command set are not part of the test mode. Therefore, at 320, the command set is executable. For example, the memory system can execute the command set by executing each of the commands according to a first sequence (e.g., according to the order in which the commands are received from the host system).

[0073] At 325, if it is determined that commands in a subset of the command set are part of a test mode, a second sequence of the command set can be configured. For example, the memory system can configure the second sequence by adjusting the order of the first sequence (e.g., the order in which the command set will be executed). In some cases, the second sequence may indicate that the LBAs of each command in the subset of commands are consecutive (e.g., the LBA of the first command to be executed is lower than the LBA of the second command to be executed after the first command).

[0074] In a non-limiting instance, the command set may comprise four commands stored in a queue according to a first sequence (e.g., storing the first command through the fourth command sequentially). The first command may indicate an LBA of 0 to 127 (e.g., the first command may have a block size of 512 KB), the second command may indicate an LBA of 256 to 383 (e.g., the second command may have a block size of 512 KB), the third command may indicate an LBA of 10240 and have a block size of 4 KB, and the fourth command may indicate an LBA of 128 to 255 (e.g., the fourth command may have a block size of 512 KB).

[0075] Because the first, second, and fourth commands each indicate the same data size (e.g., a 512KB block size), the memory system can determine that the first, second, and fourth commands are part of a test mode. Therefore, the memory system can use a second sequence to configure the order in which the commands are stored in the queue, such that the order indicates that the first command will be executed, followed by the fourth command (e.g., because the LBA of the fourth command follows the first command), then the second command, and then the third command. In other words, the memory system can reorder a subset of commands such that the LBA of a command is equal to the LBA of the previous command plus the block size of the previous command.

[0076] At 330, a subset of executable commands. For example, the memory system may execute a subset of commands in the order indicated by a second sequence (e.g., configured at 325). In some cases, the subset of commands to be executed may include writing data associated with at least one command of the subset of commands into a newly opened block (e.g., a first block) of the memory cell. For example, as part of a test mode, the memory system may open a first block of memory to record a target test file and subsequently write the data indicated in the subset of commands into the first block.

[0077] In some cases, writing a subset of commands to the first block may involve writing the data for each command to contiguous physical addresses (e.g., the physical addresses of the memory cells indicated by the LBAs of the subset of commands may be contiguous), such as contiguous physical page addresses. For example, the first command executed in the subset may involve writing data to a first set of physical addresses, the second command executed in the subset may involve writing data to a second set of physical addresses immediately following the first set, and so on, until every write command in the subset has been executed. In some cases, writing the target test file to contiguous physical addresses can improve write performance, as well as read performance (if the target test file is subsequently read).

[0078] In some cases, a cancel mapping command may be received at position 335. For example, the memory system may receive a cancel mapping command from the host system. The cancel mapping command may indicate that data written as part of a test mode (e.g., data written at position 330) will be erased. In some instances, receiving a cancel mapping command may indicate the end of the test mode. Therefore, in response to receiving a cancel mapping command, the memory system may erase the data written as part of the test mode from the first block.

[0079] In some cases, the test mode may end at 340. For example, the memory system may determine to end the test mode in response to receiving an unmapping command, executing an unmapping command, or both. Alternatively, the memory system may determine to end the test mode in response to a second subset of commands satisfying a threshold number of commands. For example, if the memory system detects a certain number of random commands (e.g., a certain number of commands that are not part of the test mode, such as commands associated with a background task), the memory system may determine to end the test mode. In some instances, the threshold number may be 16, but it should be understood that other numbers are possible.

[0080] In some cases, at 345, a second subset of commands can be executed. For example, after exiting test mode, the memory system can execute the remainder of the commands not associated with test mode (e.g., the second subset) stored in the queue at 310. The second set of commands can be instances of access commands such as read, write, or erase commands, or any other commands received by the memory system from the host system. In some instances, such as if the second subset of commands contains write commands, the second subset of commands can be executed on a different block than the block used to execute the write commands associated with test mode.

[0081] Aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, the instructions, when executed by a controller (e.g., memory system controller 115), may cause the controller to perform the operation of process flow 300.

[0082] Figure 4 An example of a process flow 400 supporting techniques for command sequence adjustment, as disclosed herein, is shown. Process flow 400 may be provided by a memory system (e.g., reference...). Figure 1 and 2 The components of the described memory system 110) are executed. For example, process flow 400 can be executed by the controller of the host system, such as as described in the reference. Figure 1 The host system controller 106 is described. Process flow 400 can be implemented to reduce latency and power consumption and increase system performance, as well as to achieve other benefits. Aspects of process flow 400 can be implemented by the controller and other components. Alternatively, aspects of process flow 400 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system controller 115 or local controller 135). For example, if these instructions are executed by the controller (e.g., memory system controller 115, local controller 135), they can cause the controller to perform the operation of process flow 400. In the following description of process flow 400, operations can be performed in a different order than those shown. For example, specific operations can be omitted from process flow 400, or other operations can be added to process flow 400.

[0083] At position 405, a command set can be stored. For example, the host system can use a first sequence in a queue, such as a host system queue, to store the command set. For example, if the command set contains six commands (i.e., commands one through six), the first sequence can indicate that the first command will be issued to the memory system, followed by the second command (e.g., after the first command), then the third command, and so on, until every command in the command set has been issued to the memory system.

[0084] At 410, it can be determined whether a subset of the command set is part of a test mode for the memory system. For example, the host system can determine whether the subset of commands is a write command associated with a test mode (e.g., a benchmarking mode) used to measure the performance of the memory system, such as write speed or read performance, and other instances. The test mode may include executing a number of write commands to write a target test file to a newly opened memory block, reading back the target test file one or more times (e.g., three times) to calculate average sequential read performance, and rewriting (e.g., overwriting) the target test file one or more times (e.g., three times) to calculate average sequential write performance.

[0085] In some cases, the host system can determine whether a subset of commands is part of a test pattern by determining whether each command in the subset is a write command associated with data of the same size. In a non-restrictive instance, as part of writing to the target test file, the host system may issue one or more write commands to write to the target test file using a common chunk size (e.g., a 512KB chunk size). Therefore, if the host system detects that each command in the subset indicates data of the same size to be written, the host system can determine that the subset of commands is part of a test pattern.

[0086] In some cases, it can be determined at 410 that commands in a subset of the command set are not part of the test mode. Therefore, at 415, the command set can be issued to the memory system. For example, the host system can issue the command set according to the first sequence.

[0087] At 420, if it is determined that commands in a subset of the command set are part of a test mode, a second sequence of the command set can be configured. For example, the host system can configure the second sequence by adjusting the order of the first sequence (e.g., the order in which the command set will be issued). In some cases, the second sequence can indicate that the LBAs of each command in the subset of commands are consecutive (e.g., the LBA of the first command to be issued is lower than the LBA of the second command to be issued after the first command).

[0088] In a non-limiting instance, the command set may comprise four commands stored in a queue according to a first sequence (e.g., storing the first command through the fourth command sequentially). The first command may indicate an LBA of 0 to 127 (e.g., the first command may have a block size of 512 KB), the second command may indicate an LBA of 256 to 383 (e.g., the second command may have a block size of 512 KB), the third command may indicate an LBA of 10240 and have a block size of 4 KB, and the fourth command may indicate an LBA of 128 to 255 (e.g., the fourth command may have a block size of 512 KB).

[0089] Because the first, second, and fourth commands each indicate the same data size (e.g., a 512KB chunk size), the host system can determine that the first, second, and fourth commands are part of a test mode. Therefore, the host system can use a second sequence to configure the order in which the commands are stored in the queue, such that the order indicates that the first command will be issued, followed by the fourth command (e.g., because the LBA of the fourth command follows the first command), then the second command, and then the third command. In other words, the host system can reorder a subset of commands such that the LBA of a command is equal to the LBA of the previous command plus the chunk size of the previous command.

[0090] At 425, a subset of commands may be issued. For example, the host system may issue a subset of commands to the memory system in the order indicated by the second sequence (e.g., configured at 420). In some cases, the host system may also issue a second subset of commands (e.g., commands in the command set that are not part of the test mode). The second subset of commands may be issued after the first subset of commands, as indicated by the second sequence.

[0091] Various aspects of process flow 400 may be implemented by a controller and other components. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, when executed by a controller (e.g., host system controller 106), the instructions may cause the controller to perform the operation of process flow 400.

[0092] Figure 5 A block diagram 500 illustrates a memory system 520 that supports techniques for command sequence adjustment based on examples disclosed herein. The memory system 520 may be as described in the references... Figures 1 to 4 Examples of aspects of the described memory system. Memory system 520 or its various components may be examples of constructs for performing various aspects of the techniques for command sequence adjustment as described herein. For example, memory system 520 may include command manager 525, queue manager 530, test mode manager 535, sequence component 540, write manager 545, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0093] Command manager 525 may be configured or otherwise supported to include components for receiving command sets at a memory system. Queue manager 530 may be configured or otherwise supported to include components for storing command sets in a queue based at least in part on a first sequence of received command sets. Test mode manager 535 may be configured or otherwise supported to include components for determining whether a subset of commands in the command set is associated with a test mode. Sequence component 540 may be configured or otherwise supported to include components for configuring a second sequence of command sets in a queue based at least in part on determining that a subset of commands is associated with a test mode, the second sequence being at least in part based on a corresponding logical address associated with each command of the subset of commands. In some instances, command manager 525 may be configured or otherwise supported to include components for executing a subset of commands according to a second sequence as part of a test mode.

[0094] In some instances, to support the configuration of a second sequence, the sequence component 540 may be configured or otherwise support a component for adjusting the order of a subset of commands in a queue such that a first logical address associated with a first command in the queue is less than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.

[0095] In some instances, to support a subset of commands to be executed, the write manager 545 may be configured or otherwise supported to write first data associated with at least one command of the subset of commands to a first block, based at least in part on determining that a subset of commands is associated with a test mode.

[0096] In some instances, the command manager 525 may be configured or otherwise support components for executing a second subset of commands in the command set, the second subset being different from the stated subset.

[0097] In some instances, to support a second subset of commands to be executed, the write manager 545 may be configured or otherwise support a component of a second block, distinct from the first block, for writing second data associated with at least one command of the second subset of commands to a memory cell.

[0098] In some instances, the command manager 525 may be configured or otherwise supported to include components for receiving unmapping commands that identify data associated with a subset of the command. In some instances, the command manager 525 may be configured or otherwise supported to include components for erasing first data from a first block, at least in part, based on the receipt of an unmapping command.

[0099] In some instances, a subset of commands may contain one or more write commands, each of which identifies the same size of data.

[0100] In some instances, the command manager 525 may be configured or otherwise supported to determine the termination of a test mode based at least in part on the number of thresholds for which a second subset of the command satisfies the command.

[0101] In some instances, determining the end of the test mode is further based, at least in part, on a second subset of the commands that include the unmapping command.

[0102] In some instances, determining which subset of commands in the command set is associated with the test pattern is based at least in part on the fact that the corresponding size of the data associated with each command in the subset meets a threshold.

[0103] In some instances, determining that a subset of commands in the command set is associated with a test pattern is at least in part based on the number of commands in the subset meeting a threshold.

[0104] Figure 6 A block diagram 600 illustrates a host system 620 that supports techniques for command sequence tuning based on examples disclosed herein. The host system 620 may be as described in the references... Figures 1 to 4 Examples of aspects of the described host system. Host system 620 or its various components may be examples of constructs for performing various aspects of the techniques for command sequence adjustment as described herein. For example, host system 620 may include queue manager 625, test mode component 630, sequence component 635, command manager 640, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0105] Queue manager 625 may be configured or otherwise supported for storing in a queue at the host system a set of commands for storing data in the memory system according to a first sequence. Test mode component 630 may be configured or otherwise supported for determining whether a subset of commands in the command set is associated with a test mode. Sequence component 635 may be configured or otherwise supported for configuring a second sequence of commands in the queue based at least in part on determining that a subset of commands is associated with a test mode, the second sequence being at least in part based on a corresponding logical address associated with each command of the subset of commands. Command manager 640 may be configured or otherwise supported for issuing a subset of commands to the memory system according to the second sequence.

[0106] In some instances, determining which subset of commands in the command set is associated with the test pattern is based at least in part on the fact that the corresponding size of the data associated with each command in the subset meets a threshold.

[0107] In some instances, to support the configuration of a second sequence, the sequence component 635 may be configured or otherwise support a component for adjusting the order of a subset of commands in a queue such that a first logical address associated with a first command in the queue is less than a second logical address associated with a second command in the queue, wherein the second command is configured to be executed after the first command according to the second sequence.

[0108] Figure 7 A flowchart illustrating an example disclosed herein shows a method 700 supporting techniques for command sequence adjustment. Operation of method 700 may be implemented by a memory system or its components as described herein. For example, operation of method 700 may be implemented by, as referenced... Figures 1 to 5 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0109] At 705, the method may include receiving a set of commands at the memory system. The operation of 705 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 705 may be provided by reference to [reference needed]. Figure 5 The command manager 525 described is executed.

[0110] At 710, the method may include storing a command set in a queue based at least in part on a first sequence of received command sets. The operation at 710 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 710 may be derived from references... Figure 5 The queue manager 530 described is executed.

[0111] At 715, the method may include determining whether a subset of commands in the command set is associated with a test mode. The operation at 715 can be performed according to examples disclosed herein. In some instances, aspects of the operation at 715 may be derived from references... Figure 5 The described test mode manager 535 is executed.

[0112] At 720, the method may include configuring a second sequence of command sets in a queue based at least in part on determining a subset of commands associated with a test mode, the second sequence being at least in part based on a corresponding logical address associated with each command of the subset of commands. The operation at 720 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 720 may be as described in references... Figure 5 The described sequence component 540 is executed.

[0113] At 725, the method may include executing a subset of commands according to a second sequence as part of a test mode. The operation of 725 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 725 may be as described in the references... Figure 5 The command manager 525 described is executed.

[0114] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a set of commands at a memory system; storing the set of commands in a queue according to a first sequence at least partially based on the received set of commands; determining whether a subset of commands in the set of commands is associated with a test mode; configuring a second sequence of commands in the queue, at least partially based on the determination that the subset of commands is associated with the test mode, the second sequence being at least partially based on a corresponding logical address associated with each command of the subset of commands; and executing the subset of commands according to the second sequence as part of the test mode.

[0115] In some instances of the method 700 and apparatus described herein, configuring the second sequence may include operations, features, circuitry, logic, components, or instructions for adjusting the order of a subset of commands in a queue such that a first logical address associated with a first command in the queue may be less than a second logical address associated with a second command in the queue, wherein the second command may be executed according to the second sequence after the first command.

[0116] In some instances of the method 700 and apparatus described herein, the subset of commands executed may include operations, features, circuit systems, logic, components, or instructions for writing first data associated with at least one command of the subset of commands into a first block, at least in part based on determining that the subset of commands may be associated with a test mode.

[0117] Some instances of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for executing a second subset of commands in the command set, the second subset being different from the stated subset.

[0118] In some instances of the method 700 and apparatus described herein, the second subset of commands may include operations, features, circuitry, logic, components, or instructions for writing second data associated with at least one command of the second subset of commands into a second block of memory cells, distinct from the first block.

[0119] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: receiving an unmapping command that identifies data associated with a subset of the command; and erasing first data from a first block based at least in part on receiving the unmapping command.

[0120] In some instances of the method 700 and device described herein, a subset of commands comprises one or more write commands, each of which identifies data of the same size.

[0121] Some instances of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for determining an end-test mode based at least in part on the number of thresholds for which a second subset of the command satisfies the command.

[0122] Some instances of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for determining the end test mode, which may further be based at least in part on a second subset of commands including unmapping commands.

[0123] Some instances of the method 700 and device described herein may further include operations, features, circuit systems, logic, components, or instructions for determining a subset of commands in a command set that may be associated with a test mode and that satisfy a threshold at least in part based on the corresponding size of the data associated with each command in the subset.

[0124] Some instances of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining a subset of commands in a command set that may be associated with a test mode and that at least in part based on the number of commands in the subset satisfying a threshold.

[0125] Figure 8 A flowchart illustrating an example disclosed herein shows a method 800 supporting techniques for command sequence adjustment. The operation of method 800 can be implemented by a host system or its components as described herein. For example, it can be implemented by, as referenced... Figures 1 to 4 The host system described in section 6 performs the operation of method 800. In some instances, the host system may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0126] At 805, the method may include storing a set of commands for storing data in a queue at the host system according to a first sequence at the memory system. The operation of 805 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 805 may be provided by reference to [reference needed]. Figure 6 The queue manager 625 described is executed.

[0127] At 810, the method may include determining whether a subset of commands in the command set is associated with a test mode. The operation at 810 may be performed according to examples disclosed herein. In some instances, aspects of the operation at 810 may be as described in references... Figure 6 The described test mode component 630 is executed.

[0128] At 815, the method may include configuring a second sequence of commands in a queue based at least in part on determining a subset of commands associated with a test mode, the second sequence being at least in part based on a corresponding logical address associated with each command of the subset of commands. The operation of 815 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 815 may be as described in references... Figure 6 The described sequence component 635 is executed.

[0129] At 820, the method may include issuing a subset of commands to a memory system according to a second sequence. The operation of 820 may be performed according to examples disclosed herein. In some instances, aspects of the operation of 820 may be as described in references... Figure 6 The command manager 640 described is executed.

[0130] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing a set of commands in a queue at a host system for storing data in a memory system according to a first sequence; determining whether a subset of commands in the command set is associated with a test mode; configuring a second sequence of the command set in the queue based at least in part on the determination that the subset of commands is associated with the test mode, the second sequence being based at least in part on a corresponding logical address associated with each command of the subset of commands; and issuing the subset of commands to the memory system according to the second sequence.

[0131] Some instances of the methods 800 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining a subset of commands in a command set that may be associated with a test mode and that satisfy a threshold based at least in part on the corresponding size of the data associated with each command in the subset.

[0132] In some instances of the method 800 and device described herein, configuring the second sequence may include operations, features, circuitry, logic, components, or instructions for adjusting the order of a subset of commands in a queue such that a first logical address associated with a first command in the queue may be less than a second logical address associated with a second command in the queue, wherein the second command may be configured to be executed according to the second sequence after the first command.

[0133] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0134] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0135] The terms “electronic connectivity,” “conductive contact,” “connection,” and “coupling” refer to the relationship between components that supports the flow of signals between them. Components are considered to be electronically connected (conductively contacted, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any time. At any given time, based on (e.g., in response to) the operation of a device containing the connected components, the conductive path between components that are electronically connected (or conductively contacted, connected, or coupled) to each other can be open or closed. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0136] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via conductive paths, while in a closed-circuit relationship, signals can be transmitted between components via conductive paths. If a component, such as a controller, couples other components together, then that component begins to allow the change of signal flow between the other components via conductive paths that were previously not permitted.

[0137] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0138] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0139] The term "in response to" can refer to a condition or action occurring at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0140] Additionally, the terms "directly responding to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action.

[0141] In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" this other condition or action.

[0142] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0143] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0144] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0145] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, without regard to the second reference numeral.

[0146] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distribution such that different parts of the functionality are implemented in different physical locations.

[0147] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0148] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0149] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0150] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device for adjusting command sequences, comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to: Receive command sets at the memory system; The command set is stored in a queue based at least in part on a first sequence of received commands; Determining whether a subset of commands in the command set is associated with a test mode, wherein determining that the subset of commands is associated with the test mode is based at least in part on the corresponding size of the data associated with each command in the subset of commands; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; as well as As part of the test mode, the subset of commands executed according to the second sequence.

2. The device of claim 1, wherein the second sequence is configured to cause the device to: The order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is less than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.

3. The device of claim 1, wherein the subset of commands executed is configured to cause the device to: First data associated with at least one command of the subset of commands is written into the first block, based at least in part on the association of the subset of commands with the test mode.

4. The device of claim 3, wherein the controller is further configured to cause the device to: Execute a second subset of commands from the command set, the second subset being different from the first subset.

5. The device of claim 4, wherein the second subset of the execution commands is configured to cause the device to: Second data associated with at least one command of the second subset of commands is written to a second block of memory cells, different from the first block.

6. The device of claim 1, wherein the subset of commands includes one or more write commands, each of the one or more write commands identifying data of the same size.

7. The device of claim 1, wherein determining that a subset of commands in the command set is associated with the test mode is based at least in part on the fact that the corresponding size of the data associated with each command in the subset satisfies a threshold.

8. The device of claim 1, wherein determining that a subset of commands in the command set is associated with the test mode is based at least in part on the number of commands in the subset satisfying a threshold.

9. A device for command sequence adjustment, comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to: Receive command sets at the memory system; The command set is stored in a queue based at least in part on a first sequence of received commands; Determine whether a subset of commands in the command set is associated with a test mode; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; As part of the test mode, the subset of commands is executed according to the second sequence; First data associated with at least one command of the subset of commands is written into the first block, based at least in part on the association of the subset of commands with the test mode. Receive an unmapping command that identifies data associated with the subset of the command; as well as The first data is erased from the first block at least in part based on receiving the unmapping command.

10. A device for command sequence adjustment, comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to: Receive command sets at the memory system; The command set is stored in a queue based at least in part on a first sequence of received commands; Determine whether a subset of commands in the command set is associated with a test mode; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; As part of the test mode, the subset of commands is executed according to the second sequence; as well as The test mode is terminated at least in part based on the number of times a second subset of the command satisfies the command's threshold.

11. The device of claim 10, wherein determining to end the test mode further, at least in part, based on the second subset of commands, includes a cancel mapping command.

12. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive command sets at the memory system; The command set is stored in a queue based at least in part on a first sequence of received commands; Determining whether a subset of commands in the command set is associated with a test mode, wherein determining that the subset of commands is associated with the test mode is based at least in part on the corresponding size of the data associated with each command in the subset of commands; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; as well as As part of the test mode, the subset of commands executed according to the second sequence.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions for configuring the second sequence are executable by the processor to: The order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is less than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.

14. The non-transitory computer-readable medium of claim 12, wherein the instructions of the subset for executing the commands are executable by the processor to: First data associated with at least one command of the subset of commands is written into the first block, based at least in part on the association of the subset of commands with the test mode.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to execute a second subset of commands in the command set, the second subset being different from the first subset.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions of the second subset for executing the commands are executable by the processor to: Second data associated with at least one command of the second subset of commands is written to a second block of memory cells, different from the first block.

17. The non-transitory computer-readable medium of claim 12, wherein the subset of commands includes one or more write commands, each of the one or more write commands identifying data of the same size.

18. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, further cause the electronic device to: Receive command sets at the memory system; The command set is stored in a queue based at least in part on a first sequence of received commands; Determine whether a subset of commands in the command set is associated with a test mode; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; As part of the test mode, the subset of commands is executed according to the second sequence; First data associated with at least one command of the subset of commands is written into the first block, based at least in part on the association of the subset of commands with the test mode. as well as Receive an unmapping command that identifies data associated with the subset of the command; as well as The first data is erased from the first block at least in part based on receiving the unmapping command.

19. A method for adjusting a command sequence, comprising: Receive command sets at the memory system; The command set is stored in a queue based at least in part on a first sequence of received commands; Determining whether a subset of commands in the command set is associated with a test mode, wherein determining that the subset of commands is associated with the test mode is based at least in part on the corresponding size of the data associated with each command in the subset of commands; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; as well as As part of the test mode, the subset of commands executed according to the second sequence.

20. The method of claim 19, wherein configuring the second sequence comprises: The order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is less than a second logical address associated with a second command in the queue, wherein the second command is executed according to the second sequence after the first command.

21. The method of claim 19, wherein the subset of commands executed comprises: First data associated with at least one command of the subset of commands is written into the first block, based at least in part on the association of the subset of commands with the test mode.

22. The method of claim 21, further comprising: Execute a second subset of commands from the command set, the second subset being different from the first subset.

23. A device for adjusting command sequences, comprising: A controller, configured to be coupled to a memory system, wherein the controller is configured to cause the device to: A set of commands for storing data in the memory system according to a first sequence is stored in a queue at the host system. Determining whether a subset of commands in the command set is associated with a test mode, wherein determining that the subset of commands is associated with the test mode is based at least in part on the corresponding size of the data associated with each command in the subset of commands; A second sequence of the command set is configured in the queue based at least in part on the association of the subset of commands with the test mode, the second sequence being based at least in part on the corresponding logical address associated with each command of the subset of commands; as well as The subset of commands is issued to the memory system according to the second sequence.

24. The device of claim 23, wherein determining that a subset of commands in the command set is associated with the test mode is based at least in part on the fact that the corresponding size of the data associated with each command in the subset satisfies a threshold.

25. The device of claim 23, wherein the second sequence is configured to cause the device to: The order of the subset of commands in the queue is adjusted such that a first logical address associated with a first command in the queue is less than a second logical address associated with a second command in the queue, wherein the second command is configured to be executed according to the second sequence after the first command.

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