Superconducting quantum chip, its substrate, and method for manufacturing the substrate

Abstract

An embodiment of the present application provides a superconducting quantum chip, its substrate, and a method for manufacturing the substrate, which are used to reduce the effect of chip crosstalk at low cost. The method for manufacturing the substrate includes: fabricating a through-hole on the main body of the chip substrate; performing film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the through-hole and the surface of the main body of the chip substrate, where the surface includes an upper surface and a lower surface; performing metal electroplating treatment on the main body of the chip substrate that has undergone film sputtering treatment to form a metal column filling the through-hole and a metal plating layer covering the upper surface of the main body of the chip substrate; performing smoothing treatment on the surface of the main body of the chip substrate that has undergone metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate, thereby forming the substrate of the superconducting quantum chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of quantum chip manufacturing, and in particular, to a superconducting quantum chip, its substrate, and a method for manufacturing the substrate. Background Art

[0002] Quantum computing is a new computing mode that regulates quantum information units according to the laws of quantum mechanics for computing. In contrast to traditional general-purpose computers, its theoretical model is the universal Turing machine. For general quantum computing, its theoretical model is the universal Turing machine reinterpreted by the laws of quantum mechanics. From the perspective of computable problems, quantum computers can only solve the problems that traditional computers can solve. However, in terms of computing efficiency, due to the existence of quantum mechanical superposition, some known quantum algorithms are faster than traditional general-purpose computers when dealing with problems.

[0003] Since the processing technology of superconducting quantum chips is similar to that of traditional semiconductors, it is considered to be one of the most promising platforms for realizing quantum computing. However, in recent years, with the sharp increase in the number of superconducting quantum bits, the volume of the substrate of the required superconducting quantum chips has become larger and larger. The substrate, as a rectangular resonator, will generate a TM110 resonance mode. For example, when the side length of the substrate reaches 0.85 cm, the frequency is about 7.8 GHz. Since the frequencies of commonly used superconducting quantum bits are between 4 - 8 GHz, if the resonance mode of the substrate is within this range, it will bring relatively large electromagnetic crosstalk.

[0004] The prior art adopts a superconducting through-silicon via (TSV) process to solve the problem of electromagnetic crosstalk in chips. Specifically, via holes are made in the main body of the chip substrate to form through holes, and then a layer of superconducting metal is plated in the through holes by a special process to disrupt the electric field distribution on the main body of the chip substrate and push up the cavity film, thereby reducing electromagnetic crosstalk to a certain extent. However, this method has a high cost. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a superconducting quantum chip, its substrate, and a method for manufacturing the substrate that can overcome or at least partially solve the above problems.

[0006] In a first aspect, the present invention provides a method for manufacturing a substrate of a superconducting quantum chip, including:

[0007] Making through holes in the main body of the chip substrate;

[0008] Performing film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the through hole and the surface of the main body of the chip substrate, where the surface includes the upper surface and the lower surface;

[0009] Perform metal electroplating on the main body of the chip substrate that has undergone film sputtering treatment to form metal pillars filling the through holes and a metal plating layer covering the upper surface of the main body of the chip substrate;

[0010] Perform smoothing treatment on the surface of the main body of the chip substrate that has undergone metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate, forming the substrate of the superconducting quantum chip.

[0011] Optionally, before fabricating the through holes on the main body of the chip substrate, the method further includes:

[0012] Clean the surface of the main body of the chip substrate using an organic solvent to remove the surface attachments on the surface of the main body of the chip substrate.

[0013] Optionally, fabricating the through holes on the main body of the chip substrate includes:

[0014] Fabricate the through holes on the main body of the chip substrate using laser-induced etching technology, where the width of the through holes meets the target width.

[0015] Optionally, after fabricating the through holes on the main body of the chip substrate, the method further includes:

[0016] Perform thinning treatment on the main body of the chip substrate using a thinning process to make the thickness of the main body of the chip substrate meet the target thickness;

[0017] Perform polishing treatment on the main body of the chip substrate after the thinning treatment to make the surface smoothness of the main body of the chip substrate meet the target smoothness.

[0018] Optionally, performing film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the through holes and the surface of the main body of the chip substrate includes:

[0019] Perform sputtering treatment of the metal film layer on the surface of the main body of the chip substrate and the inner wall of the through holes respectively using magnetron sputtering technology to form a barrier layer on the inner wall of the through holes and the surface of the main body of the chip substrate;

[0020] After the barrier layer is formed on the inner wall of the through holes and the surface of the main body of the chip substrate, grow a seed layer on the inner wall of the through holes and the surface of the main body of the chip substrate so that the seed layer covers the barrier layer; where the metal film layer includes the barrier layer and the seed layer.

[0021] Optionally, the smoothing process for the surface of the main body of the chip substrate that has undergone metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate includes:

[0022] Perform aluminum layer electroplating treatment on the main body of the chip substrate using an organic solvent to fill aluminum into the through holes to form aluminum pillars, and cover the upper surface of the main body of the chip substrate with the aluminum to form the metal plating layer, where the metal pillars are the aluminum pillars.

[0023] Optionally, the smoothing process for the surface of the main body of the chip substrate that has undergone metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate includes:

[0024] Perform metal electroplating treatment on the main body of the chip substrate using an electroplating process to fill copper or gold into the through holes to form copper pillars or gold pillars, and cover the upper surface of the main body of the chip substrate with the copper and the gold to form the metal plating layer, where the metal pillars are the copper pillars or gold pillars.

[0025] Optionally, the smoothing process for the surface of the main body of the chip substrate that has undergone metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate to form the substrate of the superconducting quantum chip includes:

[0026] Perform etching treatment on the main body of the chip substrate using wet etching to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate;

[0027] Perform polishing treatment on the surface of the main body of the chip substrate after the etching treatment using a chemical mechanical polishing process to make the surface of the main body of the chip substrate smooth and make the thickness of the main body of the chip substrate meet the target thickness.

[0028] Optionally, the main body of the chip substrate at least includes quartz glass.

[0029] In a second aspect, the present invention provides a substrate for a superconducting quantum chip, the substrate includes a main body and through holes penetrating the upper and lower surfaces of the main body, the inner walls of the through holes are covered with a metal film layer, and the through holes covered with the metal film layer are filled with metal pillars, the metal film layer at least includes a seed layer and a barrier layer, where the seed layer covers the barrier layer, the barrier layer is located between the inner wall of the through hole and the seed layer, and the main body is at least made of quartz glass.

[0030] Optionally, the metal film layer at least includes a seed layer and a barrier layer. The seed layer is a metal film layer containing copper, and the barrier layer is a metal film layer containing tantalum.

[0031] Optionally, the substrate of the superconducting quantum chip provided in the second aspect is fabricated by the fabrication method described in the first aspect.

[0032] In a third aspect, the present invention provides a superconducting quantum chip, which includes a substrate of the superconducting quantum chip, a superconducting metal bottom film covering the upper surface of the substrate, and a circuit structure disposed on the superconducting metal bottom film, wherein the substrate of the superconducting quantum chip is the substrate described in the second aspect.

[0033] From the above technical solutions, it can be seen that the present invention has the following advantages: making through-holes on the main body of the chip substrate; performing film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the through-holes and the surface of the main body of the chip substrate, wherein the surface includes the upper surface and the lower surface; performing metal electroplating treatment on the main body of the chip substrate after the film sputtering treatment to form metal columns filled in the through-holes and a metal plating layer covering the upper surface of the main body of the chip substrate; performing smoothing treatment on the surface of the main body of the chip substrate after the metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate, thereby forming the substrate of the superconducting quantum chip. In the embodiments of the present application, a through-hole structure is formed on the main body of the chip substrate, and metal is filled in the through-hole part, which can effectively suppress crosstalk, and the thickness and structure of the main body of the chip substrate can be selected according to actual needs. At the same time, since the main body of the chip substrate has a lower cost compared to the silicon substrate and the processing process is simple, the cost can also be effectively reduced. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings.

[0035] Figure 1 It is a process step diagram of the fabrication method of the substrate of the superconducting quantum chip disclosed in the present invention;

[0036] Figure 2 It is another process step diagram of the fabrication method of the substrate of the superconducting quantum chip disclosed in the present invention;

[0037] Figure 3 It is yet another process step diagram of the fabrication method of the substrate of the superconducting quantum chip disclosed in the present invention;

[0038] Figure 4 This is a flowchart of a method for fabricating a substrate of a superconducting quantum chip disclosed by the present invention;

[0039] Figure 5 This is another flowchart of a method for fabricating a substrate of a superconducting quantum chip disclosed by the present invention. Detailed implementation manners

[0040] Due to the similar processing technology between superconducting quantum chips and traditional semiconductors, superconducting quantum chips are considered to be one of the most promising platforms for realizing quantum computing. However, in recent years, with the sharp increase in the number of qubits of superconducting quantum, the main volume of the required chip substrate has become larger and larger. Since the qubit frequencies of commonly used superconducting quantum are in the range of 4 - 8 GHz, it will bring relatively large electromagnetic crosstalk and affect the performance of quantum chips.

[0041] The prior art proposes to use superconducting TSVs to solve the chip crosstalk problem. Specifically, through-hole processing is mainly performed on the main body of the chip substrate, and then a layer of metal (superconducting metal or non-superconducting metal) is plated in the through-holes by a special process, which can disrupt the electric field distribution on the substrate and push up the cavity membrane. Since the cavity membrane is positively correlated with the frequency, increasing the cavity membrane can correspondingly increase the frequency, thereby achieving the effect of reducing crosstalk. However, the price advantage of silicon wafers is not obvious and the cost is relatively high.

[0042] Another prior art solution is to use a special sample box to solve the chip electromagnetic crosstalk problem. Metal columns are formed on the sample box itself, and holes are drilled at the positions corresponding to the metal columns on the substrate of the superconducting quantum chip. After the two are assembled together (the holes on the substrate of the superconducting quantum chip are sleeved on the metal columns), it can play a role in pushing up the mold cavity and suppressing the electromagnetic crosstalk of the chip. However, the crosstalk problem of the chip itself has not been solved, and it is difficult to achieve general expansion due to excessive dependence on the special sample box.

[0043] Since both of the above two solutions have problems, accordingly, the embodiments of the present application provide a method for fabricating a substrate of a superconducting quantum chip, which is used to reduce the electromagnetic crosstalk of the chip at low cost.

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0045] Please refer to Figures 1 to 3 , Figures 1 to 3 Both are process step diagrams of a method for fabricating a substrate of a superconducting quantum chip disclosed by the present invention. For convenience of description, Figure 1The three small process steps included are named step a, step b, and step c from left to right, Figure 2 The three small process steps included are named step d, step e, and step f from left to right, Figure 3 The small process step included is named step g. It is not difficult to understand that, in the order of execution of the process steps, they are step a, step b, step c, step d, step e, step f, and step g in sequence. That is to say, steps a to g together constitute a manufacturing method of the substrate of the superconducting quantum chip. It should be noted that, Figures 1 to 2 In any one of the process steps, the rectangular diagram located above is the cross-sectional view of the main body of the chip substrate, and the rectangular diagram located below is the top view of the main body of the chip substrate. Figure 3 In process step g, the rectangular diagram located above is the cross-sectional view of the substrate of the superconducting quantum chip, and the rectangular diagram located below is the top view of the substrate of the superconducting quantum chip. For the convenience of understanding, it will not be elaborated further hereafter.

[0046] For step a, this diagram can be understood as preparing the main body of the chip substrate in advance. Preferably, the main body of the chip substrate can be made of one or more semiconductor materials. Among them, the semiconductor materials include but are not limited to silicon Si, silicon dioxide SiO 2 etc. Of course, in this manufacturing process, the main body of the chip substrate can also be made of other suitable insulating materials, such as quartz glass. Since the price and production capacity of quartz glass are far superior to those of semiconductor materials, therefore, the superconducting quantum chip manufactured by this process has a greater price advantage, so quartz glass can be selected as the substrate material of the superconducting quantum chip. For the convenience of description, the subsequent description of the main body of the chip substrate will be specifically described in detail with a quartz glass substrate.

[0047] In the process step shown in step a, prepare a quartz glass substrate (i.e., the main body of the above-mentioned chip substrate) in advance. To make the thickness of the main body of the final superconducting quantum chip substrate meet the target thickness, the thickness of the quartz glass substrate can be slightly higher than the target thickness. For example, if the target thickness is 300 μm, the thickness of the quartz glass substrate can be between 330 - 350 μm. Optionally, the quartz glass substrate can be cleaned to remove impurities on the surface of the quartz glass substrate.

[0048] According to step b, through holes can be made on the quartz glass substrate by laser modification and wet etching. Of course, the method for making through holes is not limited to the method described above and can also be other methods. It is not difficult to understand from the cross-sectional view of the main body of the chip substrate in step b that the through hole completely penetrates the quartz glass substrate. In order to make the superconducting quantum chip achieve the target performance as much as possible, the through hole needs to meet a certain depth-to-width ratio. For example, it has been found through experiments that the performance of the superconducting quantum chip meets the target performance when the depth-to-width ratio is 6:1. Therefore, under the condition that the thickness (depth) of the quartz glass substrate is selected to be 300μm, the diameter of the through hole can be selected to be 50μm. Of course, in practical applications, the depth-to-width ratio can also be other ratios to meet other performances.

[0049] Therefore, a specific embodiment is: a through hole with a depth-to-width ratio of 6:1 is made on a quartz glass substrate by laser modification and wet etching, wherein the width of the through hole can be set to 50 μm.

[0050] According to step c, the quartz glass substrate can be thinned by a thinning process, so that the quartz glass substrate is thinned to the target thickness as much as possible, and then the quartz glass substrate is surface polished to improve the surface smoothness of the quartz glass substrate. Of course, the thinning process step is not necessary. If the quartz glass substrate meets the target thickness, it is not necessary to thin it.

[0051] Therefore, a specific embodiment is: thinning and polishing are performed on the quartz glass substrate by thinning process and surface polishing, so as to thin the quartz glass substrate to a target thickness as much as possible, for example, thinning the quartz glass substrate to a thickness of 300 μm.

[0052] According to step d, metal sputtering is performed on the inner wall of the through hole of the quartz glass substrate and the surface of the quartz glass substrate (wherein the surface includes the upper surface and the lower surface) by means of, but not limited to, film layer sputtering, so that a metal film layer grows on the inner wall of the through hole and the surface of the quartz glass substrate. It can be understood that, from the cross-sectional view of the main body of the chip substrate in step d, it can be seen that there are at least two layers of metal film layers on the inner wall of the through hole and the surface of the quartz glass substrate, wherein the inner layer is a barrier layer and the outer layer is a seed layer. That is, the seed layer covers the barrier layer, and the barrier layer is located between the inner wall of the through hole and the seed layer. Compared with the top view of the main body of the chip substrate in step c, it can be seen from the top view of the main body of the chip substrate in step d that the surface of the quartz glass substrate appears gray, which means that the surface of the quartz glass substrate is covered with a seed layer.

[0053] Therefore, a specific embodiment is: performing metal sputtering treatment on the quartz glass substrate by film sputtering to first grow a barrier layer on the inner wall of the through hole and the surface of the quartz glass substrate, and then grow a seed layer, wherein the metal film layer at least includes a barrier layer and a seed layer.

[0054] According to step e, the inner wall of the through hole and the upper surface of the quartz glass substrate are electroplated by, but not limited to, a metal electroplating process, so as to fill the inner wall of the through hole with metal to form a metal column filled in the through hole. At the same time, the metal is filled onto the seed layer on the upper surface of the quartz glass substrate, so as to form a metal coating covering the seed layer. It can be understood that, compared with the cross-sectional view of the main body of the chip substrate in step d, from the cross-sectional view of the main body of the chip substrate in step e, it can be seen that there is a dark black layer on the inner wall of the through hole and the upper surface of the quartz glass substrate in step e, which is the metal column or metal coating formed after electroplating. Compared with the top view of the main body of the chip substrate in step d, from the top view of the main body of the chip substrate in step e, it can be seen that the color of the upper surface of the quartz glass substrate in step e is significantly darker than that of the quartz glass substrate in step d. It is not difficult to understand that the layer covered on the quartz glass substrate in step e at this time is the metal coating.

[0055] Therefore, a specific embodiment is: a metal coating covering the metal film layer and a metal column filling the through hole are electroplated on the upper surface of the quartz glass substrate by a metal electroplating process.

[0056] According to step f, the quartz glass substrate is processed by a wet etching and polishing process to remove the metal coating on the upper surface of the quartz glass substrate and the metal film layer on the surface of the quartz glass substrate, and then the quartz glass substrate is polished to improve the smoothness of the surface of the quartz glass substrate. Finally, the substrate of the superconducting quantum chip can be formed. It can be understood that, compared with the cross-sectional view of the main body of the chip substrate in step e, from the cross-sectional view of the main body of the chip substrate in step f, it can be seen that the surface of the quartz glass substrate in step f has removed the electroplated metal coating and the metal film layer after metal sputtering. At the same time, compared with the top view of the main body of the chip substrate in step e, from the top view of the main body of the chip substrate in step f, it can be seen that the dark black layer (i.e., the metal coating) has been removed from the quartz glass substrate in step f.

[0057] Therefore, a specific embodiment is: first, the metal coating on the upper surface of the quartz glass substrate, the metal film layer on the lower surface of the quartz glass substrate, and the metal film layer on the lower surface of the quartz glass substrate are removed by, but not limited to, a wet etching process, and then the surface of the quartz glass substrate is polished by, but not limited to, a polishing process, so that the upper surface and the lower surface of the quartz glass substrate are smooth. Finally, the substrate of the superconducting quantum chip is formed.

[0058] According to step g, the substrate of the superconducting quantum chip is processed by, but not limited to, processes such as magnetron sputtering or electron beam evaporation, so that at least one layer of superconducting metal bottom film grows on the upper surface of the substrate of the superconducting quantum chip. It can be understood that, compared with the cross-sectional view of the main body of the chip substrate in step f, from the cross-sectional view of the substrate of the superconducting quantum chip in step g, there is a gray layer on the upper surface of the substrate of the superconducting quantum chip in step g, where this gray layer is the superconducting metal bottom film grown by processes such as magnetron sputtering or electron beam evaporation. At the same time, compared with the top view of the main body of the chip substrate in step f, from the top view of the substrate of the superconducting quantum chip in step g, the upper surface of the substrate of the superconducting quantum chip in step g is covered with a gray layer (i.e., the superconducting metal bottom film).

[0059] Therefore, a specific embodiment is: growing at least one layer of superconducting metal bottom film on the substrate of the superconducting quantum chip by processes such as magnetron sputtering or electron beam evaporation, and making the superconducting metal bottom film cover the substrate of the superconducting quantum chip.

[0060] Through the above Figures 1 to 3 described process steps, a superconducting quantum chip with quartz glass as the substrate material can be fabricated, which has a more obvious price advantage compared with silicon wafers. Moreover, since a layer of superconducting metal bottom film is electroplated on the through holes, it can also effectively disrupt the electric field distribution on the substrate and push up the cavity film, thereby effectively reducing crosstalk and meeting the design requirements of the superconducting quantum chip.

[0061] For the convenience of understanding the above Figures 1 to 3 described process steps, please refer to Figure 4 , Figure 4 which is a flowchart of a method for fabricating a substrate of a superconducting quantum chip disclosed in the present invention, including step 401 - step 405.

[0062] 401. Fabricate through holes on the main body of the chip substrate.

[0063] After selecting to use quartz glass as the substrate of the superconducting quantum chip, it is necessary to fabricate through holes on the main body of the chip substrate. It is not difficult to understand that, from the main body of the chip substrate described above Figures 1 to 3 the main body of the chip substrate can be made of one or more semiconductor materials. Among them, the semiconductor material includes but is not limited to silicon Si, silicon dioxide SiO 2etc. Of course, in this manufacturing process, the main body of the chip substrate can also be made of other suitable insulating materials, such as fused quartz, etc. Since the price and production capacity of fused quartz are far superior to those of semiconductor materials, therefore, the substrate of the superconducting quantum chip fabricated by this process has a greater price advantage, so fused quartz can be selected as the substrate of the superconducting quantum chip. For the convenience of description, the subsequent description of the main body of the chip substrate will be specifically described in detail with a fused quartz substrate.

[0064] It is not difficult to understand that since there are no freely moving charges in the glass substrate material, thus, it has dielectric properties, low high-frequency loss, and good transmission characteristics, and is suitable for high-frequency applications. The glass through-via (TGV, through glass via) technology does not require the fabrication of an insulating layer, reducing the process complexity and processing cost. In some embodiments, vias that meet the design requirements can be fabricated on the fused quartz substrate.

[0065] In some embodiments, a method combining laser modification and wet etching can be used to quickly fabricate vias on the fused quartz substrate. Among them, the laser modification and wet etching method has high hole-forming accuracy and high processing efficiency. Specifically, first, laser-induced modification is performed at the positions where TGV vias need to be fabricated, and then the glass material at the modified positions is etched away through wet etching to form a TGV via array.

[0066] Based on the above embodiments, the aspect ratio of the vias can be set according to the usage requirements. In a specific embodiment, the aspect ratio of the vias can be designed to be greater than or equal to 6:1. Specifically, this is to ensure that the superconducting quantum chip can achieve optimal performance in the subsequent electroplating process. Of course, the via array can be determined according to the main body specifications of the chip substrate. When the aspect ratio does not exceed 6:1, the TGV holes are well metallized. As can be seen from the top view or cross-sectional view in Figures 1 to 3 , at this time, the via array shows a regular distribution. In another embodiment, the number or arrangement of the via arrays on the fused quartz substrate can also be not limited. It is not difficult to understand that the above is only a specific embodiment in the process of fabricating vias. For the above aspect ratio and via array, different aspect ratios or via array situations can also be designed according to the design requirements, and specific details are not limited here.

[0067] 402. Perform film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the via and the surface of the main body of the chip substrate.

[0068] After the through holes are formed on the quartz glass substrate, the quartz glass substrate can be subjected to film sputtering treatment. Specifically, film sputtering is mainly performed on the inner walls of the through holes of the quartz glass substrate and the surfaces (upper surface and lower surface) of the quartz glass substrate, so that corresponding metal films will also grow on the inner walls of the through holes and the surfaces of the quartz glass substrate. At the same time, it is also necessary to ensure that the inner walls of the through holes can be completely covered by the metal films.

[0069] In some embodiments, the metal films grown on the inner walls of the through holes and the surfaces of the quartz glass substrate at least include a barrier layer and a seed layer. Specifically, after the barrier layer is grown on the inner walls of the through holes and the surfaces of the quartz glass substrate through film sputtering treatment, the seed layer is grown on the basis of the barrier layer. Moreover, the barrier layer and the seed layer can completely cover the inner walls on both sides of the through holes, so as to wrap the quartz glass substrate between any two adjacent through holes. It is not difficult to understand that the seed layer covers the barrier layer at this time. That is, the seed layer covers the barrier layer, and the barrier layer is located between the inner wall of the through hole and the seed layer.

[0070] 403. Perform metal electroplating treatment on the main body of the chip substrate that has undergone film sputtering treatment to form metal pillars filled in the through holes and a metal plating layer covering the upper surface of the main body of the chip substrate.

[0071] After the metal film grows on the inner wall of the through hole of the quartz glass substrate, it is necessary to perform metal electroplating treatment on the quartz glass substrate, so as to fill the metal into the metal films (barrier layer and seed layer) on the inner wall of the through hole and the upper surface of the quartz glass substrate.

[0072] In some embodiments, an organic solution can be used for aluminum layer electroplating treatment to achieve the filling of the aluminum layer on the inner wall of the through hole. Finally, aluminum pillars (i.e., metal pillars containing aluminum) are formed on the inner wall of the through hole, and a metal film containing aluminum is formed on the upper surface of the quartz glass substrate.

[0073] Of course, in another embodiment, electroplating technology can also be used to perform metal electroplating treatment on the quartz glass substrate, so as to fill the metal onto the metal films (barrier layer and seed layer) filled in the above steps. Specifically, the metal is filled onto the upper surface of the quartz glass substrate and the inner wall of the through hole, and a metal plating layer covering the metal film is formed on the upper surface of the quartz glass substrate and metal pillars that completely fill the through holes. Based on this embodiment, the metal can be gold or copper. However, alternatively, in some embodiments, it can also be electroplated with other metals.

[0074] It should be noted that during the electroplating treatment process, at different electroplating times and current densities, the thickness of the grown metal plating layer will be different, and the corresponding polarization resistance will also be different.

[0075] 404. Smooth the surface of the main body of the chip substrate that has undergone metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate, forming the substrate of the superconducting quantum chip.

[0076] The metal film layer grown on the inner wall of the through hole or the metal column filled therein cannot exceed the surface of the quartz glass substrate. That is to say, the surface of the quartz glass substrate should be smooth and at the same horizontal plane. Therefore, after all the through holes are filled with metal plating, it is necessary to perform wet etching and polishing treatment on the quartz glass substrate to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate. It should be noted that the smoothing treatment described in this embodiment includes but is not limited to the wet etching and polishing treatment described above. Since the surface of the finally formed quartz glass substrate needs to be flat and smooth, the surface of the quartz glass substrate can be subjected to wet etching treatment to make the surface of the quartz glass substrate relatively flat, and then the surface of the quartz glass substrate can be polished to make the surface of the quartz glass substrate relatively smooth.

[0077] In one embodiment, first remove the excess metal film layer and metal plating layer on the surface of the quartz glass substrate by wet etching. Since there may be concave or convex parts on the surface of the quartz glass substrate after wet etching, it is necessary to polish the quartz glass substrate after wet etching to make the surface of the quartz glass substrate smooth.

[0078] Finally, after the quartz glass substrate has undergone wet etching and polishing treatment, the quartz glass substrate can be processed to form the substrate of the superconducting quantum chip.

[0079] A method for manufacturing a substrate of a superconducting chip disclosed in the present invention uses quartz glass as the substrate material, forms a through-hole structure on the main body of the chip substrate, and fills metal in the through-hole part, thereby effectively suppressing crosstalk. Moreover, the thickness of the quartz glass and the through-structure can be selected according to actual needs. At the same time, since the main body of the chip substrate has a lower cost compared to the silicon substrate and a simple processing technology, the cost can also be effectively reduced.

[0080] For the convenience of understanding the above Figures 1 to 3 process steps described, and Figure 4 the method flow described in Figure 5 , Figure 5 is a flowchart of another method for manufacturing a substrate of a superconducting quantum chip disclosed in the present invention, including steps 501 - step 509.

[0081] 501. Use an organic solvent to clean the surface of the main body of the chip substrate to remove the surface attachments on the main body of the chip substrate.

[0082] The material of the substrate of the superconducting quantum chip can be selected as, but not limited to, quartz glass. Taking the quartz glass substrate as an example, before manufacturing the superconducting quantum chip, an organic solvent can be used to clean the surface (upper surface and lower surface) of the quartz glass substrate to remove the surface attachments on the quartz glass substrate. For example, the organic solution can be a kind of organic solvent of tetrahydrofuran-benzene AlCl 3 +LiAlH 4 . Of course, an organic solvent containing other substances can also be selected, such as AlCl 3 -LiAlH 4 diethyl ether, AlBr 3 -MBr-benzene (toluene), etc., and specific details are not limited here.

[0083] In some embodiments, an organic reagent can be used to clean the fused quartz glass to remove surface contaminants. Specifically, the main material of the quartz glass at this time is silicon dioxide SiO 2 , and its content ratio is about 99.999%. The specific size structure can be a 2-inch wafer. Due to process machining errors, the thickness of the selected quartz glass substrate is approximately 330 - 350 μm at this time.

[0084] It is not difficult to understand that the material and size of the above quartz glass substrate are only for illustrative purposes, and other situations are also possible.

[0085] In some other embodiments, a pretreatment plan for degreasing and micro-etching can also be formulated in combination with the material characteristics of the quartz glass and the characteristics of the TGV process. Specifically, acetone is used for degreasing to remove the organic contamination on the surface of the quartz glass substrate, the chromic acid oxidation effect is utilized to remove the microscopic particles on the substrate surface, and a treatment process of soaking the substrate in 10% hydrofluoric acid for micro-etching is used to clean the surface of the quartz glass substrate again. It is not difficult to understand that the selected cleaning plan above is only for illustrative purposes, and other situations are also possible.

[0086] Based on the above embodiments, in order to improve the cleaning rate, uniformity, and the subsequent etching rate, 5% NH4F additive can also be added to the original 20% hydrofluoric acid solution and the water bath heating method at 40 °C can be adopted. This method can effectively improve the etching rate and uniformity of the subsequent wet etching, and can achieve batch processing of TGV through-holes. The through-hole rate is increased from less than 30% before to more than 99%. It is not difficult to understand that the selected cleaning plan above is only for illustrative purposes, and other situations are also possible.

[0087] It should be noted that other descriptions can refer to the description of step a, and will not be elaborated here.

[0088] 502. Use laser-induced and etching techniques to fabricate vias on the main body of the chip substrate.

[0089] In this embodiment, step 502 is similar to step 401 described above. Figure 4 Details are not elaborated here. It should be noted that a combination of laser-induced and wet etching can be used to fabricate vias.

[0090] In some embodiments, it is not difficult to understand that the aspect ratio of the vias at this time can also be other ratios, such as 7:1, 8:1, or 9:1, etc. There is no specific limitation here. For example, the aspect ratio can be low, but not too high, as an excessive aspect ratio will affect the fabrication of the seed layer during sputtering. Correspondingly, if the aspect ratio changes, the aperture of the vias needs to be adjusted adaptively, and there is no specific limitation here. Optimally, in this embodiment, the target aspect ratio of the selected vias is 6:1.

[0091] Based on the embodiment described in step 501 above, after wet etching the quartz glass substrate that has been laser-modified (laser-induced), ultrasonic cleaning with deionized water can be performed after etching to remove the residual hydrofluoric acid on the inner wall of the vias. It is not difficult to understand that the selected cleaning solution mentioned above is only for illustrative purposes, and other situations are also possible.

[0092] It should be noted that other explanations can refer to the description of step b, and will not be elaborated here.

[0093] 503. Process the main body of the chip substrate using a thinning process and a surface polishing process.

[0094] In some embodiments, after fabricating vias on the main body of the chip substrate, to make the thickness of the quartz glass substrate meet the target thickness, i.e., 300 μm, a thinning process needs to be used to thin the quartz glass substrate to the target thickness. Of course, the thinning process step is not necessary. If the quartz glass substrate meets the target thickness, it can be not thinned.

[0095] After the quartz glass substrate is processed using a wet etching process or a thinning process, the surface of the quartz glass substrate may exhibit non-uniformity. Additionally, due to the inherent non-uniformity of wet etching, there may be certain damage in local areas of the quartz glass substrate, namely the edges of the TGV holes, or there may be a phenomenon of "over-etching" on the substrate surface. Therefore, surface treatment processes such as polishing are required to improve the surface quality of the substrate and restore the uniform and micro-defect-free surface state of the quartz glass substrate. Or, the roughness does not meet the target roughness. Thus, in some embodiments, a surface polishing process (e.g., chemical mechanical polishing process) is required to polish the quartz glass substrate to improve the surface smoothness of the quartz glass substrate. It is not difficult to understand that the polishing process selected above is only for illustration, and there may be other situations.

[0096] It should be noted that other explanations can be referred to the description of step c, and will not be elaborated here.

[0097] 504. Use magnetron sputtering technology to perform sputtering treatment of metal film layers on the surface of the main body of the chip substrate and the inner wall of the through hole respectively, so that a barrier layer and a seed layer are formed on the inner wall of the through hole and the surface of the main body of the chip substrate.

[0098] In this embodiment, step 504 is similar to step 402 in the foregoing Figure 4 and will not be elaborated here specifically. However, it should be noted that in one of the embodiments, magnetron sputtering can be used to perform metal film layer sputtering on the surface (including the upper surface and the lower surface) of the quartz glass substrate and the inner wall of the through hole. Specifically, the metal film layer includes at least two layers, namely a barrier layer and a seed layer. Correspondingly, a barrier layer can be grown on the inner wall of the through hole and the surface of the quartz glass substrate first, and then a seed layer can be grown on the basis of the barrier layer. That is, the seed layer covers the barrier layer, and the barrier layer is located between the inner wall of the through hole and the seed layer.

[0099] In one embodiment, the material of the barrier layer can be tantalum metal, that is, the metal film layer corresponding to the barrier layer is a tantalum film, and the material of the seed layer can be copper metal, that is, the metal film layer corresponding to the seed layer is a copper film. It is not difficult to understand that in addition to the superconducting metals described above, other non-superconducting metal materials can also be used, and correspondingly, other superconducting metal materials can also be used, which will not be elaborated here specifically. Thus, it is ensured that the metal film layer on the inner wall of the through hole completely covers the surface of the quartz glass substrate. It is not difficult to understand that at this time, the copper film (seed layer) covers the tantalum film (barrier layer).

[0100] It should be noted that other explanations can be referred to the description of step d, and will not be elaborated here.

[0101] 505. The main body of the chip substrate is subjected to metal electroplating using an electroplating process to fill the through holes with metal to form metal pillars, and to cover the upper surface of the main body of the chip substrate with metal to form a metal coating.

[0102] In this embodiment, step 505 is similar to step 403 in the foregoing Figure 4 and will not be elaborated here specifically.

[0103] However, it should be noted that in some embodiments, an organic solution can be used for aluminum layer electroplating treatment to fill the aluminum layer (metal coating) on the inner wall of the through hole and the upper surface of the quartz glass substrate. Among them, the aluminum filled into the inner wall of the through hole will form a metal pillar containing aluminum (i.e., an aluminum pillar). It is not difficult to understand that the above-mentioned selected electroplating scheme is only for illustration, and there can be other situations.

[0104] In some other embodiments, an electroplating process can also be used to perform metal electroplating treatment on the quartz glass substrate, so as to fill copper or gold into the through holes to form copper pillars or gold pillars, and cover copper or gold on the upper surface of the main body of the said chip substrate to form a metal coating. Among them, the metal pillar is a copper pillar or a gold pillar, and moreover, the metal coating covers the metal film layer on the upper surface of the chip substrate. Based on this embodiment, the metal corresponding to the metal coating or the metal pillar can be gold or copper, etc. However, alternatively, in some implementation manners, it can also be electroplated with other metals. Specifically, it is not limited here.

[0105] It should be noted that for other descriptions, reference can be made to the description of step e, which will not be elaborated here.

[0106] 506. The main body of the chip substrate is etched using wet etching to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate.

[0107] Since in step 505, during the process of metal electroplating, there may be a situation of over-electroplating of the metal coating. At the same time, it is also necessary to remove the metal coating or metal film layer on the upper surface of the quartz glass substrate and the metal film layer on the lower surface of the quartz glass substrate. Therefore, in some embodiments, wet etching can be used to etch the surface (upper surface and lower surface) of the quartz glass substrate, so as to remove the metal coating (refer to step 505) and metal film layer (refer to step 504) covered on the upper surface of the quartz glass substrate and the metal film layer (refer to step 504) covered on the lower surface. It is not difficult to understand that the above-mentioned selected etching scheme is only for illustration, and there can be other situations.

[0108] 507. The surface of the main body of the chip substrate after etching treatment is polished by a chemical mechanical polishing process to make the surface of the main body of the chip substrate smooth and make the thickness of the main body of the chip substrate meet the target thickness.

[0109] Due to the certain non-uniformity of wet etching, there are certain damages at the edges of TGV holes in local areas of the quartz glass substrate or there is a certain "over-etching" phenomenon on the substrate surface. Therefore, it is necessary to improve the substrate surface quality through surface treatment processes such as chemical mechanical polishing process to restore the uniform and micro-defect-free surface state of the quartz glass substrate.

[0110] Specifically, in some embodiments, the surface of the quartz glass substrate is polished by a chemical mechanical polishing process to remove the metal film layers (including at least the barrier layer and the seed layer) and metal coatings that exceed the surface (upper surface and lower surface) of the quartz glass substrate in the through holes, so as to make the surface of the main body of the chip substrate smooth. At the same time, since the target thickness of the determined quartz glass substrate is 300 μm, thus, when the thickness of the quartz glass substrate in the above steps does not meet the target thickness, at this time, the quartz glass substrate can also be polished by a chemical mechanical polishing process to finely adjust the thickness of the quartz glass substrate, so that the thickness of the quartz glass substrate meets the target thickness.

[0111] Based on the above embodiments, the polishing pad is a porous polyurethane polishing pad, and the polishing liquid is SiO 2 polishing liquid, the abrasive particle size is relatively fine (nanometer level), and the alkaline SiO 2 colloid polishing has the typical characteristics of chemical mechanical polishing process to perform micro-polishing on the substrate surface. The SiO 2 abrasive particle suspension has good dispersibility and fluidity, can effectively remove the passivation film formed on the quartz glass surface, and at the same time cut the Si-O-Si bonds on the quartz glass surface through mechanical action. Since SiO 2 has low hardness, small particle size, and the silica sol is prone to gelation phenomenon, during the whole polishing process, the two effects of chemical reaction and mechanical friction alternate and cycle to perform micro and precise surface processing on the quartz glass substrate. It is not difficult to understand that the above selected polishing scheme is only for illustration, and there may be other situations.

[0112] It should be noted that other descriptions in steps 506 - 507 can refer to the description of step f, which will not be elaborated here.

[0113] Finally, after the quartz glass substrate undergoes wet etching and polishing treatment, the quartz glass substrate can be processed to form the substrate of the superconducting quantum chip.

[0114] 508. Grow a superconducting metal bottom film on the substrate of the superconducting quantum chip to grow a superconducting metal bottom film on the upper surface of the substrate of the superconducting quantum chip.

[0115] After the processing of the vias is completed, in order to enable good vertical interconnection performance between different vias, it is necessary to grow a superconducting metal bottom film on the substrate of the superconducting quantum chip to grow a superconducting metal bottom film on the upper surface of the substrate of the superconducting quantum chip, so that the vias on the substrate of the superconducting quantum chip form circuit connections.

[0116] Specifically, processes such as magnetron sputtering or electron beam evaporation can be used to grow a superconducting metal bottom film on the substrate of the superconducting quantum chip. It is not difficult to understand that the selected growth scheme above is only for illustrative purposes, and there can be other situations. Among them, the superconducting metal bottom film at least includes an aluminum film, a tantalum film or a niobium film.

[0117] Correspondingly, in some embodiments, if the metal electroplated in step 505 is aluminum, that is, the metal contained in the metal column is aluminum, the superconducting metal bottom film at least includes an aluminum film, a niobium film or a tantalum film. If the metal electroplated in step 505 is gold, that is, the metal contained in the metal column is gold, the superconducting metal bottom film at least includes a gold film, a tantalum film, a niobium film or a copper film. If the metal electroplated in step 505 is copper, that is, the metal contained in the metal column is copper, the superconducting metal bottom film at least includes a copper film, a niobium film or a tantalum film. In one embodiment, it can be understood that the metal contained in the superconducting metal bottom film is not affected by the metal contained in the substrate of the superconducting quantum chip.

[0118] It should be noted that for other descriptions, reference can be made to the description of step g, which will not be elaborated here.

[0119] 509. Perform chip processing on the substrate of the superconducting quantum chip on which the superconducting metal bottom film is grown to form a superconducting quantum chip.

[0120] After a superconducting metal bottom film is grown on the substrate of the superconducting quantum chip, corresponding chip processing can be performed on the substrate of the superconducting quantum chip, thereby forming a superconducting quantum chip.

[0121] It should also be noted that steps 508 - 509 can be understood as steps for processing the substrate of the superconducting quantum chip. In the steps of manufacturing the substrate of the superconducting quantum chip, steps 508 - 509 may not be executed, and specific details are not limited here.

[0122] This embodiment designs a manufacturing method for the main body of a superconducting quantum chip substrate with a relatively simple processing technology that can achieve crosstalk suppression. Using semiconductor processing technology, quartz glass is used as the substrate. After making vias by wet etching and laser drilling using the TGV process, superconducting metal is filled in the via part to achieve the purpose of suppressing crosstalk. Moreover, this manufacturing method can achieve crosstalk suppression of the substrate without a sample box, and the thickness of the quartz glass and the via structure can be selected according to actual needs. Compared with the TSV process, the TGV process has better microwave performance, can simplify the process and reduce parasitic capacitance, reduce electromagnetic interference of vias, and has a huge price advantage for glass wafers compared with silicon wafers of the same order of magnitude, and the processing technology is simple, so the cost is lower than that of silicon substrates.

[0123] The present invention also provides a substrate for a superconducting quantum chip, which includes but is not limited to the main body of the chip substrate and vias penetrating the upper and lower surfaces of the main body. The inner wall of the via is covered with a metal film layer, and a metal column is filled in the via covered with the metal film layer. The metal film layer includes at least a seed layer and a barrier layer, wherein the seed layer covers the barrier layer, and the barrier layer is located between the inner wall of the via and the seed layer, and the main body is quartz glass.

[0124] The present invention also provides a superconducting quantum chip, which includes the substrate for a superconducting quantum chip made by the above Figures 4 to 5 a superconducting metal bottom film, and a circuit structure provided on the superconducting metal bottom film.

[0125] As can be seen from the above description, a substrate for a superconducting quantum chip can be made by Figures 1 to 3 the process steps of the manufacturing method of a substrate for a superconducting quantum chip described above, or Figures 4 to 5 the method flow of the manufacturing method of a substrate for a superconducting quantum chip described above. In some other embodiments, it can also be made by other manufacturing methods, which will not be elaborated here specifically.

[0126] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0127] The features of the above embodiments are conducive to those with ordinary knowledge in the technical field to understand the embodiments of the present invention. Those with ordinary knowledge in the technical field should understand that the embodiments of the present invention can be used as a basis to design and vary other manufacturing processes and structures to achieve the same purpose and / or the same advantages as the above embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent substitutions do not depart from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. A manufacturing method of a substrate for a superconducting quantum chip, characterized in that, the method includes: using quartz glass as the chip substrate, with through holes penetrating the chip substrate, and the through holes are fabricated by the TGV process, and the TGV process includes a laser-induced etching technique; performing film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the through hole and the surface of the main body of the chip substrate, where the surface includes the upper surface and the lower surface, and the metal film layer at least includes a seed layer and a barrier layer, where the seed layer covers the barrier layer, and the barrier layer is located between the inner wall of the through hole and the seed layer; performing metal electroplating treatment on the main body of the chip substrate after the film sputtering treatment to form metal columns filling the through holes and a metal plating layer covering the upper surface of the main body of the chip substrate; performing a smoothing treatment on the surface of the main body of the chip substrate after the metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate, forming a substrate for a superconducting quantum chip; after fabricating through holes on the main body of the chip substrate, the method further includes: performing a thinning treatment on the main body of the chip substrate using a thinning process to make the thickness of the main body of the chip substrate meet the target thickness; performing a polishing treatment on the main body of the chip substrate after the thinning treatment to make the surface smoothness of the main body of the chip substrate meet the target smoothness; the performing film sputtering treatment on the main body of the chip substrate to grow a metal film layer on the inner wall of the through hole and the surface of the main body of the chip substrate includes: using a magnetron sputtering technique to perform sputtering treatment of the metal film layer on the surface of the main body of the chip substrate and the inner wall of the through hole respectively, so that a barrier layer is formed on the inner wall of the through hole and the surface of the main body of the chip substrate; when the barrier layer is formed on the inner wall of the through hole and the surface of the main body of the chip substrate, a seed layer is formed on the inner wall of the through hole and the surface of the main body of the chip substrate so that the seed layer covers the barrier layer; where the metal film layer includes the barrier layer and the seed layer.

2. The manufacturing method according to claim 1, characterized in that, before fabricating through holes on the main body of the chip substrate, the method further includes: using an organic solvent to clean the surface of the main body of the chip substrate to remove the surface attachments of the main body of the chip substrate.

3. The manufacturing method according to claim 1, characterized in that, the width of the through hole meets the target width.

4. The manufacturing method according to claim 1, characterized in that, the performing a smoothing treatment on the surface of the main body of the chip substrate after the metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate includes: The main body of the chip substrate is subjected to aluminum layer electroplating treatment using an organic solvent, so as to fill aluminum into the through holes to form aluminum pillars, and to cover the aluminum on the upper surface of the main body of the chip substrate to form the metal coating, wherein the metal pillars are the aluminum pillars.

5. The manufacturing method according to claim 1, characterized in that the surface of the main body of the chip substrate that has undergone metal electroplating treatment is smoothed to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, and it includes: The main body of the chip substrate is subjected to metal electroplating treatment using an electroplating process, so as to fill copper or gold into the through holes to form copper pillars or gold pillars, and to cover the copper or the gold on the upper surface of the main body of the chip substrate to form the metal coating, wherein the metal pillars are the copper pillars or the gold pillars.

6. The manufacturing method according to claim 1, characterized in that the surface of the main body of the chip substrate that has undergone metal electroplating treatment is smoothed to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, and it includes: The main body of the chip substrate is etched using wet etching to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate; The surface of the main body of the chip substrate after the etching treatment is polished using a chemical mechanical polishing process, so that the surface of the main body of the chip substrate is smooth and the thickness of the main body of the chip substrate meets the target thickness.

7. A substrate for a superconducting quantum chip, characterized in that it includes: a main body, and through holes penetrating the upper and lower surfaces of the main body. The inner walls of the through holes are covered with a metal film layer, and the through holes covered with the metal film layer are filled with metal pillars. The metal film layer at least includes a seed layer and a barrier layer, wherein the seed layer covers the barrier layer, and the barrier layer is located between the inner wall of the through hole and the seed layer. The main body at least includes quartz glass; The substrate for the superconducting quantum chip is manufactured by the method according to any one of claims 1-6.

8. The substrate for the superconducting quantum chip according to claim 7, characterized in that the seed layer is a metal film layer containing copper, and the barrier layer is a metal film layer containing tantalum.

9. A superconducting quantum chip, characterized in that the superconducting quantum chip includes a substrate for a superconducting quantum chip, a superconducting metal bottom film covering the upper surface of the substrate, and a circuit structure provided on the superconducting metal bottom film, wherein the substrate for the superconducting quantum chip is the substrate according to any one of claims 7-8.

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