PLC and high-speed data acquisition and analysis processing method and system based thereon

Abstract

The present invention relates to the field of data acquisition technology, and in particular to a PLC and a high-speed data acquisition, analysis and processing method and system based thereon. A main program block, a cyclic interrupt block, a first array data block, and a second array data block are set in the CPU module of the PLC, and the cyclic interrupt time of the cyclic interrupt block is configured; during the execution of the main program block, the cyclic interrupt block is called once every cyclic interrupt time, and when the cyclic interrupt block is called, signal input data is acquired from the signal input module; the signal input data is sequentially stored in the first array data block by moving the current pointer; after the current pointer moves a preset number of times, the signal input data of the first array data block is transferred as a whole and stored in the second array data block, and the current pointer of the first array data block is set to the initial position. The present invention realizes low-cost high-speed data acquisition based on the PLC.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and in particular to a PLC and a high-speed data acquisition and analysis processing method and system based thereon. Background Art

[0002] Programmable logic controllers (PLCs) are common devices in the industrial control field. A PLC is a digital electronic device with a microprocessor, used for automated control. It can load control instructions into memory for storage and execution at any time. A PLC is modularly composed of an internal CPU, instruction and data memory, input / output units, power supply modules, and digital analog modules. Currently, when high-speed data acquisition and processing is required in industrial control, embedded systems, FPGAs (field-programmable gate arrays), or the addition of data acquisition cards or high-speed counter modules to the PLC are often used. Existing high-speed data acquisition and processing solutions are not only costly and difficult to learn and use, but also offer functionality that may not be sufficient for applications requiring ultra-high-speed data acquisition. Furthermore, different manufacturers and different types of PLCs manufacture and use different analog acquisition and high-speed counter modules. These modules are not only incompatible and expensive, but also pose significant challenges in use.

[0003] The PLC's operating principle can be summarized as "cyclic scanning and periodic updating." A PLC scan cycle consists of three phases: input sampling, program execution, and output updating. This cycle repeats at a constant scanning speed. During the input sampling phase, the PLC reads the status of the physical input points and stores them in the user program memory area. After the input sampling phase, the PLC enters the program execution phase and the output updating phase. During these phases, even if the status of the physical input points changes, the data in the program memory area remains unchanged. During the program execution phase, the PLC scans the user program from top to bottom and left to right, sending the calculated results to the memory area for storage. During the output updating phase, the data is sent to the actual physical output points. During a PLC cycle, the user program is executed sequentially from beginning to end. It is important to note that the cycle time is not fixed but determined by the program's runtime. Furthermore, only one main program can be executed at a time; parallel execution is not possible. These characteristics of the PLC's operating mode make it difficult to perform high-speed periodic data acquisition.

[0004] Currently, PLCs are not typically chosen when high-speed data acquisition is required. This is because PLCs alone are difficult to maintain a fixed and consistent acquisition cycle. PLCs can only acquire analog signals at speeds of seconds or sub-seconds, making them incapable of meeting higher-speed signal acquisition requirements. Furthermore, PLCs alone lack a comprehensive solution for storing and processing rapidly acquired data. Therefore, when high-speed data acquisition at milliseconds or higher is required, specialized modules (such as high-speed counters or data acquisition boards with high-speed processing) are typically purchased, rather than the PLC as the sole data acquisition medium. Adding high-speed counters or acquisition cards can achieve sampling frequencies of microseconds, but this incurs additional costs and complicates use. Therefore, achieving both the standard PLC functionality and high-speed acquisition capabilities while using a PLC alone presents a current research and development challenge. The challenge is to achieve low-cost, high-speed data acquisition within the PLC itself. Summary of the Invention

[0005] In response to the above problems, the purpose of the present invention is to provide a PLC and a high-speed data acquisition and analysis processing method and system based thereon, which is used to solve the technical problem of how to achieve low-cost and high-speed data acquisition based on the PLC itself, while realizing the general functional requirements of the PLC while taking into account the high-speed acquisition function.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] In one aspect, the present invention provides a PLC, comprising a CPU module, a signal input module, and a signal output module, wherein the CPU module comprises a main program block, a cycle interrupt block, a first array data block, a second array data block, and a third array data block, wherein:

[0008] The main program block is used to start the cycle interruption block once every cycle interruption time during the running process;

[0009] The cyclic interruption block is used to continuously acquire signal input data from the signal input module by starting once every cyclic interruption time, and store the data in the first array data block and the second array data block according to a preset rule, and analyze and process the data in the second array data block before storing it in the third array data block;

[0010] The signal output module is used to output the processing results in the third array data block.

[0011] Preferably, the loop interruption block is stored in the first array data block and the second array data block according to a preset rule, including:

[0012] The signal input data is sequentially stored into the first array data block by moving the current pointer;

[0013] After the current pointer moves a preset number of times, the loop interruption block transfers and stores the signal input data of the first array data block as a whole to the second array data block, and sets the current pointer of the first array data block to the initial position.

[0014] Preferably, the loop interruption block analyzes and processes the data in the second array data block, including: maximum value, frequency and duty cycle analysis.

[0015] Preferably, the PLC further comprises a backplane bus; the signal input module sends the signal input data to the CPU module via the backplane bus; and the data processing result of the CPU is output via the backplane bus and the signal output module.

[0016] Preferably, the signal input module is an analog signal input module and / or a digital signal input module.

[0017] Preferably, when the loop interruption block is called to acquire signal input data from the signal input module, the sampling rate thereof is in the range of 50 Hz to 2000 Hz.

[0018] Another aspect of the present invention further provides a PLC-based high-speed data acquisition and analysis system, which includes the PLC, a host computer, an oscilloscope, and an external controlled object;

[0019] The output end of the host computer is connected to the PLC, and is used to control the PLC to start data collection and analysis;

[0020] The PLC is used to collect and analyze data, and send the analysis results to the oscilloscope and the external controlled object;

[0021] The oscilloscope is used to display the output result of the signal output module;

[0022] The external controlled object is used to execute the controlled task according to the output result of the PLC.

[0023] Another aspect of the present invention further provides a high-speed data acquisition and analysis method based on the PLC, characterized in that the method comprises the following steps:

[0024] Signal data is collected by the signal input module, and the collected signal input data is stored in the first array data block and the second array data block according to a preset rule, and the data in the second array data block is analyzed and processed before being stored in the third array data block; wherein, the signal collection is continued in a manner that the cyclic interrupt block is activated once every cyclic interrupt time; during operation, the cyclic interrupt block is activated once every cyclic interrupt time and is controlled by the main program block;

[0025] The processing results in the third array data block are output through the signal output module.

[0026] Preferably, storing the collected signal input data into the first array data block and the second array data block according to a preset rule includes:

[0027] The signal input data is sequentially stored into the first array data block by moving the current pointer;

[0028] After the current pointer moves a preset number of times, the signal input data of the first array data block is transferred and stored in its entirety to the second array data block, and the current pointer of the first array data block is set to an initial position.

[0029] Preferably, the analyzing and processing of the data in the second array data block includes: maximum value, frequency and duty cycle analysis.

[0030] Compared with the prior art, the present invention has the following advantages due to the adoption of the above technical solution:

[0031] (1) Based on a simple PLC hardware environment, the PLC's CPU module and analog input module (AI module) enable the use of PLC to perform high-speed data acquisition and analysis of analog quantities. This eliminates the need to purchase additional equipment and products, making it simple, convenient, and low-cost.

[0032] (2) Combined with the PLC hardware parameter conditions, the sampling period when using PLC for data acquisition is increased from seconds to microseconds, providing a new idea and implementation method for high-speed acquisition for ordinary PLC users who do not need ultra-high-speed acquisition;

[0033] (3) It can collect analog signals in real time, analyze and process changing analog signals, and ensure the validity and accuracy of the data. The error verified by experiments is about 0.0000, which is sufficient to meet personal and industrial needs.

[0034] (4) It can visualize the signals that are constantly changing during the acquisition process, providing a way for subsequent data processing. It can take out the required amount of data at will and conveniently process the data without affecting the reading and storage of the newly acquired signals, and can realize the synchronous execution process of acquisition and analysis;

[0035] (5) During the simultaneous execution of data acquisition and analysis, data is continuously collected through the first array data block to ensure that data is not lost. On the other hand, the constantly changing signal can be "paused" for the data of the second array data block, that is, its update frequency can be controlled as needed, and the signal of a certain period in the middle can be taken from the second array data block for observation and analysis while ensuring that data is not lost. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. Throughout the drawings, the same reference numerals are used to denote the same components. In the drawings:

[0037] Figure 1 This is the architecture diagram of the data acquisition and analysis system based on PLC;

[0038] Figure 2 This is a schematic diagram of the signal relationship of the hardware architecture of the PLC-based data acquisition and analysis system;

[0039] Figure 3 It is the execution flow chart of the main program block in the CPU module of the PLC;

[0040] Figure 4 It is the execution flow chart of the cyclic interrupt block program in the CPU module of the PLC. DETAILED DESCRIPTION

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.

[0042] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0043] To achieve low-cost, high-speed data acquisition based on the PLC itself, and further enable analysis and processing of the high-speed acquired data. During the operation of the programmable logic controller (PLC), the cyclic interrupt block OB30 interrupts the main program execution at fixed intervals. This characteristic, which distinguishes it from the main program block (Main) OB1, determines that the PLC can be used for fixed-frequency data acquisition. The programmable logic controller includes a CPU module and a signal input module. The CPU module is provided with a main program block, a cyclic interrupt block, a first array data block, and a second array data block, and the cyclic interrupt time of the cyclic interrupt block is configured. During the execution of the main program block, signal input data is acquired from the signal input module by calling the cyclic interrupt block once every cyclic interrupt time. The signal input data is sequentially stored in the first array data block by moving the current pointer. After the current pointer has moved a preset number of times, the signal input data of the first array data block is transferred and stored in its entirety in the second array data block, and the current pointer of the first array data block is set to its initial position. A third array data block is provided in the CPU module for storing, analyzing, and processing the data of the second array data block.

[0044] The technical solution of the present invention can achieve the goal of high-speed data acquisition by developing the functions of the CPU module of the PLC itself, without the need for additional equipment and complex processes, to increase the sampling frequency from seconds to milliseconds. According to the performance of the CPU module and the conversion time of the analog input module, even faster data acquisition speeds can be achieved. Taking the PLC model 1513-1PN produced by Siemens as an example, the cyclic interruption of the CPU module can reach a cycle of 500 microseconds (μs) at the fastest. By applying the high-speed data acquisition technical solution of the present invention, the sampling rate can reach up to 2000 samples / s at the fastest. In specific applications, the actual data acquisition conversion speed can be selected according to different high-speed analog input modules as needed. In actual applications, the maximum sampling rate can reach 2000 Hz, and when matched with the analog input module, the sampling rate value range can be between 50Hz and 2000Hz. The specific sampling rate can be set according to the actual sampling requirements.

[0045] like Figure 1 As shown in the figure, the data acquisition and analysis system architecture diagram based on PLC is given. Figure 1 In the process, the host computer controls the PLC to collect input signals. The AI ​​(analog input) module inside the PLC collects analog input signals. The collected data is transmitted to the CPU module via the backplane bus. The CPU module then outputs the data to the oscilloscope via the backplane bus and the AQ (analog output) module for signal display. Specifically, this may include waveform display of the collected signal input data. At the same time, for external controlled objects, the PLC's CPU outputs control signals via the DQ (digital output) module via the backplane bus. Usually, each PLC controls one or more controlled objects, and the controlled objects specifically perform corresponding business functions under the control of the PLC. There is also a DI (digital input) module inside the PLC to collect digital input signals.

[0046] like Figure 2 Shown is given Figure 1 Schematic diagram of the signal relationship of the hardware architecture. The host computer can be connected to the CPU module via Ethernet and send the switch value to the CPU module. The CPU module accesses the data source through the IO device and the backplane bus, collects the input signal of the data source through the analog or digital signal input module, and outputs the control signal to the controlled object through the IO device and the backplane bus. Figure 1 and Figure 2 The hardware environment shown here enables data and signal acquisition prior to processing. Signal acquisition can be performed on voltage or current signals, and signals can be either sine waves or square waves. Signal analysis can be performed to determine waveform-related metrics such as maximum value, frequency, and duty cycle. Process control during acquisition and analysis includes signal monitoring and control.

[0047] Example 1

[0048] An embodiment of the present invention provides a programmable logic controller (PLC), which includes a CPU module, a signal input module, and a signal output module. The CPU module is provided with a main program block, a cyclic interrupt block, a first array data block, a second array data block, and a third array data block, and a cyclic interrupt time of the cyclic interrupt block is configured. The process of high-speed data acquisition and analysis by the programmable logic controller (PLC) is specifically as follows:

[0049] The main program block calls the cycle interrupt block every cycle interrupt time to collect data;

[0050] The cyclic interrupt block executes data acquisition to obtain signal input data from the signal input module, and stores the signal input data into the first array data block and the second array data block according to a preset rule;

[0051] The loop interrupt block analyzes and processes the signal input data in the second array data block during the data acquisition process and then stores the data in the third array data block;

[0052] The signal output module outputs the analysis and processing results in the third array data block.

[0053] The loop interruption block stores signal input data into the first array data block and the second array data block according to a preset rule, including:

[0054] The signal input data is sequentially stored into the first array data block by moving the current pointer;

[0055] After the current pointer moves a preset number of times, the loop interruption block is used to transfer the signal input data of the first array data block to the second array data block as a whole and set the current pointer of the first array data block to the initial position.

[0056] The analysis process includes analysis process of maximum value, frequency and duty cycle.

[0057] The specific implementation of the technical solution for high-speed data acquisition and analysis based on PLC can include the following steps:

[0058] Step S1: Build a PLC-based hardware platform

[0059] Among them, the hardware platform of the PLC is shown in Figure 1 , only a CPU module with a cyclic interrupt function and a digital input module (DI) and / or an analog input module (AI) are needed. The specific signal input module to be used depends on whether the data to be collected is a digital signal or an analog signal. The analog input and digital input signals can be collected separately or simultaneously.

[0060] Step S2, create the required program blocks

[0061] Among them, the program part mainly uses the main program block (Main) OB1 and the cyclic interrupt block (Cyclic interrupt) OB30; the data storage part uses three data blocks, two of which are array data blocks DB1 and DB2 for storing data, and the other is a data block DB3 for control and display parameters.

[0062] The main program block OB1 is mainly used to implement functions such as the control of the switch quantity from the host computer, the setting of other parameters, and clearing. Specifically, the switch quantity is set according to business needs, sent by the host computer and received by the PLC. For example, the host computer sends a switch quantity with a signal of 1 to the PLC, and the PLC starts to execute the sampling task after receiving the switch quantity. Data block DB3 is used to clear the array data block DB1 and the array data block DB2 when necessary (such as power off and restart), and the block move instruction MOVE_BLK is used to achieve this. Data block DB3 is used to store and display some data and semaphores. The main program controls the clearing of some parameters stored in DB3.

[0063] Step S3, write program

[0064] The main program block primarily implements functions such as switching control, parameter setting, and reset. The key is setting and programming the loop interrupt block. The loop time is set when adding the block or in the block's properties afterward. For example, if the loop time is set to 2ms, the loop interrupt block runs and collects data every 2ms, resulting in a sampling rate of 500Hz. By running the loop interrupt block multiple times at the desired sampling frequency, the loop interrupt block program enables high-speed acquisition and storage of changing signals, facilitating subsequent data processing.

[0065] Step S4: Process the collected data

[0066] The collected signals are stored in the first data array block DB1 and the second data array block DB2. Since the collected signals are transferred and stored en masse from the first data array block DB1 to the second data array block DB2, the required data can be easily retrieved using an address pointer for arbitrary data processing. The values ​​in the first data array block DB1 are continuously updated, while the update frequency of the second data array block DB2 can be controlled as needed, for example, when the number of samples reaches a preset number or the sampling time reaches a preset time.

[0067] In step S3, the work within the loop interrupt block further includes the following sub-steps:

[0068] Step S301: Visualize the collected frequency through the adder. The visualization is implemented in DB3, and an HMI interface can be set up to display and interact with the host computer's LCD screen to achieve further visualization. At the same time, the adder acts as a pointer to indicate the storage location of the collected signal.

[0069] Step S302: The collected signal is stored in the array data block DB1. The number of times the loop interrupt block is executed is used as the address pointer. When the loop interrupt block is started and executed once, the pointer number is incremented by 1, and the data sampled each time is stored in the corresponding position in the first array data block DB1.

[0070] Step S303: When the first array data block DB1 is full of a preset number of elements (the loop interrupt block has run a corresponding number of times), as indicated by the address pointer, the fully stored data is moved as a whole, and the data and the corresponding pointer are copied to the second array data block DB2. This facilitates data processing in the second array data block DB2. The data processing is completed by the program written in the loop interrupt block. At the same time, the data in the first array data block DB1 is continuously updated without losing newly collected signals during the data processing of DB2.

[0071] After data is transferred to DB2, there's a time lag between analysis and processing. The current data collection value can be viewed in DB3, but because the signal updates quickly, every 2ms, it's difficult for the human eye to discern. If 500 data points are stored and copied, the time lag is 2ms * 500 = 1s. If 250 data points are stored and copied, the time lag is 2ms * 250 = 0.5s. This time lag allows ample time for data processing without losing new data.

[0072] The timer can be used to change the frequency of reading data from the first data array DB1 to the second data array DB2, and can also be used to observe signal changes, making it ideal for monitoring whether and when errors occur in the signal. Since the observation task can be completed on the signal data stored in the second data array DB2, the first data array DB1 can continue to collect signals, thus not affecting real-time data collection.

[0073] In step S304, the collected data is subjected to subsequent data processing, such as summing, averaging, etc., which is also completed through the address pointer. The address pointer can index any element stored in the second array data block DB2. For example, to sum the 5th to 500th collected signals, it is only necessary to program in the loop interrupt block using SCL language (or ladder diagram) to implement functions such as summing, averaging, and finding the maximum value. Data processing can also be implemented in the data block DB3 for data in any required variable interval. By simply establishing variables m and n in the data block DB3, the data interval can be changed at any time (including when the program is running), and the signals collected at different times in the data in DB2 can be taken out for data processing as needed; the obtained data processing and data analysis results can be stored in DB3.

[0074] In step S305, the address pointer is cleared within loop interrupt block OB30. DB1 and DB2 use the same pointer. When the first array data block DB1 is full, it is cleared so that new data can overwrite old data at the beginning of the next loop. The data in DB2 is large and rapidly changing, making it difficult to store. However, it can be connected to a human-machine interface (HMI) to display continuous data in graphical form and output to external storage. The processed data (such as the required average value) is relatively small and is output to DB3 for display. The results can also be stored in external memory.

[0075] The following example uses high-speed acquisition and averaging of a 0-5V voltage signal. The sampling rate for the high-speed acquisition process is 500Hz. The specific implementation steps of this PLC-based high-speed acquisition and analysis process include:

[0076] Step S501: Establish a hardware environment, build a PLC platform, use a Siemens PLC-1513 CPU module and an analog input module (AI module), and connect the changing voltage signal to the analog input module;

[0077] Step S502: In the PLC CPU module, a main program block OB1, a cyclic interrupt block OB30, a first array data block DB1, a second array data block DB2, and a third array data block DB3 are established and configured accordingly. The cycle time of the cyclic interrupt block OB30 is set to 2000 microseconds (μs) to read the analog signal (i.e., a 0-5V voltage signal) every 2 milliseconds (ms) to ensure the real-time, validity, and accuracy of the data.

[0078] Step S503: Connect the analog signal to the analog input module to allow the program to run in a stable environment.

[0079] like Figure 3 As shown in the figure, the execution flow of the main program block is given. First, determine whether the switch state is 1. If the switch state is 1, it means the switch is on, then the program runs. During the running process, the loop interrupt program is started every 2 milliseconds. The loop interrupt block program is executed according to Figure 4 The data acquisition process is executed as shown; if the switch state is not 1, it means that the switch is not connected, then the first array data block DB1 and the second array data block DB2, the count value, the superposition value, the average value, etc. are cleared, and wait for the next switch state to be 1.

[0080] like Figure 4 As shown in the figure, the execution flow chart of the cycle interrupt block program is given. The cycle interrupt block program is executed according to Figure 4 The data collection process shown in the figure specifically includes:

[0081] First, determine whether the switch state is 1. If not, do not read the data. If the switch state is 1, read the signal data and store it in the pointer position in the first array data block DB1, and increase the counter value (pointer) by 1. If the counter value does not reach the preset value, continue to read the signal data until the counter value reaches the preset value (for example, 499). After the counter value reaches the preset value (for example, 499), the counting range is 0-499, and a total of 500 samples are completed. The 500 data stored in the first array data block DB1 are transferred to the second array data block DB2 as a whole, and the counter is cleared. Read any variable data or data interval from the second array data block DB2, and the data reading is controlled by the pointer. Process the data read from the second array data block DB2. Part or all of the data read from the second array data block DB2 is directly placed in the third array data block DB3, or part or all of the data read from the second array data block DB2 is placed in the third array data block DB3 after data processing for observation or output.

[0082] Step S504: Observe and read the data in the second array data block DB2; extract the required data interval from the second array data block DB2 and perform data processing. In this example, it is only necessary to control the value of the address pointer, for example, presetting two values ​​m and n, extract the data between m and n, and perform superposition and averaging to obtain the average value of the signal values ​​collected at the corresponding time within the interval. The required or processed data is then stored in the third array data block DB3 for observation or output.

[0083] Taking a square wave voltage signal as an example, analysis of the data in the second array data block DB2 may include analysis of the maximum value, frequency, and duty cycle.

[0084] The loop interrupt block performs a square wave maximum value analysis every 1 second, finds the maximum and minimum values ​​of the 500 collected data from the data to be analyzed and stores them separately. After obtaining the 5 maximum and 5 minimum values, the average value of the maximum value is obtained as the high level, and the average value of the minimum value is obtained as the low level by averaging.

[0085] The loop interrupt block waits for execution every 2 milliseconds. After the pointer address is increased by 1, the count value is increased by 1 when the signal level jumps. When the timing reaches 5 seconds, the count value is divided by the timing value to obtain the frequency value, and the count value is cleared to zero.

[0086] The loop interrupt block waits for execution every 2 milliseconds. After determining whether the level has changed from low to high, it starts the timer. Every 2 milliseconds, it compares the current value with the previous value to determine whether the level has changed from high to low. If so, it ends the timer and stores the value. The duty cycle is calculated by dividing the value by the period.

[0087] Taking a sine wave signal as an example, the analysis of the data in the second array data block DB2 can include maximum value and frequency analysis. The loop interrupt block compares three adjacent data every 2 milliseconds. If the middle value is greater than (or less than) the two adjacent values, the maximum value (or minimum value) is found. After obtaining five maximum values ​​(or minimum values), the five maximum values ​​(or minimum values) are averaged to obtain a more accurate maximum value after averaging. The loop interrupt block increments the counter value by 1 each time the maximum value is obtained. When the timing value is equal to 5, the sine wave frequency is obtained by dividing the count value by the timing value. The count value and timing value are then cleared.

[0088] The results of the above embodiments show that the technical solution of the present invention realizes high-speed data acquisition and analysis processing based on PLC, which is a simple solution that is easy to implement and has considerable real-time, accuracy and stability. On the one hand, this technical solution greatly improves the development rate and utilization rate of the CPU module and loop interrupt function of the PLC, and at the same time greatly reduces the cost required for high-speed data acquisition and analysis processing, filling the gap in data acquisition and processing of analog or digital signals based solely on PLC. By applying the high-speed data acquisition and analysis technical solution of the present invention, high-speed data acquisition and analysis processing can be realized when there is no need to pursue ultra-high sampling rates or do not want to purchase additional acquisition equipment. It can not only realize high-speed data acquisition based on PLC, but also realize the analysis and processing of the collected data by PLC and the visualization of the data to be processed, which can help users conveniently collect, store, observe and process changing analog or digital signals.

[0089] Example 2

[0090] Based on the PLC for high-speed data acquisition and analysis provided in the above embodiment 1, correspondingly, this embodiment provides a system for high-speed data acquisition and analysis, which includes a PLC, a host computer, an oscilloscope, and an external controlled object;

[0091] The host computer sends a control signal to the PLC to control the PLC to start data collection and analysis;

[0092] The PLC performs data acquisition and analysis, and outputs the analysis and processing results to the oscilloscope and the external controlled object;

[0093] The oscilloscope is used to display the output result of the signal output module.

[0094] The PLC includes a CPU module, a signal input module and a signal output module. The CPU module includes a main program block, a cycle interrupt block, a first array data block, a second array data block and a third array data block.

[0095] The main program block is used to start the cycle interruption block once every cycle interruption time during operation;

[0096] The cyclic interruption block is used to continuously acquire signal input data from the signal input module by starting once every cyclic interruption time, and store the data in the first array data block and the second array data block according to a preset rule, and at the same time analyze and process the data in the second array data block and store it in the third array data block;

[0097] The signal output module is used to output the processing results in the third array data block to the oscilloscope and the external controlled object.

[0098] The loop interruption block is stored in the first array data block and the second array data block according to a preset rule, including:

[0099] The signal input data is sequentially stored into the first array data block by moving the current pointer;

[0100] After the current pointer moves a preset number of times, the loop interruption block is used to transfer the signal input data of the first array data block to the second array data block as a whole and set the current pointer of the first array data block to the initial position.

[0101] The loop interrupt block analyzes and processes the data in the second array data block, including maximum value, frequency, and duty cycle analysis. When the loop interrupt block is called, the sampling rate of the signal input data acquired from the signal input module is in the range of 50 Hz to 2000 Hz.

[0102] The PLC also includes a backplane bus; the signal input module sends signal input data to the CPU module via the backplane bus; the data processing results of the CPU are output via the backplane bus and the signal output module. The signal input module is an analog signal input module and / or a digital signal input module.

[0103] Example 3

[0104] Based on the PLC for high-speed data acquisition and analysis provided in Example 1, this embodiment provides a method for high-speed data acquisition and analysis based on a PLC. Therefore, the description of this embodiment is relatively simple, and relevant details can be found in the partial description of Example 1. The method provided in this embodiment is merely illustrative.

[0105] The method for high-speed data acquisition and analysis based on PLC provided in this embodiment includes:

[0106] The method comprises the following steps:

[0107] Signal data is collected by the signal input module, and the collected signal input data is stored in the first array data block and the second array data block according to a preset rule, and the data in the second array data block is analyzed and processed before being stored in the third array data block; wherein, the signal collection is continued in a manner that the cyclic interrupt block is activated once every cyclic interrupt time; during operation, the cyclic interrupt block is activated once every cyclic interrupt time and is controlled by the main program block;

[0108] The processing results in the third array data block are output through the signal output module.

[0109] The storing of the collected signal input data into the first array data block and the second array data block according to a preset rule includes:

[0110] The signal input data is sequentially stored into the first array data block by moving the current pointer;

[0111] After the current pointer moves a preset number of times, the signal input data of the first array data block is transferred and stored in its entirety to the second array data block, and the current pointer of the first array data block is set to an initial position.

[0112] The analysis and processing of the data in the second array data block includes: maximum value, frequency and duty cycle analysis.

[0113] When the signal data is collected by the signal input module to obtain the signal input data, the sampling rate thereof ranges from 50 Hz to 2000 Hz.

[0114] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiment of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal translation scripting language JavaScript, etc.

[0115] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0116] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0118] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0119] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A PLC comprising a CPU module, a signal input module and a signal output module, characterized in that: The CPU module includes a main program block, a cycle interrupt block, a first array data block, a second array data block and a third array data block, wherein: The main program block is used to start the cycle interruption block once every cycle interruption time during the running process; The cyclic interruption block is used to continuously acquire signal input data from the signal input module by starting once every cyclic interruption time, and store the data in the first array data block and the second array data block according to a preset rule, and analyze and process the data in the second array data block before storing it in the third array data block; The signal output module is used to output the processing result in the third array data block; The loop interruption block is stored in the first array data block and the second array data block according to a preset rule, including: The signal input data is sequentially stored into the first array data block by moving the current pointer; After the current pointer moves a preset number of times, the loop interruption block transfers and stores the signal input data of the first array data block as a whole to the second array data block, and sets the current pointer of the first array data block to the initial position.

2. The PLC according to claim 1, characterized in that: The loop interruption block analyzes and processes the data in the second array data block, including: maximum value, frequency and duty cycle analysis.

3. The PLC according to claim 1, wherein: The PLC further comprises a backplane bus; the signal input module sends signal input data to the CPU module via the backplane bus; and the data processing result of the CPU is output via the backplane bus and the signal output module.

4. The PLC according to claim 1, characterized in that: The signal input module adopts an analog signal input module and / or a digital signal input module.

5. The PLC according to claim 1, wherein: When the loop interruption block is called to acquire signal input data from the signal input module, the sampling rate thereof ranges from 50 Hz to 2000 Hz.

6. A high-speed data acquisition and analysis system based on PLC, characterized in that: The system comprises a PLC according to any one of claims 1 to 5, a host computer, an oscilloscope and an external controlled object; The output end of the host computer is connected to the PLC, and is used to control the PLC to start data collection and analysis; The PLC is used to collect and analyze data, and send the analysis and processing results to the oscilloscope and the external controlled object; The oscilloscope is used to display the output result of the signal output module; The external controlled object is used to execute the controlled task according to the output result of the PLC.

7. A high-speed data acquisition and analysis method based on the PLC according to any one of claims 1 to 5, characterized in that: The method comprises the following steps: Signal data is collected by the signal input module, and the collected signal input data is stored in the first array data block and the second array data block according to a preset rule, and the data in the second array data block is analyzed and processed before being stored in the third array data block; wherein, the signal collection is continued in a manner that the cyclic interrupt block is activated once every cyclic interrupt time; during operation, the cyclic interrupt block is activated once every cyclic interrupt time and is controlled by the main program block; The processing results in the third array data block are output through the signal output module.

8. The high-speed data acquisition and analysis method according to claim 7, characterized in that: The storing of the collected signal input data into the first array data block and the second array data block according to a preset rule includes: The signal input data is sequentially stored into the first array data block by moving the current pointer; After the current pointer moves a preset number of times, the signal input data of the first array data block is transferred and stored in its entirety to the second array data block, and the current pointer of the first array data block is set to an initial position.

9. The high-speed data acquisition and analysis method according to claim 7, characterized in that: The analysis and processing of the data in the second array data block includes: maximum value, frequency and duty cycle analysis.

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