Current-limiting threshold precision adjusting circuit, chip and electronic device

Abstract

Embodiments of the present disclosure provide a current limiting threshold precision adjusting circuit, a chip and an electronic device, and belong to the technical field of integrated circuits. The current limiting threshold precision adjusting circuit coupled with a charge pump for providing a driving current signal comprises: a current sampling circuit for generating a first sampling current signal and a second sampling current signal in a multiple relationship with a received load current signal, and providing the first sampling current signal and the second sampling current signal to a current adjusting circuit via a first node and a second node, respectively; a reference current generating circuit for generating a reference current signal and providing the reference current signal to the current adjusting circuit via the first node; and the current adjusting circuit for comparing the first sampling current signal with the reference current signal to obtain a net current signal, and adjusting the influence of the deviation of the driving current signal on the current limiting threshold by using the second sampling current signal and the net current signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a current limit threshold precision adjusting circuit, a chip and an electronic device. BACKGROUND

[0002] In current current limit protection circuits, when the load current output by a detected circuit exceeds a current limit threshold, the current limit protection circuit will provide current limit protection. In current current limit protection circuits, there is a charge pump for providing a driving current signal. Due to factors such as mismatch, the charge pump has a precision deviation in actual application, which ultimately affects the current limit threshold. Especially when the current limit threshold is small, the deviation of the driving current signal provided by the charge pump will have a greater impact on the current limit threshold, which is prone to cause problems such as poor threshold precision and unreasonable mismatch factor proportion for small-valued current limit thresholds. SUMMARY

[0003] An object of embodiments of the present disclosure is to provide a current limit threshold precision adjusting circuit, a chip and an electronic device, which reduces the impact of the deviation of the driving current provided by the charge pump on the current limit threshold precision when the load current approaches the current limit threshold.

[0004] To achieve the above object, according to a first aspect of the present disclosure, a current limit threshold precision adjusting circuit is provided, which is coupled with a charge pump for providing a driving current signal, and the current limit threshold precision adjusting circuit comprises: a current sampling circuit, a reference current generating circuit, and a current adjusting circuit, wherein the current sampling circuit is configured to generate a first sampling current signal and a second sampling current signal in a multiple relationship with a received load current signal, and provide the first sampling current signal and the second sampling current signal to the current adjusting circuit via a first node and a second node, respectively; the reference current generating circuit is configured to generate a reference current signal and provide the reference current signal to the current adjusting circuit via the first node; and the current adjusting circuit is configured to compare the first sampling current signal with the reference current signal to obtain a net current signal, and adjust the impact of the deviation of the driving current signal on the current limit threshold by using the second sampling current signal and the net current signal.

[0005] In some embodiments of the present disclosure, the current sampling circuit comprises a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and an error amplifier, wherein a first end of the first resistor is coupled to a first voltage terminal, and a second end of the first resistor is coupled to a non-inverting input terminal of the error amplifier; a first end of the second resistor is coupled to the first voltage terminal, and a second end of the second resistor is coupled to an inverting input terminal of the error amplifier; a control electrode of the first transistor is coupled to an output terminal of the charge pump, a first electrode of the first transistor is coupled to the non-inverting input terminal of the error amplifier, and a second electrode of the first transistor is coupled to a load current input terminal and a second voltage terminal; a control electrode of the second transistor is coupled to an output terminal of the error amplifier, a first electrode of the second transistor is coupled to the inverting input terminal of the error amplifier, and a second electrode of the second transistor is coupled to a first electrode of the third transistor; a control electrode of the third transistor is coupled to the first electrode of the third transistor, and a second electrode of the third transistor is coupled to the second voltage terminal; a control electrode of the fourth transistor is coupled to the control electrode of the third transistor, a first electrode of the fourth transistor is coupled to the second node, and a second electrode of the fourth transistor is coupled to the second voltage terminal; a control electrode of the fifth transistor is coupled to the first electrode of the fifth transistor and the second node, and a second electrode of the fifth transistor is coupled to the first voltage terminal; a control electrode of the sixth transistor is coupled to the control electrode of the fifth transistor, a first electrode of the sixth transistor is coupled to the first node, and a second electrode of the sixth transistor is coupled to the first voltage terminal.

[0006] In some embodiments of the present disclosure, the reference current generating circuit comprises an operational amplifier, an eleventh transistor and an adjustable resistor, wherein a non-inverting input terminal of the operational amplifier is coupled to a reference voltage input terminal, an inverting input terminal of the operational amplifier is coupled to a first electrode of the eleventh transistor and a first end of the adjustable resistor, and an output terminal of the operational amplifier is coupled to a control terminal of the eleventh transistor; a second electrode of the eleventh transistor is coupled to the first node; and the first end of the adjustable resistor is coupled to an adjustable terminal of the adjustable resistor, and a second end of the adjustable resistor is coupled to a second voltage terminal.

[0007] In some embodiments of the present disclosure, the current adjusting circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a third resistor, wherein a control electrode of the seventh transistor is coupled to the second node, a first electrode of the seventh transistor is coupled to a first end of the third resistor, and a second electrode of the seventh transistor is coupled to the first voltage terminal; a control electrode of the eighth transistor is coupled to a first electrode of the eighth transistor and the first node, and a second electrode of the eighth transistor is coupled to the second voltage terminal; a control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor, a first electrode of the ninth transistor is coupled to the output terminal of the charge pump, and a second electrode of the ninth transistor is coupled to the second voltage terminal; a control electrode of the tenth transistor is coupled to the control electrode of the eighth transistor, a first electrode of the tenth transistor is coupled to the output terminal of the charge pump, and a second electrode of the tenth transistor is coupled to the first end of the third resistor; and a second end of the third resistor is coupled to the second voltage terminal.

[0008] In some embodiments of the present disclosure, the first transistor, the third transistor and the fourth transistor are NMOS transistors, and a width-length ratio of the third transistor is greater than a width-length ratio of the fourth transistor; the second transistor, the fifth transistor and the sixth transistor are PMOS transistors, and a width-length ratio of the fifth transistor is greater than a width-length ratio of the sixth transistor.

[0009] In some embodiments of the present disclosure, the seventh transistor is a PMOS transistor, the eighth transistor, the ninth transistor and the tenth transistor are NMOS transistors, and a width-length ratio of the seventh transistor is equal to a width-length ratio of the sixth transistor.

[0010] In some embodiments of the present disclosure, a resistance value of the third resistor is a minimum resistance value in an adjustable range of the adjustable resistor.

[0011] In some embodiments of the present disclosure, when the load current is equal to the current limiting threshold, a voltage drop of the net current signal on the third resistor is proportional to the drive current signal, and a voltage drop of the second sampling current signal on the third resistor is inversely proportional to the drive current signal.

[0012] According to a second aspect of the present disclosure, a chip is provided. The chip comprises the current limiting threshold precision adjusting circuit according to the first aspect of the present disclosure.

[0013] According to a third aspect of the present disclosure, an electronic device is provided. The electronic device comprises the chip according to the second aspect of the present disclosure.

[0014] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation of the embodiments of the present disclosure. In the accompanying drawings:

[0016] Figure 1 is an exemplary circuit diagram of a current limiting protection circuit;

[0017] Figure 2 is a schematic block diagram of a current limiting threshold accuracy adjustment circuit according to an embodiment of the present disclosure;

[0018] Figure 3 is an exemplary circuit diagram of a current limit threshold accuracy adjustment circuit according to an embodiment of the present disclosure.

[0019] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0022] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0023] Figure 1 An exemplary circuit diagram of a current limit protection circuit 100 is shown. In Figure 1 In the example, when current limit protection occurs, the current on the transistor Mn0 is IMn0 = 1 / n*Icp, which is defined as the net current Inet, and the current flowing through the transistor Mn0 is also referred to as the net current Inet below. Figure 1 The current limit threshold in the circuit structure shown is shown in the following formula (1):

[0024]

[0025] In actual applications, due to factors such as mismatch, the driving current Icp provided by the charge pump actually has an accuracy deviation. In the embodiments of the present disclosure, ΔI represents the accuracy deviation of the driving current Icp actually existing, and then according to formula (1), the accuracy deviation of the driving current Icp will finally be reflected on the current limit threshold Ilim, so that the current limit threshold after including the accuracy deviation is shown in the following formula (2):

[0026]

[0027] Then, the accuracy deviation of the current limit threshold caused by the accuracy deviation of the driving current Icp is the difference between formula (2) and formula (1), which is shown in the following formula (3):

[0028]

[0029] In the embodiments of the present disclosure, the proportion value ratio of formula (3) and formula (1) is used to quantify the accuracy influence of the accuracy deviation of the driving current Icp on the current limit threshold Ilim, which is shown in the following formula (4):

[0030]

[0031] In actual applications, different Iset current values can be obtained by setting different current limit resistors Rlim off-chip, and then the numerical size of the current limit threshold Ilim is adjusted. According to formula (4), the proportion value ratio is proportional to the current limit resistor Rlim, that is, inversely proportional to the current limit threshold Ilim, which will cause that when the current limit threshold Ilim is small, the deviation of the driving current Icp has a greater influence on the accuracy of the current limit threshold Ilim, and if the design is not proper, it is easy to cause the problem that the proportion of the mismatch factor is unreasonable when the small numerical current limit threshold Ilim. The following will be illustrated by combining the above formula derivation and Figure 1 the circuit example diagram: assuming Figure 1In the example, n = 4, Vref = 0.77V, Icp = 2uA, S = 1300, M = 2.8, N = 2.5, the accuracy deviation of Icp ΔI = 30% * Icp. When Rlim = 2.3kΩ, from formula (1) we know that Ilim = 3051mA, and from formula (4) we know that ratio = 0.045%. When Rlim = 38kΩ, from formula (1) we know that Ilim = 189mA, and from formula (4) we know that ratio = 0.73%. Assuming that in this example, Figure 1 The ratio of the impact of the equivalent input offset of the error amplifier on the current limit threshold accuracy is 0.5%. It can be seen that when Ilim = 189mA, the impact of the accuracy deviation of the drive current Icp on the current limit threshold accuracy exceeds the impact of the equivalent input offset of the error amplifier on the current limit threshold accuracy, which is unreasonable in circuit design.

[0032] The embodiments of the present disclosure provide a current limit threshold precision adjustment circuit that reduces the impact of the deviation of the driving current provided by the charge pump on the current limit threshold precision when the load current approaches the current limit threshold. Figure 2 FIG. 2 shows a schematic block diagram of a current limiting threshold precision adjustment circuit 200 according to an embodiment of the present disclosure. Figure 2 As shown, the current limit threshold precision adjustment circuit 200 is coupled to a charge pump 300 that provides a driving current signal Icp. The current limit threshold precision adjustment circuit 200 may include: a current sampling circuit 210 , a reference current generating circuit 220 and a current adjustment circuit 230 .

[0033] The current sampling circuit 210 can be coupled to the reference current generating circuit 220, the current regulating circuit 230, the charge pump 300, a first voltage terminal V1, a second voltage terminal V2, and a load current input terminal Iout. The current sampling circuit 210 is configured to generate a first sampling current signal I1 and a second sampling current signal I2 that are multiples of the load current signal Iout based on the received load current signal Iout, and provide the first sampling current signal I1 and the second sampling current signal I2 to the current regulating circuit 230 via a first node N1 and a second node N2, respectively.

[0034] The reference current generating circuit 220 can be coupled to the current sampling circuit 210, the current regulating circuit 230, the reference voltage input terminal Vref, and the second voltage terminal V2. The reference current generating circuit 220 is configured to generate a reference current signal Iset and provide the reference current signal Iset to the current regulating circuit 230 via the first node N1.

[0035] The current regulating circuit 230 can be coupled with the current sampling circuit 210, the reference current generating circuit 220, the charge pump 300, the first voltage terminal V1 and the second voltage terminal V2. The current regulating circuit 230 is configured to compare the first sampling current signal I1 with the reference current signal Iset to obtain a net current signal Inet, and adjust the influence of the second sampling current signal I2 and the net current signal Inet on the deviation of the driving current signal Icp to the current limit threshold Ilim.

[0036] The current limit threshold precision regulating circuit according to the embodiments of the present disclosure reduces the influence of the precision deviation of the driving current signal of the charge pump on the precision of the current limit threshold at a small current limit threshold by the adjustment of the two current signals, i.e., the second sampling current signal and the net current signal, restores the rationality of the circuit design, and improves the precision of the small current limit threshold compared with the circuit scheme of Figure 1

[0037] Figure 3 An exemplary circuit diagram of the current limit threshold precision regulating circuit 200 according to the embodiments of the present disclosure is shown. As shown in FIG. 2, the current limit threshold precision regulating circuit 200 includes a current sampling circuit 210, a reference current generating circuit 220, a current regulating circuit 230, a charge pump 300, a first voltage terminal V1 and a second voltage terminal V2. Figure 3 ​As shown, the current sampling circuit 210 can include a first resistor R1, a second resistor R2, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and an error amplifier EA. The first end of the first resistor R1 is coupled to a first voltage terminal V1, and the second end of the first resistor R1 is coupled to a non-inverting input terminal of the error amplifier EA. The first end of the second resistor R2 is coupled to the first voltage terminal V1, and the second end of the second resistor R2 is coupled to an inverting input terminal of the error amplifier EA. The control electrode of the first transistor M1 is coupled to an output terminal of the charge pump 300, the first electrode of the first transistor M1 is coupled to the non-inverting input terminal of the error amplifier EA, and the second electrode of the first transistor M1 is coupled to a load current input terminal Iout and a second voltage terminal V2. The control electrode of the second transistor M2 is coupled to an output terminal of the error amplifier EA, the first electrode of the second transistor M2 is coupled to the inverting input terminal of the error amplifier EA, and the second electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3. The control electrode of the third transistor M3 is coupled to the first electrode of the third transistor M3, and the second electrode of the third transistor M3 is coupled to the second voltage terminal V2. The control electrode of the fourth transistor M4 is coupled to the control electrode of the third transistor M3, the first electrode of the fourth transistor M4 is coupled to a second node N2, and the second electrode of the fourth transistor M4 is coupled to the second voltage terminal V2. The control electrode of the fifth transistor M5 is coupled to the first electrode of the fifth transistor M5 and the second node N2, and the second electrode of the fifth transistor M5 is coupled to the first voltage terminal V1. The control electrode of the sixth transistor M6 is coupled to the control electrode of the fifth transistor M5, the first electrode of the sixth transistor M6 is coupled to a first node N1, and the second electrode of the sixth transistor M6 is coupled to the first voltage terminal V1.

[0038] The reference current generating circuit 220 can include an operational amplifier OPA, an eleventh transistor M11, and an adjustable resistor Rlim. The non-inverting input terminal of the operational amplifier OPA is coupled to a reference voltage input terminal Vref, the inverting input terminal of the operational amplifier OPA is coupled to the first electrode of the eleventh transistor M11 and the first end of the adjustable resistor Rlim, and the output terminal of the operational amplifier OPA is coupled to the control terminal of the eleventh transistor M11. The second electrode of the eleventh transistor M11 is coupled to the first node N1. The first end of the adjustable resistor Rlim is coupled to an adjustable terminal of the adjustable resistor Rlim, and the second end of the adjustable resistor Rlim is coupled to the second voltage terminal V2.

[0039] The current regulating circuit 230 can include a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a third resistor R3. The control electrode of the seventh transistor M7 is coupled to the second node N2, the first electrode of the seventh transistor M7 is coupled to the first end of the third resistor R3, and the second electrode of the seventh transistor M7 is coupled to the first voltage terminal V1. The control electrode of the eighth transistor M8 is coupled to the first electrode of the eighth transistor M8 and the first node N1, and the second electrode of the eighth transistor M8 is coupled to the second voltage terminal V2. The control electrode of the ninth transistor M9 is coupled to the control electrode of the eighth transistor M8, the first electrode of the ninth transistor M9 is coupled to the output terminal of the charge pump 300, and the second electrode of the ninth transistor M9 is coupled to the second voltage terminal V2. The control electrode of the tenth transistor M10 is coupled to the control electrode of the eighth transistor M8, the first electrode of the tenth transistor M10 is coupled to the output terminal of the charge pump 300, and the second electrode of the tenth transistor M10 is coupled to the first end of the third resistor R3. The second end of the third resistor R3 is coupled to the second voltage terminal V2.

[0040] In Figure 3 the first voltage terminal V1 inputs a high voltage signal, and the second voltage terminal V2 is grounded. The load current input terminal Iout inputs a load current signal, and the reference voltage input terminal Vref inputs a reference voltage. The first transistor M1, the third transistor M3, the fourth transistor M4, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are all NMOS transistors, and the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all PMOS transistors. In addition, the resistance value of the second resistor R2 is greater than the resistance value of the first resistor R1, and R2 / R1=S. The width-length ratio of the third transistor M3 is greater than the width-length ratio of the fourth transistor M4, and the width-length ratios of the two are M:1. The width-length ratio of the fifth transistor M5 is greater than the width-length ratio of the sixth transistor M6, and the width-length ratios of the two are N:1, and the width-length ratio of the seventh transistor M7 is equal to the width-length ratio of the sixth transistor M6. In addition, the resistance value of the third resistor R3 is the minimum resistance value Rlim_min in the adjustable range of the adjustable resistor Rlim.

[0041] In Figure 3In the example, the seventh transistor M7 and the sixth transistor M6 form a mirror relationship, and the width-length ratio of the two is 1:1, so the seventh transistor M7 replicates the current IM6 of the sixth transistor M6 in a ratio of 1:1 and injects it into the third resistor R3. When the load current Iout approaches the current limit threshold Ilim, it can be known from the circuit connection relationship that IM7 = IM6 ≈ Iset = Vref / Rlim. Then, the voltage drop ΔV_R3 on the third resistor R3 is Vref / Rlim*R3. The mirror ratio of the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 is m:n:1. In addition, for ease of description, the tenth transistor M10, the ninth transistor M9 and the third resistor R3 are combined and equivalent to a transistor in the embodiments of the present disclosure, defined as Mncombo (not shown in the figure), wherein the control electrode of the transistor Mncombo is coupled to the control electrode of the eighth transistor M8, the first electrode of the transistor Mncombo is coupled to the output end of the charge pump 300, and the second electrode of the transistor Mncombo is coupled to the second voltage end V2. In addition, the mirror ratio of the transistor Mncombo and the eighth transistor M8 is defined as K:1, so the current flowing through the eighth transistor M8, that is, the net current signal Inet = 1 / K*Icp. It can be known from the connection relationship of the circuit that the voltage drop ΔV_R3 of the third resistor R3 will affect the conduction state of the tenth transistor M10, that is, when the voltage drop ΔV_R3 is greater than the gate-source voltage of the tenth transistor M10, the tenth transistor M10 is cut off, thereby affecting the mirror ratio K of the transistor Mncombo and the eighth transistor M8, so that K changes between n and m+n, and finally affects the size of the net current signal Inet. It can be known from the connection relationship of the circuit that the value of K is inversely proportional to ΔV_R3. It can be known from the above description and formula (4) that the influence of the accuracy deviation of the driving current signal Icp on the accuracy of the current limit threshold Ilim is as shown in the following formula (5):

[0042]

[0043] When the value of Rlim is increased to obtain a small current limit threshold, and the voltage drop ΔV_R3 on the third resistor R3 is much smaller than the gate-source voltage of the tenth transistor M10, the source negative feedback effect of the third resistor R3 on the tenth transistor M10 can be ignored, so it can be known that K = m+n at this time.

[0044] Then formula (5) can be equivalent to the following formula (6):

[0045]

[0046] Therefore, the change of the value of K essentially reduces the influence of the accuracy deviation of the driving current Icp on the accuracy of the current limit threshold Ilim when the current limit threshold Ilim is small.

[0047] The following will be illustrated by way of example: assuming that the reference voltage Vref = 770 mV, the adjustable resistor Rlim = 38 kΩ, the drive current signal Icp = 2 uA, S = 1300, M = 2.8, N = 2.5, the width-length ratios of M10, M9, and M8 are 8:4:1, and the corresponding current limit threshold Ilim = 189 mA. In this example, the minimum value in the adjustable range of the adjustable resistor Rlim is 2.3 kΩ, and thus when the current limit threshold Ilim = 189 mA, the voltage drop on the third resistor R3 is 46.6 mV, which is only 6% of the turn-on voltage drop of the NMOS transistor. In addition, the mirror ratio of the current mirror composed of the transistor Mncombo and the eighth transistor M8 is about 12:1. When the load current Iout = 189 mA, i.e., the load current Iout is equal to the current limit threshold, the current of the eighth transistor M8, i.e., the net current Inet = 1 / 12*Icp, and according to formula (5), the influence ratio of the accuracy deviation of the drive current signal Icp on the accuracy of the current limit threshold is ratio = 0.25%. If the influence ratio of the equivalent input offset of the error amplifier EA on the accuracy of the current limit threshold is still 0.5%, the influence of the accuracy deviation of the drive current signal Icp on the accuracy of the current limit threshold is less than the influence of the equivalent input offset of the error amplifier EA on the accuracy of the current limit threshold, which restores the rationality of the design and improves the accuracy of the small current limit threshold compared with the circuit shown in FIG. 1. Figure 1 The circuit shown in FIG. 2 improves the accuracy of the small current limit threshold.

[0048] Embodiments of the present disclosure also provide a chip. The chip comprises the current limit threshold accuracy adjusting circuit according to the embodiments of the present disclosure. The chip is, for example, a chip that needs to be protected by current limiting.

[0049] Embodiments of the present disclosure also provide an electronic device. The electronic device comprises the chip according to the embodiments of the present disclosure. The electronic device is, for example, a device such as a power tube, a USB, an LCD TV, and a smart phone.

[0050] Unless the context clearly indicates otherwise, the singular forms of words used in the present text and the appended claims include the plural, and vice versa. Thus, when referring to a singular, the plural of the respective term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive, unless explicitly prohibited from such interpretation herein. Where the term "example" is used in the present text, especially after the phrases "such as" or "for example", the "example" is merely an example and is not to be construed as being exclusive or exhaustive.

[0051] Further aspects and ranges of adaptation become apparent from the description provided herein. It should be understood that various aspects of the application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0052] The above detailed description of several embodiments of the disclosure has been presented for the purposes of illustration and description. It is apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is defined by the appended claims.

Claims

1. A current limiting threshold precision adjustment circuit, coupled to a charge pump providing a driving current signal, characterized in that: The current limiting threshold precision adjustment circuit includes: a current sampling circuit, a reference current generating circuit, and a current adjustment circuit. The current sampling circuit is configured to generate a first sampling current signal and a second sampling current signal that are multiples of the load current signal according to the received load current signal, and provide the first sampling current signal and the second sampling current signal to the current regulation circuit via a first node and a second node respectively; The reference current generating circuit is configured to generate a reference current signal and provide the reference current signal to the current regulating circuit via the first node; The current regulating circuit is configured to compare the first sampling current signal with the reference current signal to obtain a net current signal, and use the second sampling current signal and the net current signal to adjust the influence of the deviation of the driving current signal on the current limiting threshold. The current regulating circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and a third resistor. wherein the control electrode of the seventh transistor is coupled to the second node, the first electrode of the seventh transistor is coupled to the first end of the third resistor, and the second electrode of the seventh transistor is coupled to the first voltage end; The control electrode of the eighth transistor is coupled to the first electrode of the eighth transistor and the first node, and the second electrode of the eighth transistor is coupled to the second voltage terminal; The control electrode of the ninth transistor is coupled to the control electrode of the eighth transistor, the first electrode of the ninth transistor is coupled to the output terminal of the charge pump, and the second electrode of the ninth transistor is coupled to the second voltage terminal; A control electrode of the tenth transistor is coupled to the control electrode of the eighth transistor, a first electrode of the tenth transistor is coupled to the output terminal of the charge pump, and a second electrode of the tenth transistor is coupled to the first terminal of the third resistor; The second terminal of the third resistor is coupled to the second voltage terminal.

2. The current limiting threshold precision adjustment circuit according to claim 1, characterized in that: The current sampling circuit includes: a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and an error amplifier. Wherein, a first end of the first resistor is coupled to a first voltage terminal, and a second end of the first resistor is coupled to a non-inverting input terminal of the error amplifier; A first end of the second resistor is coupled to the first voltage terminal, and a second end of the second resistor is coupled to the inverting input terminal of the error amplifier; The control electrode of the first transistor is coupled to the output terminal of the charge pump, the first electrode of the first transistor is coupled to the non-inverting input terminal of the error amplifier, and the second electrode of the first transistor is coupled to the load current input terminal and the second voltage terminal; The control electrode of the second transistor is coupled to the output terminal of the error amplifier, the first electrode of the second transistor is coupled to the inverting input terminal of the error amplifier, and the second electrode of the second transistor is coupled to the first electrode of the third transistor; The control electrode of the third transistor is coupled to the first electrode of the third transistor, and the second electrode of the third transistor is coupled to the second voltage terminal; The control electrode of the fourth transistor is coupled to the control electrode of the third transistor, the first electrode of the fourth transistor is coupled to the second node, and the second electrode of the fourth transistor is coupled to the second voltage terminal; The control electrode of the fifth transistor is coupled to the first electrode of the fifth transistor and the second node, and the second electrode of the fifth transistor is coupled to the first voltage terminal; A control electrode of the sixth transistor is coupled to the control electrode of the fifth transistor, a first electrode of the sixth transistor is coupled to the first node, and a second electrode of the sixth transistor is coupled to the first voltage terminal.

3. The current limiting threshold precision adjustment circuit according to claim 2, characterized in that: The reference current generating circuit includes: an operational amplifier, an eleventh transistor and an adjustable resistor, wherein the non-inverting input terminal of the operational amplifier is coupled to the reference voltage input terminal, the inverting input terminal of the operational amplifier is coupled to the first electrode of the eleventh transistor and the first end of the adjustable resistor, and the output terminal of the operational amplifier is coupled to the control terminal of the eleventh transistor; The second electrode of the eleventh transistor is coupled to the first node; The first end of the adjustable resistor is coupled to the adjustable end of the adjustable resistor, and the second end of the adjustable resistor is coupled to the second voltage end.

4. The current limiting threshold precision adjustment circuit according to claim 2, characterized in that: The first transistor, the third transistor and the fourth transistor are all NMOS transistors, and the width-to-length ratio of the third transistor is greater than the width-to-length ratio of the fourth transistor; the second transistor, the fifth transistor and the sixth transistor are all PMOS transistors, and the width-to-length ratio of the fifth transistor is greater than the width-to-length ratio of the sixth transistor.

5. The current limiting threshold precision adjustment circuit according to claim 2, characterized in that: The seventh transistor is a PMOS transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all NMOS transistors, and a width-to-length ratio of the seventh transistor is equal to a width-to-length ratio of the sixth transistor.

6. The current limiting threshold precision adjustment circuit according to claim 3, characterized in that: The resistance value of the third resistor is the minimum resistance value in the adjustable range of the adjustable resistor.

7. The current limiting threshold precision adjustment circuit according to claim 6, characterized in that: When the load current is equal to the current limit threshold, the voltage drop of the net current signal across the third resistor is proportional to the drive current signal, and the voltage drop of the second sampling current signal across the third resistor is inversely proportional to the drive current signal.

8. A chip, characterized in that: The invention comprises a current limiting threshold precision adjustment circuit according to any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising the chip according to claim 8.

Images