Edge-delay-based memory operation circuit and multiply-accumulate circuit

Abstract

The present application relates to the technical field of integrated circuit design, more particularly, to a memory and computing unit circuit based on edge transmission delay, and a multi-bit time-domain multiply-accumulate calculation circuit constructed by using the unit circuit. The memory and computing unit circuit comprises two SRAM storage units, a delay calculation unit and a bit line connection switch. The two SRAM storage units are used for storing the weights required in calculation and providing 2-bit weights as multipliers. The delay calculation unit adopts four local delay units, each of which can calculate 2-bit weight multiplied by 2-bit input, so that the delay calculation unit can calculate 2-bit weight multiplied by 8-bit input, so as to improve the calculation efficiency. In addition, an inverter for regulating the edge signal is added in the local delay unit, so as to improve the accuracy of unit delay and time-domain accumulation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and more particularly, to a storage-computing unit circuit based on edge transmission delay, and a multi-bit time domain multiply-accumulate computing circuit constructed by using the unit circuit. BACKGROUND

[0002] The storage-computing integrated technology breaks through the Von Neumann bottleneck and brings new changes to the artificial intelligence era. Under the storage-computing integrated architecture, the memory not only retains the original storage function, but also can perform some logic or multiply-add operations in its internal during the process of reading out data, that is, it is not necessary to transfer a large amount of original data to the processor for calculation, so that the in-memory computing greatly reduces the energy loss caused by data access in the calculation process, increases the data throughput, and greatly improves the calculation speed and energy efficiency.

[0003] The static random memory (SRAM) has a fast reading speed and good compatibility with advanced logic processes, and thus is a common memory for in-memory computing. The SRAM in-memory multiply-accumulate (MAC) computing can be divided into voltage domain, digital domain, time domain (TD), frequency domain, etc. according to the calculation principle, wherein the time domain computing data is represented as pulse width or path delay, and the MAC is realized by changing the pulse width in proportion or comparing the time difference of pulse edges.

[0004] The time domain computing breaks the limitation of working voltage and current on the calculation precision in the analog domain, and has low energy consumption. However, for different multiply implementation structures, the TD-MAC unit based on path delay is mostly still single-bit computing, and the working efficiency still has room for improvement. In addition, the delay timing of the time domain computing is easily affected by process, voltage and temperature, and the delay signal is unstable, which causes difficulty in quantization. SUMMARY

[0005] Therefore, it is necessary to provide a storage-computing unit circuit based on edge transmission delay and a multi-bit time domain multiply-accumulate computing circuit constructed by using the unit circuit, in order to solve the problem of low efficiency of the existing time domain computing, wherein the storage-computing unit circuit can perform 8bit input multiply 2bit weight, and the multi-bit time domain multiply-accumulate computing circuit can stably and accurately realize multi-bit multiply-accumulate operation.

[0006] The present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a storage-computing unit circuit based on edge transmission delay, comprising two SRAM storage parts, a bit line communication switch and a delay computing unit.

[0008] Two SRAM storage sections are used to store the weights required for calculation. One SRAM storage section represents the high-order bits, and the other represents the low-order bits, to achieve weighted bit addition. The high-order SRAM storage section shares the same local bit line LBLa and the same local bit line LBLBa, while the low-order SRAM storage section shares the same local bit line LBLb and the same local bit line LBLBb. The two SRAM storage sections share the same global bit line GBL and the same global bit line GBLB.

[0009] Bit line connection switches are used to control the connection or disconnection of local bit lines and global bit lines.

[0010] The delay calculation unit is used to calculate the product of a 2-bit weight and an 8-bit input. The delay calculation unit includes four local delay units. The 8-bit input is divided into four 2-bit inputs, which are input one-to-one to the four local delay units in the form of group voltages to control the delay duration. The local delay units are electrically connected to two SRAM storage sections and are used to calculate the product of the 2-bit weight and the 2-bit input.

[0011] The 2-bit weight includes 1 bit weight obtained from the high-order SRAM storage and 1 bit weight obtained from the low-order SRAM storage.

[0012] Each local delay unit receives an input edge signal, and the product result is characterized by the transmission delay duration. Based on the product result, the local delay unit delays by n*Δt on top of the inherent delay, where n is the product result.

[0013] The implementation of this in-memory computing unit circuit is based on the method or process of an embodiment of this disclosure.

[0014] Secondly, the present invention discloses a multi-bit time-domain multiply-accumulate calculation circuit for calculating the accumulation of the operation results of k groups of first-aspect storage unit circuits, that is, calculating the multiply-accumulate of 2-bit weights multiplied by 8-bit inputs.

[0015] The multi-bit time-domain multiply-accumulate circuit comprises k sets of memory-based computational units based on edge propagation delay in the first aspect. k > 1.

[0016] k groups of memory-based computing unit circuits are connected in series horizontally to form a k-level arithmetic circuit. The output edge signal of the previous level arithmetic circuit serves as the input edge signal of the next level arithmetic circuit. The k-level arithmetic circuits share the same horizontal word line HWL.

[0017] The implementation of this multi-bit time-domain multiply-accumulate calculation circuit is based on the method or process of an embodiment of this disclosure.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. The in-memory computing unit circuit of the present invention adopts a delay computing unit composed of four local delay units. Each local delay unit can calculate 2-bit weight multiplied by 2-bit input, so that the delay computing unit can calculate 2-bit weight multiplied by 8-bit input, thereby improving the unit computing efficiency. In addition, the in-memory computing unit circuit of the present invention can be used in k groups in series to construct a k-level computing circuit, which can calculate the sum of k 2-bit weights multiplied by 8-bit input, realizing multi-bit time domain multiplication and accumulation.

[0020] 2. The delay calculation unit of the present invention adds inverters at the input and output terminals of the edge. One inverter specifies the input edge signal as a rapidly changing rising edge signal E1, and the other inverter specifies the delay signal E3 as a rapidly changing falling edge signal, and serves as the output edge signal. This idealizes the input and output, making the measurement of edge delay more ideal. Moreover, in the multi-bit time domain multiply-accumulate calculation circuit, the output edge signal of the previous stage can be used as the input edge signal of the next stage. Since the signal is processed as described above, the delay is stable and accurate, thereby ensuring the overall calculation accuracy. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the memory-based computing unit circuit based on edge propagation delay disclosed in Embodiment 1 of the present invention;

[0023] Figure 2 for Figure 1 A schematic diagram of the structure of the 6T-SRAM memory cell in the image;

[0024] Figure 3 for Figure 1 Schematic diagram of inverters INV1 and INV2;

[0025] Figure 4 for Figure 1 A schematic diagram of the working waveform of the first local delay unit in the in-memory computing unit circuit;

[0026] Figure 5 for Figure 1 Schematic diagram of the product and corresponding delay time of the in-memory computing unit circuit;

[0027] Figure 6 for Figure 1A schematic diagram of the internal signal state changes when the product of a local delay unit in the in-memory computing unit circuit is 9;

[0028] Figure 7 for Figure 1 A schematic diagram of the series connection of the k-group memory computing unit circuits. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] Example 1

[0033] See Figure 1 This is a structural diagram of the memory computing unit circuit based on edge propagation delay disclosed in this invention. The memory computing unit circuit based on edge propagation delay can be simply referred to as a delay computing unit (DCU).

[0034] The memory-based computing unit circuit based on edge propagation delay includes two SRAM storage sections, a delay calculation unit, and a bit line connection switch.

[0035] Two SRAM storage sections are used to store the weights required for calculation. One SRAM storage section represents the high-order bits (distinguished by the suffix 'a'), and the other SRAM storage section represents the low-order bits (distinguished by the suffix 'b'), to achieve weighted calculation of the weight bits.

[0036] It should be noted that the higher-order SRAM memory segments share the same local bit line LBLa and the same local bit line LBLBa. The lower-order SRAM memory segments share the same local bit line LBLb and the same local bit line LBLBb. The two SRAM memory segments share the same global bit line GBL and the same global bit line GBLB.

[0037] The two SRAM storage sections have the same structure and are used to provide 2-bit weights to the delay calculation unit.

[0038] The high-order SRAM storage section comprises several 6T-SRAM storage cells, sharing the same local bit line LBLa and the same local bit line LBLBa. That is, the weighted storage nodes of these 6T-SRAM storage cells are all connected to the local bit line LBLa, and the complementary weighted storage nodes are connected to the local bit line LBLBa. The low-order SRAM storage section comprises several 6T-SRAM storage cells, sharing the same local bit line LBLb and the same local bit line LBLBb. That is, the weighted storage nodes of these 6T-SRAM storage cells are all connected to the local bit line LBLb, and the complementary weighted storage nodes are connected to the local bit line LBLBb.

[0039] Furthermore, as 6T-SRAM memory cells are a well-known technology, their general structure will be explained here: For example... Figure 2 It includes two PMOS transistors QP1 to QP2 and four NMOS transistors QN1 to QN4. The gate of QP1 is connected to the gate of QN1, the drain of QP2, the drain of QN2, and the drain of QN4, respectively. The gate of QP2 is connected to the gate of QN2, the drain of QP1, the drain of QN1, and the drain of QN3, respectively. The sources of QP1 and QP2 are both connected to the power supply VDD. The gates of QN3 and QN4 are both connected to the word line WL. The source of QN3 is connected to the corresponding local bit line LBL, and the source of QN4 is connected to the corresponding local bit line LBLB. The sources of QN1 and QN2 are both connected to the common terminal GND. The drains of QP1 and QN1 are connected to the weighted storage node Q, and the drains of QP2 and QN2 are connected to the complementary weighted storage node QB.

[0040] Thus, the word line WL in the higher SRAM memory location is WLa, and its storage weight is Wa. The word line WL in the lower SRAM memory location is WLb, and its storage weight is Wb.

[0041] In this embodiment, the two SRAM storage units are located above and below the delay calculation unit. See Figure 1Both SRAM storage sections are configured with m 6T-SRAM storage cells. Considering factors such as storage density, the higher-order SRAM storage section uses a column of 16 6T-SRAM storage cells, and the lower-order SRAM storage section uses a column of 16 6T-SRAM storage cells. Of course, the number of 6T-SRAM storage cells in the higher and lower-order SRAM storage sections can also be adjusted.

[0042] The bitline connection switch is used to control whether the local bitline is connected to or disconnected from the global bitline. Specifically, the bitline connection switch is closed during memory operation, which disconnects the local bitline from the global bitline; and it is opened during memory read / write operation, which connects the local bitline to the global bitline.

[0043] The bit line connection switches include PMOS transistors P1 to P4. P1's source is connected to the global bit line GBL, its drain to the local bit line LBLa, and its gate to the horizontal word line HWL. P2's source is connected to the global bit line GBLB, its drain to the local bit line LBLBa, and its gate to the horizontal word line HWL. P3's source is connected to the global bit line GBL, its drain to the local bit line LBLb, and its gate to the horizontal word line HWL. P4's source is connected to the global bit line GBLB, its drain to the local bit line LBLBb, and its gate to the horizontal word line HWL. For ease of control, a single horizontal word line HWL is shared. Adjusting the horizontal word line HWL to a high level turns off P1 to P4, disconnecting the local bit lines from the global bit lines; adjusting the horizontal word line HWL to a low level turns on P1 to P4, connecting the local bit lines to the global bit lines.

[0044] When in use, the high-order SRAM memory opens a row and provides 1 bit weight; the low-order SRAM memory opens a row and provides 1 bit weight, thus forming a 2-bit weight.

[0045] The delayed calculation unit is used to calculate the 2-bit weight multiplied by the 8-bit input. For example... Figure 1 As shown, the delay calculation unit includes four Local Delay Cells (LDCs) and can complete 8-bit input.

[0046] Specifically, the 8-bit input is divided into four 2-bit inputs. The four 2-bit inputs are input one-to-one to the four local delay units in the form of group voltages to control the delay duration.

[0047] It should be noted that each group of voltages includes three input voltages converted from 2-bit inputs. The Mth group of voltages converted from the Mth 2-bit input out of the four 2-bit inputs is input into the Mth local delay unit, where M = 1, 2, 3, 4.

[0048] See Figure 1The 8-bit input is divided into four 2-bit inputs, including the first 2-bit input (VIN10, also written as VIN[1:0]), the second 2-bit input (VIN32, also written as VIN[3:2]), the third 2-bit input (VIN54, also written as VIN[5:4]), and the fourth 2-bit input (VIN76, also written as VIN[7:6]), which are converted into corresponding group voltages through an external DAC circuit (not shown).

[0049] Specifically, VIN10 is converted into three input voltages, Input1, Input2, and Input3, and input to the first local delay cell (Local Delay Cell #0). Similarly, VIN32 is also converted into three input voltages and input to the second local delay cell (Local Delay Cell #1); VIN54 is also converted into three input voltages and input to the third local delay cell (Local Delay Cell #2); and VIN76 is also converted into three input voltages and input to the fourth local delay cell (Local Delay Cell #3).

[0050] The local delay unit is electrically connected to two SRAM memory locations and is used to calculate a 2-bit weight multiplied by a 2-bit input. The 2-bit weight includes 1 bit of weight obtained from the higher-order SRAM memory location and 1 bit of weight obtained from the lower-order SRAM memory location. Each local delay unit is connected to an input edge signal, and the propagation delay duration characterizes the product result.

[0051] The four local delay units have the same structure, each including four PMOS transistors P5 to P8, eight NMOS transistors N1 to N8, and two inverters INV1 and INV2.

[0052] See Figure 1 Taking the first local delay cell (Local Delay Cell #0) as an example, it takes the first 2-bit input (VIN10) as input, connects to the input edge signal EIN0, and outputs the output edge signal EOUT0.

[0053] Specifically, the source of P5 is connected to the power supply VDD. The source of P6 is connected to the power supply VDD, and its gate is connected to the drain of P5. The gate of P7 is connected to the local bit line LBLa. The source of P8 is connected to the power supply VDD, its drain is connected to the source of P7, and its gate is connected to the local bit line LBLb. The drain of N1 is connected to the drain of P5, and its gate is connected to the gate of P5. The source of N2 is connected to GND, its drain is connected to the drain of P6, and its gate is connected to the drain of N1. The source of N3 is connected to GND, its drain is connected to the source of N1, and its gate is connected to the drain of P7. The drain of N4 is connected to the gate of N3, and its gate is connected to the local bit line LBLa. The source of N5 is connected to Input3, its drain is connected to the source of N4, and its gate is connected to the local bit line LBLb. The source of N6 is connected to Input2, its drain is connected to the source of N4, and its gate is connected to the local bit line LBLBb. The drain of N7 is connected to the gate of N3, and its gate is connected to the local bit line LBLBa. The source of N8 is connected to Input1, the drain is connected to the source of N7, and the gate is connected to the local bit line LBLb. The input of inverter INV1 is connected to the input edge signal EIN0, and the output is connected to the gate of N1. Inverter INV2 has its input connected to the drain of N2, and its output connected to the output edge signal EOUT0.

[0054] Input1 is the first input voltage in the group voltage converted from VIN10. Input2 is the second input voltage in the group voltage converted from VIN10. Input3 is the second input voltage in the group voltage converted from VIN10.

[0055] The other local delay units follow the same pattern: the second local delay unit takes the second 2-bit input (VIN32), connects to the input edge signal EIN1, and outputs the output edge signal EOUT1. The third local delay unit takes the third 2-bit input (VIN54), connects to the input edge signal EIN2, and outputs the output edge signal EOUT2. The fourth local delay unit takes the fourth 2-bit input (VIN76), connects to the input edge signal EIN3, and outputs the output edge signal EOUT3.

[0056] It should be noted that P5 / N1 / N3 form the first inverting structure and P6 / N2 form the second inverting structure. The two together constitute a buffer for delaying signals.

[0057] N4 / N5, N4 / N6, N7 / N8, and P7 / P8 form logic branches, which are used to logically select a certain branch so that the selected voltage is transmitted to the gate of N3, changing the gate voltage of N3 to control the current of N3, thereby changing the control discharge speed and controlling the delay time.

[0058] Inverters INV1 and INV2 are used to standardize the signal. Specifically, inverter INV1 standardizes the input edge signal to a rapidly changing rising edge signal E1. The input edge signal EIN is inverted for the first time by inverter INV1 to generate the rising edge signal E1. E1 is inverted a second time by P5 / N1 to generate the delayed signal E2. E2 is inverted a third time by P6 / N2 to generate the delayed signal E3. Inverter INV2 standardizes the delayed signal E3 to a rapidly changing falling edge signal, which serves as the output edge signal. The delayed signal E3 is inverted a fourth time by inverter INV2 to generate the falling edge signal, which serves as the output edge signal EOUT.

[0059] Specifically, since this memory-based computing unit circuit uses the propagation delay of edge signals to characterize the calculation results, and during the delay process, the changes of E2 and E3 may be slow and nonlinear, which are very undesirable edge signals, inverters INV1 and INV2 are used to make the measurement of edge delay more ideal, thereby improving the stability and accuracy of the delay.

[0060] The two inverters INV1 and INV2 can be designed as follows: See Figure 3 Inverter INV1 includes a PMOS transistor VP1 and an NMOS transistor VN1. The source of VP1 is connected to the power supply VDD, and its drain is connected to the gate of N1, with the gate connected to the input edge signal. The source of VN1 is connected to GND, and its drain is connected to the gate of N1, with the gate connected to the input edge signal. Inverter INV2 includes a PMOS transistor VP2 and an NMOS transistor VN2. The source of VP2 is connected to the power supply VDD, its drain is connected to the output edge signal, and its gate is connected to the drain of N2. The source of VN2 is connected to GND, its drain is connected to the output edge signal, and its gate is connected to the drain of N2. Of course, other inverter structures can also be used, but they must also have the above-described functions.

[0061] In this embodiment, the components adopt the following specifications: the gate length of all transistors is 180nm; the gate widths of PMOS transistors P5 and P6 are 2.4um and 3.9um, respectively; the gate widths of NMOS transistors N1, N2, and N3 are 0.8um, 1.2um, and 1.0um, respectively; the gate widths of PMOS transistors VP1 and VP2 in inverters INV1 / INV2 are 1.95um; the gate widths of NMOS transistors VN1 and VN2 in inverters INV1 / INV2 are 0.6um; and the gate widths of the remaining transistors are all 220nm.

[0062] The local delay unit delays by n*Δt based on the product result, on top of the inherent delay, where n is the product result.

[0063] In summary, the in-memory computation process of this computing unit is cyclical, with one computation cycle consisting of two stages:

[0064] In the first stage, the horizontal word line HWL is adjusted to a high level, and the bit line connection switches (P1 / P2 / P3 / P4) are turned off, disconnecting the local bit line from the global bit line. The 2-bit input is converted into the corresponding group voltage through the external DAC circuit and input into the local delay unit. At the same time, the word lines of the SRAM storage section are turned on, so that the weight data stored in the high-order SRAM storage section is read onto the local bit lines LBLa and LBLBa, and the weight data stored in the low-order SRAM storage section is read onto the local bit lines LBLb and LBLBb.

[0065] It should be noted that each time a row is opened in the high-order SRAM storage section, 1 bit weight (Wa) is provided; each time a row is opened in the low-order SRAM storage section, 1 bit weight (Wb) is provided, thus forming a 2-bit weight ([Wa:Wb]).

[0066] In the second stage, the input edge signal is input to the local delay unit. First, it is inverted by inverter INV1 into a rapidly changing rising edge signal. Then, it is inverted and delayed by inverter structure one, then inverted and delayed by inverter structure two, and finally inverted by inverter INV2 into a rapidly changing falling edge signal, which serves as the output edge signal. The output edge signal has a delay compared to the input edge signal; the product result n is represented by the delay duration. The internal calculation process of the delay calculation unit ends.

[0067] Thus, there is a delay between the output edge signal and the input edge signal, and the product result n is represented by the delay duration.

[0068] See Figure 4 The diagram below shows the working waveform of the first local delay unit in this embodiment, also known as the delay waveform. The specific simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 1.8V. Figure 4 The waveform of the first local delay unit is shown when VIN10 is 11 and [Wa:Wb] is 10.

[0069] Specifically, the horizontal word line HWL controls the bit line connection switches (P1 / P2 / P3 / P4) to be in the off state, disconnecting the local bit lines from the global bit lines. The external DAC circuit converts VIN10=11 into the corresponding group voltage (Input1~Input3, where Input1 is V1, Input2 is V2, and Input3 is V3) and inputs it into the first local delay unit. The word lines of the SRAM storage section are enabled (through the external word line driver circuit, etc.), causing the weighted data stored in the high-order SRAM storage section to be read onto the local bit lines LBLa and LBLBa, and the weighted data stored in the low-order SRAM storage section to be read onto the local bit lines LBLb and LBLBb. Since the 2-bit weight is 10, that is, the local bit line LBLa is high, the local bit line LBLBa is low, the local bit line LBLb is low, and the local bit line LBLBb is high, the AND logic branch composed of N4 / N6 forms a path, and the other branches are open; thus, the gate voltage of N3 is Input2.

[0070] The falling edge signal EIN0 is input to the first local delay unit. First, it is inverted by inverter INV1 into a rapidly changing rising edge signal E1. Then, it is inverted and delayed by inverter structure one to generate a delayed signal E2. Next, it is inverted and delayed by inverter structure two to generate a delayed signal E3. Finally, it is inverted by inverter INV2 into a rapidly changing falling edge signal, which becomes the output edge signal EOUT0. The delay calculation process within the unit ends.

[0071] Among them, the delay effect of the reverse structure composed of P5 / N1 / N3 is affected by the gate voltage of N3. The delay time will change accordingly depending on the gate voltage of N3.

[0072] When the gate voltage of N3 is VIN10 = 11, the delay between EOUT0 and EIN0 is t0 + 6Δt, where 6 is the product of [Wa:Wb] (10) and VIN10 (11). Here, t0 is the inherent delay, which is the delay of the local delay unit when at least one of the input and weight is 00.

[0073] The working principle of the other local delay units is similar and will not be elaborated further. Of course, see [link to relevant documentation]. Figure 5This diagram illustrates the product and corresponding delay duration of the memory-based computing unit circuit in this embodiment. Since the 2-bit input includes four cases: 00, 01, 10, and 11, and the 2-bit weight also includes four cases: 00, 01, 10, and 11, the product of the 2-bit input and the 2-bit weight includes seven cases: 0, 1, 2, 3, 4, 6, and 9, with delay durations of t0, t0+Δt, t0+2Δt, t0+3Δt, t0+4Δt, t0+6Δt, and t0+9Δt, respectively.

[0074] In addition, see Table 1 below, which shows the group voltages corresponding to the input voltages and their respective delay time truth tables, covering various cases of 2-bit input and 2-bit weights.

[0075] Table 1 shows the multiplication results and delay truth table for a local delay unit.

[0076]

[0077] Since the in-memory unit circuit has four local delay units, and each unit performs a 2-bit input multiplied by a 2-bit weight, four product results are obtained. These four product results can then be converted into an 8-bit input multiplied by a 2-bit weight in the digital domain. This process is achieved through an external time-to-digital converter (TDC).

[0078] To illustrate the function of the two inverters, let's take a product of 9 as an example: See [link / reference] Figure 6 This is a schematic diagram illustrating the internal signal state changes when the product of a local delay unit in this embodiment is 9. Figure 6 It can be seen that there is a delay between EOUT and EIN. Inverter INV1 converts the falling edge signal of the input into a rapidly changing rising edge signal E1, providing a stable input for the subsequent inverting structure during the delay process. Inverter INV2 converts the delayed signal E3 into a rapidly changing output falling edge signal, which is used as the output edge signal EOUT, providing a stable input for the next stage when used in series.

[0079] Furthermore, it is possible to obtain from Figure 6 Direct observation reveals that E2 and E3 change slowly over longer delay times, making them undesirable edge signals. If E2 or E3 is directly used as the output edge signal of a local delay unit, it may remain at an intermediate voltage for an extended period, hindering external circuitry (such as TDC) from determining the delay duration. Furthermore, if E2 or E3 is subsequently used as the input edge signal of a later memory-based unit, it cannot provide a stable input level, severely impacting the delay process of subsequent delay calculation units. This hinders linear superposition in the time domain, reduces the linearity of the delay, and increases errors in delay and time measurement.

[0080] Example 2

[0081] See Figure 7 The diagram shows the series operation of the memory-based computing unit circuit in Example 1, which constitutes a multi-bit time-domain multiply-accumulate computing circuit.

[0082] The multi-bit time-domain multiply-accumulate calculation circuit includes k sets of memory-based computing unit circuits as described in Example 1. k > 1.

[0083] like Figure 6 As shown, k groups of memory-based computing unit circuits are connected in series horizontally, thus forming a k-level arithmetic circuit. The first group of memory-based computing unit circuits is the first-level arithmetic circuit; the second group of memory-based computing unit circuits is the second-level arithmetic circuit; and so on. The k-level arithmetic circuits share the same horizontal word line HWL for unified control.

[0084] When used in series, the output edge signal of the previous stage arithmetic circuit is used as the input edge signal of the next stage arithmetic circuit. Specifically, the output edge signal of the Mth local delay unit of the previous stage arithmetic circuit is connected to the input edge signal of the Mth local delay unit of the next stage arithmetic circuit, so that the output edge signal of the Mth local delay unit of the previous stage arithmetic circuit is used as the input edge signal of the Mth local delay unit of the next stage arithmetic circuit, thereby accumulating the product result.

[0085] The Mth local delay unit of each stage of the operational circuit receives the Mth group of voltages converted from the Mth of the four 2-bit inputs.

[0086] Since a local delay unit can calculate a 2-bit weight multiplied by a 2-bit input, each stage of the arithmetic circuit can calculate a 2-bit weight multiplied by an 8-bit input. The output signal of the previous stage of the arithmetic circuit serves as the input signal of the next stage of the arithmetic circuit. Thus, k stages of the arithmetic circuit can calculate the sum of k 2-bit weights multiplied by 8-bit inputs.

[0087] Similar to the memory cell circuit, the digital domain result of the sum of k 2-bit weights multiplied by 8-bit inputs is also achieved through an external time-to-digital converter (TDC): Specifically, the TDC counts the delay time to obtain the accumulated digital result, and the accumulated results of the four local delay cells are added together according to their weights to obtain the digital domain result of the sum of k 2-bit weights multiplied by 8-bit inputs.

[0088] It should be noted that the delayed signal undergoes the processing procedure described in Example 1 in each stage of the arithmetic circuit. If the output edge signal of the upper stage changes slowly, it cannot provide a stable input level for the lower stage as its input edge signal, causing delay deviations in the lower stage. However, in this multiply-accumulate calculation circuit, the output edge signal of the upper stage changes quickly, providing a stable input level to the lower stage in a short time, greatly reducing the delay deviation of the lower stage and thus ensuring the overall calculation accuracy.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A memory-based computing unit circuit based on edge propagation delay, characterized in that, include: Two SRAM storage sections are used to store the weights needed for calculation; One of the SRAM storage units represents the high-order bits, and the other SRAM storage unit represents the low-order bits, to achieve weighted bit addition; the high-order SRAM storage units share the same local bit line LBLa and the same local bit line LBLBa, and the low-order SRAM storage units share the same local bit line LBLb and the same local bit line LBLBb; the two SRAM storage units share the same global bit line GBL and the same global bit line GBLB; Bit line connection switch, used to control the connection or disconnection of local bit lines and global bit lines; and A delay calculation unit is used to calculate the product of a 2-bit weight and an 8-bit input. The delay calculation unit includes four local delay units. The 8-bit input is divided into four 2-bit inputs, which are input one-to-one into the four local delay units in the form of group voltages to control the delay duration. The Mth group voltage converted from the Mth 2-bit input is input into the Mth local delay unit, where M = 1, 2, 3, 4. The local delay unit is electrically connected to the two SRAM storage units and is used to calculate a 2-bit weight multiplied by a 2-bit input; wherein the 2-bit weight includes a 1-bit weight obtained from the high-order SRAM storage unit and a 1-bit weight obtained from the low-order SRAM storage unit. Each of the local delay units is connected to an input edge signal, and the product result is characterized by the transmission delay duration. The local delay unit delays by n*Δt based on the product result and the inherent delay t0, where t0 is the delay of the local delay unit when at least one of the input and weight is 0; n is the product result; and Δt is the difference between the delay duration when the product result is 1 and the delay duration when the product result is 0.

2. The memory-based computing unit circuit based on edge propagation delay according to claim 1, characterized in that, The high-order SRAM storage section includes several 6T-SRAM storage cells, which share the same local bit line LBLa and the same local bit line LBLBa; The low-order SRAM storage section includes several 6T-SRAM storage cells that share the same local bit line LBLb and the same local bit line LBLBb.

3. The memory-based computing unit circuit based on edge propagation delay according to claim 1, characterized in that, Each voltage group consists of three input voltages converted from 2-bit input.

4. The memory-based computing unit circuit based on edge propagation delay according to claim 1, characterized in that, The bit line connection switch includes: PMOS transistor P1 has its source connected to the global bit line GBL, its drain connected to the local bit line LBLa, and its gate connected to the horizontal word line HWL. PMOS transistor P2 has its source connected to the global bit line GBLB, its drain connected to the local bit line LBLBa, and its gate connected to the horizontal word line HWL. PMOS transistor P3 has its source connected to the global bit line GBL, its drain connected to the local bit line LBLb, and its gate connected to the lateral word line HWL; and PMOS transistor P4 has its source connected to the global bit line GBLB, its drain connected to the local bit line LBLBb, and its gate connected to the lateral word line HWL.

5. The memory-based computing unit circuit based on edge propagation delay according to claim 4, characterized in that, The local delay unit includes: PMOS transistor P5, its source is connected to power supply VDD; PMOS transistor P6 has its source connected to the power supply VDD and its gate connected to the drain of P5. PMOS transistor P7 has its gate connected to the local bit line LBLa; PMOS transistor P8 has its source connected to the power supply VDD, its drain connected to the source of P7, and its gate connected to the local bit line LBLb. NMOS transistor N1 has its drain connected to the drain of P5 and its gate connected to the gate of P5. NMOS transistor N2 has its source connected to GND, its drain connected to the drain of P6, and its gate connected to the drain of N1. NMOS transistor N3 has its source connected to GND, its drain connected to the source of N1, and its gate connected to the drain of P7. NMOS transistor N4 has its drain connected to the gate of N3, and its gate connected to the local bit line LBLa. NMOS transistor N5 has its source connected to the third input voltage, its drain connected to the source of N4, and its gate connected to the local bit line LBLb. NMOS transistor N6 has its source connected to the second input voltage, its drain connected to the source of N4, and its gate connected to the local bit line LBLBb. NMOS transistor N7 has its drain connected to the gate of N3, and its gate is connected to the local bit line LBLBa. NMOS transistor N8 has its source connected to the first input voltage, its drain connected to the source of N7, and its gate connected to the local bit line LBLb. Inverter INV1, its input terminal is connected to the input edge signal, and its output terminal is connected to the gate of N1; and Inverter INV2 has its input connected to the drain of N2 and its output connected to the output edge signal.

6. The memory-based computing unit circuit based on edge propagation delay according to claim 5, characterized in that, P5, N1, and N3 form an inverting structure one, and P6 and N2 form an inverting structure two. The two together form a buffer for delaying signals. N4 and N5, N4 and N6, N7 and N8, P7 and P8 respectively form logic branches, which are used to logically select a certain branch, so that the selected voltage is transmitted to the gate of N3, changing the gate voltage of N3 to control the current of N3, thereby changing the control discharge speed and controlling the delay time. The inverter INV1 is used to standardize the input edge signal as a rapidly changing rising edge signal; the inverter INV2 is used to standardize the delayed signal as a rapidly changing falling edge signal, and serves as the output edge signal.

7. The memory-based computing unit circuit based on edge propagation delay according to claim 6, characterized in that, The inverter INV1 includes: PMOS transistor VP1 has its source connected to power supply VDD and its drain connected to the gate of N1, with the gate connected to the input edge signal; and The NMOS transistor VN1 has its source connected to GND and its drain connected to the gate of N1. The gate is connected to the input edge signal. The inverter INV2 includes: PMOS transistor VP2 has its source connected to power supply VDD, its drain connected to the output edge signal, and its gate connected to the drain of N2; and The NMOS transistor VN2 has its source connected to GND, its drain connected to the output edge signal, and its gate connected to the drain of N2.

8. The memory cell circuit based on edge propagation delay according to any one of claims 7, characterized in that, One computation cycle of the memory computing unit circuit includes two stages, which are: In the first stage, the horizontal word line HWL controls P1, P2, P3, and P4 to be in the off state, and the local bit lines are disconnected from the global bit lines; the 2-bit input is converted into the corresponding group voltage and input into the local delay unit; simultaneously, the word lines of the SRAM storage section are enabled, so that the weighted data stored in the high-order SRAM storage section is read onto the local bit lines LBLa and LBLBa, and the weighted data stored in the low-order SRAM storage section is read onto the local bit lines LBLb and LBLBb, thereby achieving selection of the input voltage; and In the second stage, the input edge signal is input to the local delay unit. First, it is inverted by inverter INV1 into a rapidly changing rising edge signal. Then, it is inverted and delayed by inverter structure one, then inverted and delayed by inverter structure two, and finally inverted by inverter INV2 into a rapidly changing falling edge signal, which serves as the output edge signal. There is a delay between the output edge signal and the input edge signal, and the product result n is represented by the delay duration.

9. A multi-bit time-domain multiply-accumulate calculation circuit for calculating the multiply-accumulate of 2-bit weights multiplied by 8-bit inputs, characterized in that, Includes k sets of memory-based unit circuits as described in any one of claims 1-8; k > 1; The k-group memory-based computing unit circuits are connected in series horizontally to form a k-level computing circuit; the output edge signal of the previous level computing circuit serves as the input edge signal of the next level computing circuit; the k-level computing circuits share the same horizontal word line HWL.

10. The multi-bit time-domain multiply-accumulate calculation circuit according to claim 9, characterized in that, The Mth local delay unit of each stage of the operational circuit receives the Mth group of voltages converted from the Mth of the four 2-bit inputs. The output edge signal of the Mth local delay unit of the previous stage arithmetic circuit is used as the input edge signal of the Mth local delay unit of the next stage arithmetic circuit.

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