Timing controller circuit

Abstract

The present invention provides a timing controller circuit for controlling at least one in-panel gate circuit in a display panel, and includes a data receiving circuit, a timing detection circuit, a control circuit, and a data transmission circuit. The data receiving circuit is used to receive image data. The timing detection circuit is coupled to the data receiving circuit and is used to detect an input timing of the image data. The control circuit is coupled to the timing detection circuit and is used to determine an in-panel gate timing of the in-panel gate circuit based on the input timing of the image data, and to generate a timing control output based on the in-panel gate timing. The data transmission circuit is coupled to the control circuit and is used to transmit the timing control output to the in-panel gate circuit.

Description

Technical Field

[0001] This invention relates to a timing controller circuit for use in a display panel, and more particularly to a timing controller circuit that increases charging time by switching the gate timing within the panel and generating a data masking signal. Background Technology

[0002] In recent years, the size and resolution of liquid crystal display (LCD) panels have been increasing, resulting in shorter charging times for the data lines. This leads to insufficient charging time at high resolutions, preventing the accurate display of grayscale. Panel manufacturers have proposed various methods to address this issue. For example, in an 8Kx4K@120Hertz (Hz) panel (i.e., 8Kx4K resolution and 120Hz frame rate), the HG2D (half-gate, two-data) architecture was proposed to sequentially and simultaneously activate two gates, doubling the charging time compared to the 1G1D (one-gate, one-data) architecture. However, the HG2D architecture increases the number of source drivers, raising costs. Therefore, an innovative timing controller circuit is urgently needed to improve the charging time problem. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a timing controller circuit that increases charging time by switching the gate timing within the panel and generating a data masking signal, in order to solve the above-mentioned problems.

[0004] In one embodiment of the present invention, a timing controller circuit for controlling at least one in-panel gate circuit in a display panel is disclosed. The timing controller circuit may include a data receiving circuit, a timing detection circuit, a control circuit, and a data transmitting circuit. The data receiving circuit can receive image data. The timing detection circuit is coupled to the data receiving circuit and can detect an input timing of the image data. The control circuit is coupled to the timing detection circuit and can determine an in-panel gate timing of the in-panel gate circuit based on the input timing of the image data, and generate a timing control output based on the in-panel gate timing. The control circuit switches between different in-panel gate timings of the in-panel gate circuit in response to different input timings of the image data. The data transmitting circuit is coupled to the control circuit and can transmit the timing control output to the in-panel gate circuit.

[0005] In one embodiment of the present invention, a timing controller circuit for controlling at least one in-panel gate circuit in a display panel is disclosed. The timing controller circuit may include a data receiving circuit, a timing detection circuit, a data processing circuit, a control circuit, and a data transmission circuit. The data receiving circuit can receive image data. The timing detection circuit is coupled to the data receiving circuit and can detect an input timing of the image data. The data processing circuit is coupled to the timing detection circuit and can perform data masking processing on the image data according to the input timing to generate a data masking signal. The control circuit is coupled to the timing detection circuit and can determine an in-panel gate timing of the in-panel gate circuit according to the input timing of the image data, and generate a timing control output according to the in-panel gate timing. The data transmission circuit is coupled to the control circuit and the data processing circuit and can transmit the timing control output and the data masking signal to the display panel.

[0006] In one embodiment of the present invention, a timing controller circuit is disclosed for controlling at least one in-panel gate circuit in a display panel. The timing controller circuit may include a data receiving circuit, a timing detection circuit, a control circuit, and a data transmitting circuit. The data receiving circuit can receive image data. The timing detection circuit is coupled to the data receiving circuit and can detect an input timing of the image data. The control circuit is coupled to the timing detection circuit and can determine an in-panel gate timing of the in-panel gate circuit based on the input timing of the image data. The data transmitting circuit is coupled to the control circuit and can transmit the timing control output to the display panel, wherein the timing control output controls the in-panel gate circuit to sequentially and simultaneously activate at least two of the gates of the display panel.

[0007] When the resolution and frame rate of the display panel are 8Kx4K and 60Hz respectively, and the input timing of the image data is 8Kx2K@120Hz, the timing controller circuit of the present invention controls the gate circuit within the control panel to sequentially and simultaneously turn on two of the multiple gate lines of the display panel. That is, it sequentially and simultaneously turns on two of the multiple gates of the multiple thin-film transistors connected to the same data line in the display panel. The sub-pixels corresponding to the two gates will simultaneously display the same sub-pixel data transmitted by the data transmission circuit in the image data. In this way, the frame rate of the display panel increases from the original 60Hz to 120Hz (that is, it increases by 2 times). In addition, the horizontal resolution of the display panel is maintained at 8K, while the vertical resolution of the display panel 12 is reduced from 4K to 2K. However, the resolution of the display panel is still maintained at true 8K. Therefore, in the case that the timing controller circuit of the present invention has only a single timing controller, the frame rate of the display panel is improved and the dynamic visual effect of the display panel is improved, and the charging time of each data line of the display panel is maintained at 3.74 microseconds.

[0008] Furthermore, when the resolution and frame rate of the display panel are 8Kx4K and 120Hz respectively, and the input timing of the image data is 8Kx4K@120Hz, the timing controller circuit of the present invention generates a data masking signal to control the source drive circuit to mask the odd-numbered data lines in each even-numbered frame of the image data and drive only the even-numbered data lines, and to control the source drive circuit to mask the even-numbered data lines in each odd-numbered frame of the image data and drive only the odd-numbered data lines. In this way, each frame of the display panel will only display data with an input timing of 8Kx2K@120Hz. Therefore, the timing controller circuit of the present invention can use the interlaced scanning architecture to increase the charging time of each data line of the display panel by 2 times from the original 1.87μs to 3.74μs, so as to improve the problem of insufficient charging time. Attached Figure Description

[0009] Figure 1 This is a block diagram of a display system according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a timing controller circuit according to an embodiment of the present invention.

[0011] Figure 3 According to an embodiment of the present invention Figure 2 The timing diagram shown is for the timing control output generated by the timing controller circuit.

[0012] Figure 4 According to another embodiment of the present invention Figure 2 The timing diagram shown is for the timing control output generated by the timing controller circuit.

[0013] Figure 5 This is a schematic diagram of a timing controller circuit according to another embodiment of the present invention.

[0014] Figure 6 According to an embodiment of the present invention Figure 5 The timing diagram shown is for the timing control output generated by the timing controller circuit.

[0015] [Symbol Explanation]

[0016] 100: Display System

[0017] 10, 200, 500: Timing controller circuit

[0018] 12: Display Panel

[0019] 14: In-panel gate circuit

[0020] 16_1~16_N: Gate

[0021] 18: Source drive circuit

[0022] 20_1~20_N: Shift registers

[0023] IDATA: Image Data

[0024] STVA: First Start Pulse Signal

[0025] STV: Second Start Pulse Signal

[0026] CLK1~CLKM: Clock signals

[0027] GL_1~GL_N: Gate lines

[0028] DATA_MASK: Data masking signal

[0029] 201: Timing Controller

[0030] 202, 502: Data receiving circuit

[0031] 204, 504: Timing detection circuits

[0032] 206, 508: Control circuit

[0033] 208, 510: Data transmission circuits

[0034] IN_TIMING: Input timing

[0035] CLK1~CLK10: Clock signals

[0036] STV0_A, STV1_A: Odd-numbered pulse signals

[0037] STV0_B, STV1_B: Even-numbered pulse signals

[0038] 50: Master timing controller

[0039] 51: From the timing controller

[0040] 506: Data Processing Signal

[0041] D1, D3, D5, D7, D9, D11, D13, D17, D19: Odd-numbered line data

[0042] D2, D4, D6, D8, D10, D12, D14, D16, D18: Even-numbered line data Detailed Implementation

[0043] Figure 1 This is a block diagram of a display system 100 according to an embodiment of the present invention. Figure 1 As shown, the display system 100 may include a timing controller circuit 10 and a display panel 12. The display panel 12 may include a gate-in-panel (GIP) circuit 14, multiple gates 16_1 to 16_N (e.g., gates of multiple thin-film transistors (TFTs)), and a source driver circuit 18. The gate-in-panel circuit 14, as a gate driver circuit, controls the opening / closing of the gates on multiple gate lines GL_1 to GL_N, and may include multiple shift registers 20_1 to 20_N, wherein the multiple shift registers 20_1 to 20_N correspond to the multiple gate lines GL_1 to GL_N respectively, and the multiple gate lines GL_1 to GL_N are respectively coupled to the multiple gates 16_1 to 16_N of the display panel 12. For ease of explanation, Figure 1Only one gate on each gate line is shown. In reality, each gate line connects to the gates of multiple thin-film transistors in the horizontal direction. Furthermore, the display panel 12 has multiple data lines, each connected to the source of multiple thin-film transistors in the vertical direction. The source drive circuit 18 controls the driving voltage applied to each data line based on the image data. The number of gate lines GL_1 to GL_N and the number of data lines (not shown) are determined by the resolution WxH of the display panel 12. Each pixel of the display panel 12 consists of three sub-pixels: a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Therefore, the horizontal resolution W of the display panel 12 determines the number of data lines in the horizontal direction to be W*3, while the vertical resolution H of the display panel 12 determines the number of gate lines GL_1 to GL_N in the vertical direction to be H (i.e., N = H). For example, in the display panel 12 resolution... In the case of an 8Kx4K resolution, the vertical direction of the display panel 12 may contain 4320 gates 16_1 to 16_4320 (i.e., N = 4320) located on 4320 gate lines GL_1 to GL_4320 respectively. The sources of the 4320 thin-film transistors corresponding to the gates 16_1 to 16_4320 are connected to the same data line. The gate circuit 14 in the panel may contain 4320 shift registers 20_1 to 20_4320, wherein the 4320 shift registers 20_1 to 20_4320 correspond to the 4320 gate lines GL_1 to GL_4320 respectively.

[0044] The timing controller circuit 10 can be used to receive image data IDATA and detect an input timing IN_TIMING of the image data IDATA. In addition, the timing controller circuit 10 can perform data masking processing on the image data IDATA according to the input timing IN_TIMING of the image data IDATA to generate a data masking signal DATA_MASK, and determine an in-panel gate timing GIP_TIMING of the in-panel gate circuit 14 according to the input timing IN_TIMING of the image data IDATA. The timing controller circuit 10 can generate a timing control output TIMING_OUTPUT to the in-panel gate circuit 14 according to the in-panel gate timing GIP_TIMING. It should be noted that in some embodiments, the timing controller circuit 10 switches between different in-panel gate timings GIP_TIMING in response to different input timings IN_TIMING of the image data IDATA. In addition, in some embodiments, the timing controller circuit 10 does not perform data masking processing on the image data IDATA according to the input timing IN_TIMING of the image data IDATA (i.e., it does not generate a data masking signal DATA_MASK), but directly transmits the image data IDATA to the display panel 12 (e.g., the source drive circuit 18 on the display panel 12). Next, the timing controller circuit 10 can transmit the timing control output TIMING_OUTPUT and image data IDATA (or the timing control output TIMING_OUTPUT, image data IDATA and data mask signal DATA_MASK) to the display panel 12, wherein the timing control output TIMING_OUTPUT is transmitted to the gate circuit 14 in the panel, and the image data IDATA (or the image data IDATA and data mask signal DATA_MASK) is transmitted to the source drive circuit 18.

[0045] In this embodiment, the timing control output TIMING_OUTPUT may include a first start pulse signal STVA, a second start pulse signal STVB, and multiple clock signals CLK1 to CLKM. The first start pulse signal STVA can be used to precharge multiple shift registers 20_1 among multiple shift registers 20_1 to 20_N to sequentially turn on multiple odd shift registers (i.e., shift register 20_1, shift register 20_3, shift register 20_4, shift register 20_5, etc.) in the gate circuit 14 in the panel corresponding to multiple odd gate lines (i.e., GL_1, GL_3, GL_5, etc.). Bit register 20_5, etc.), and the second start pulse signal STVB can be used to precharge shift register 20_2 among multiple shift registers 20_1 to 20_N to sequentially turn on multiple even registers (i.e., shift register 20_2, shift register 20_4, shift register 20_6, etc.) in the gate circuit 14 in the panel corresponding to multiple even gate lines (i.e., GL_2, GL_4, GL_6, etc.). Multiple clock signals CLK1 to CLKM can be used to drive multiple odd gate lines and multiple even gate lines respectively through multiple odd shift registers and multiple even registers, so as to The gates connected to each gate line are turned on (for example, multiple gates 16_1 to 16_N in the vertical direction are turned on one by one according to the driving timing of multiple gate lines). For example, when the resolution of the display panel 12 is 8Kx4K (that is, the display panel 12 may contain multiple gates 16_1 to 16_4320, which are the gates of 4320 thin-film transistors on the same data line), the timing control output TIMING_OUTPUT may contain multiple clock signals CLK1 to CLK10 (that is, M=10), where each clock signal of the multiple clock signals CLK1 to CLK10 is turned on. Each signal has 432 pulses to turn on 432 gate lines out of 4320 gate lines GL_1 to GL_4320 respectively. For the gates 16_1 to 16_4320 of the 4320 thin film transistors on the same data line, the 432 pulses of each of the multiple clock signals CLK1 to CLK10 will turn on the 432 gates out of the multiple gates 16_1 to 16_4320 respectively (for example, the 432 pulses of the clock signal CLK1 turn on gates 16_1, 16_11, 16_21, ..., 16_4311 respectively).

[0046] Figure 2 This is a schematic diagram of a timing controller circuit 200 according to an embodiment of the present invention. Figure 1 The timing controller circuit 10 shown can be modified by Figure 2The timing controller circuit 200 shown is used to implement this. It should be noted that in this embodiment, the resolution and frame rate of the display panel 12 are 8Kx4K and 60Hz, respectively. The timing controller circuit 200 does not perform data masking processing on the image data IDATA according to the input timing IN_TIMING of the image data IDATA (that is, it does not generate a data masking signal DATA_MASK), but directly transmits the image data IDATA to the display panel 12 (e.g., the source drive circuit 18 of the display panel 12). In addition, the timing controller circuit 200 has only a single timing controller 201, and this single timing controller can be used to control the gate drive and data drive (i.e., source drive) of all sub-pixels of the display panel 12.

[0047] like Figure 2 As shown, the timing controller circuit 200 (especially the timing controller 201) may include a data receiving circuit 202, a timing detection circuit 204, a control circuit 206, and a data transmission circuit 208. The data receiving circuit 202 can be used to receive image data IDATA, wherein the input timing IN_TIMING of the image data IDATA can be 8Kx4K@60Hz (i.e., the resolution and frame rate of the image data IDATA are 8Kx4K and 60Hz respectively) or 8Kx2K@120Hz (i.e., the resolution and frame rate of the image data IDATA are 8Kx2K and 120Hz respectively). The timing detection circuit 204 can be coupled to the data receiving circuit 202 and can be used to detect the input timing IN_TIMING of the image data IDATA. The control circuit 206 can be coupled to the timing detection circuit 204 and can be used to determine the in-panel gate timing GIP_TIMING of the in-panel gate circuit 14 based on the detected input timing IN_TIMING of the image data IDATA, and generate a timing control output TIMING_OUTPUT (which includes a first start pulse signal STVA, a second start pulse signal STVB and multiple clock signals CLK1 to CLK10 (M=10)) based on the in-panel gate timing GIP_TIMING. The control circuit 206 will switch between different in-panel gate timing GIP_TIMING of the in-panel gate circuit 14 in response to different input timing IN_TIMING of the image data IDATA. The data transmission circuit 208 can be coupled to the control circuit 206 and can be used to transmit the timing control output TIMING_OUTPUT to the in-panel gate circuit 14 and output the image data IDATA to the source drive circuit 18.

[0048] For example, when the input timing IN_TIMING of the image data IDATA is 8Kx4K@60Hz, the timing control output TIMING_OUTPUT will control the gate circuit 14 to sequentially turn on each of the multiple gate lines GL_1 to GL_4320 of the display panel 12, that is, sequentially turn on each of the multiple gates 16_1 to 16_4320 in the vertical direction connected to the same data line in the display panel 12 to light up the display panel 12. For example, when the input timing IN_TIMING of the image data IDATA is 8Kx2K@120Hz, the timing control output TIMING_OUTPUT will control the gate circuit 14 to sequentially and simultaneously turn on two gate lines of the multiple gate lines GL_1 to GL_4320 of the display panel 12. That is, it will sequentially and simultaneously turn on two gates of the multiple gates 16_1 to 16_4320 connected to the same data line in the display panel 12. The sub-pixels corresponding to the two gates will simultaneously display the same sub-pixel data transmitted by the data transmission circuit 208 in the image data IDATA. In this way, the frame rate of the display panel 12 increases from the original 60Hz to 120Hz (that is, it increases by 2 times). In addition, the horizontal resolution of the display panel 12 is maintained at 8K, while the vertical resolution of the display panel 12 is reduced from 4K to 2K. However, the resolution of the display panel 12 is still maintained at true 8K. Therefore, with only a single timing controller 201 in the timing controller circuit 200, the frame rate of the display panel 12 is improved and the dynamic visual effect of the display panel 12 is improved. The charging time of each data line of the display panel 12 is maintained at 3.74 microseconds (μs).

[0049] Figure 3 According to an embodiment of the present invention Figure 2The timing diagram shown is for the timing control output generated by the timing controller circuit 200. In this embodiment, the input timing IN_TIMING of the image data IDATA is 8Kx4K@60Hz. The first start pulse signal STVA may include multiple odd pulse signals STV0_A and STV1_A, wherein the pulse width of one pulse signal of odd pulse signal STV0_A is 1.5*3.7μs, and the pulse width of one pulse signal of odd pulse signal STV1_A is 3*3.7μs. The second start pulse signal STVB may include multiple even pulse signals STV0_B and STV1_B, wherein the pulse width of one pulse signal of even pulse signal STV0_B is 1.5*3.7μs, and the pulse width of one pulse signal of even pulse signal STV1_B is 3*3.7μs. Since the input timing IN_TIMING of the image data IDATA is 8Kx4K@60Hz, the timing control output TIMING_OUTPUT controls the gate circuit 14 within the control panel to sequentially turn on each of the multiple gates 16_1 to 16_4320 of the display panel 12 to illuminate the display panel 12, as shown below. Figure 3 As shown, each of the multiple clock signals CLK1 to CLK10 has 432 pulses to turn on 432 gates from 16_1 to 16_4320 respectively (for example, the 432 pulses in clock signal CLK1 turn on gates 16_1, 16_11, 16_21, ..., 16_4311 respectively). Each pulse signal has a width of 2*3.7μs. For simplicity, ... Figure 3 The diagram only shows the pulses corresponding to the first 20 gates (i.e., gates 16_1 to 16_20) out of the multiple gates 16_1 to 16_4320.

[0050] Figure 4 According to another embodiment of the present invention Figure 2The timing diagram shown is for the timing control output generated by the timing controller circuit 200. In this embodiment, the input timing IN_TIMING of the image data IDATA is 8Kx2K@120Hz. The first start pulse signal STVA may include multiple odd pulse signals STV0_A and STV1_A, wherein the pulse width of one odd pulse signal STV0_A is 1.5*3.7μs, and the pulse width of one odd pulse signal STV1_A is 3*3.7μs. The second start pulse signal STVB may include multiple even pulse signals STV0_B and STV1_B, wherein the pulse width of one even pulse signal STV0_B is 1.5*3.7μs, and the pulse width of one even pulse signal STV1_B is 3*3.7μs. Since the input timing IN_TIMING of the image data IDATA is 8Kx2K@120Hz, the timing control output TIMING_OUTPUT will control the gate circuit 14 within the control panel to sequentially and simultaneously turn on two gates among the multiple gates 16_1 to 16_4320 of the display panel 12. For example, it sequentially and simultaneously turns on gates 16_1 and 16_2, gates 16_3 and 16_4, gates 16_5 and 16_6, ..., gates 16_4319 and 16_4320. Figure 4 As shown, each of the multiple clock signals CLK1 to CLK10 has 432 pulses to turn on 432 gates from 16_1 to 16_4320 respectively (for example, the 432 pulses in clock signal CLK1 turn on gates 16_1, 16_11, 16_21, ..., 16_4311 respectively). Each pulse signal has a width of 2*3.7μs. For simplicity, ... Figure 4 The diagram only shows the pulses corresponding to the first 20 gates (i.e., gates 16_1 to 16_20) out of the multiple gates 16_1 to 16_4320.

[0051] Figure 5 This is a schematic diagram of a timing controller circuit 500 according to another embodiment of the present invention. Figure 1 The timing controller circuit 10 shown can be modified by Figure 5The timing controller circuit 500 shown is used to implement this. It should be noted that in this embodiment, the resolution and frame rate of the display panel 12 are 8Kx4K and 120Hz, respectively. The timing controller circuit 500 may include a master timing controller 50 and a slave timing controller 51. The master timing controller 50 can be used to control the gate driving of all sub-pixels of the display panel 12 and control the data driving (source driving) of a portion of the sub-pixels of the display panel 12. The slave timing controller 51 can be used to control the data driving (source driving) of another portion of the sub-pixels of the display panel 12. For example, the data output of the master timing controller 50 and the data output of the slave timing controller 51 are coupled to the left and right sides of the display panel 12, respectively. Then, the master timing controller 50 can be used to control the data driving of the left half of the display panel 12, and the slave timing controller 51 can be used to control the data driving of the right half of the display panel 12.

[0052] like Figure 5As shown, the timing controller circuit 500 includes a main timing controller 50, which may include a data receiving circuit 502, a timing detection circuit 504, a data processing circuit 506, a control circuit 508, and a data transmission circuit 510. The data receiving circuit 502 can receive image data IDATA, where the input timing IN_TIMING of the image data IDATA can be 8Kx4K@120Hz (i.e., the resolution and frame rate of the image data IDATA are 8Kx4K and 120Hz, respectively). The timing detection circuit 504 can be coupled to the data receiving circuit 502 and can be used to detect the input timing IN_TIMING of the image data IDATA. The data processing circuit 506 can be coupled to the timing detection circuit 504 and can perform data masking processing on the image data IDATA according to the input timing IN_TIMING of the image data IDATA to generate a data masking signal DATA_MASK. The control circuit 508 can be coupled to the timing detection circuit 504 and can be used to determine the in-panel gate timing GIP_TIMING of the in-panel gate circuit 14 based on the input timing IN_TIMING of the image data IDATA, and generate the timing control output TIMING_OUTPUT (which includes a first start pulse signal STVA, a second start pulse signal STVB, and multiple clock signals CLK1 to CLK10) based on the in-panel gate timing GIP_TIMING. The data transmission circuit 510 can be coupled to the data processing circuit 506 and the control circuit 508, and can be used to transmit the timing control output TIMING_OUTPUT, the image data IDATA, and the data mask signal DATA_MASK to the display panel 12, wherein the timing control output TIMING_OUTPUT is output to the in-panel gate circuit 14, and the image data IDATA and the data mask signal DATA_MASK are output to the source drive circuit 18.

[0053] In this embodiment, the data masking signal DATA_MASK can be used to control the source drive circuit 18 to mask the odd-numbered data lines in each even-numbered frame of the image data IDATA and drive only the even-numbered data lines, and to control the source drive circuit 18 to mask the even-numbered data lines in each odd-numbered frame of the image data IDATA and drive only the odd-numbered data lines. In this way, each frame of the display panel 12 will only display data with an input timing IN_TIMING of 8Kx2K@120Hz. Therefore, the timing controller circuit 500 can use the interlaced scanning architecture to increase the charging time of each data line of the display panel 12 by 2 times from the original 1.87μs to 3.74μs, so as to improve the problem of insufficient charging time.

[0054] Figure 6 According to an embodiment of the present invention Figure 5 The timing diagram shown is for the timing control output generated by the timing controller circuit 500. (See diagram for example.) Figure 6 As shown, the first start pulse signal STVA may include multiple odd-numbered pulse signals STV0_A and STV1_A, wherein the pulse width of one odd-numbered pulse signal STV0_A is 3*1.85μs, and the pulse width of one odd-numbered pulse signal STV1_A is 6*1.85μs. The second start pulse signal STVB may include multiple even-numbered pulse signals STV0_B and STV1_B, wherein the pulse width of one even-numbered pulse signal STV0_B is 3*1.85μs, and the pulse width of one even-numbered pulse signal STV1_B is 6*1.85μs. The timing control output TIMING_OUTPUT controls the gate circuit 14 within the control panel to sequentially turn on each of the multiple gates 16_1 to 16_4320 of the display panel 12 to illuminate the display panel 12, as shown. Figure 6 As shown, each of the multiple clock signals CLK1 to CLK10 has 432 pulses to turn on 432 gates from 16_1 to 16_4320 respectively (for example, the 432 pulses in clock signal CLK1 turn on gates 16_1, 16_11, 16_21, ..., 16_4311 respectively). Each pulse signal has a width of 4 * 1.85 μs. For simplicity, ... Figure 6 The diagram only shows the pulses corresponding to the first 20 gates (i.e., gates 16_1 to 16_20) out of the multiple gates 16_1 to 16_4320.

[0055] Assuming image data IDATA has multiple odd-numbered line data D1, D3, D5, ..., D4319 (each odd-numbered line data contains sub-pixel data used to drive multiple thin-film transistors located on the same odd-numbered scan line) and multiple even-numbered line data D2, D4, D6, ..., D4320 (each even-numbered line data contains sub-pixel data used to drive multiple thin-film transistors located on the same even-numbered scan line), when the data masking signal DATA_MASK controls the source drive circuit 18, multiple odd-numbered gates corresponding to multiple odd-numbered gate lines will only display odd-numbered line data (e.g., gate 16_1 will only display odd-numbered line data D1, and gate 16_3 will only display odd-numbered line data D3), and multiple even-numbered gates corresponding to multiple even-numbered gate lines will only display even-numbered line data (e.g., gate 16_2 will only display even-numbered line data D2, and gate 16_4 will only display even-numbered line data D4). For simplicity, in... Figure 6The diagram only shows the data that will be displayed for the first 20 gates (i.e., gates 16_1 to 16_20) out of the multiple gates 16_1 to 16_4320.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A timing controller circuit for controlling at least an in-panel gate circuit in a display panel, the timing controller circuit comprising: Data receiving circuit, used to receive image data; A timing detection circuit is coupled to the data receiving circuit and is used to detect the input timing of the image data; A data processing circuit is coupled to the timing detection circuit and performs data masking processing on the image data according to the input timing of the image data to generate a data masking signal. A control circuit, coupled to the timing detection circuit, is configured to determine the in-panel gate timing of the in-panel gate circuit based on the input timing of the image data, and to generate a timing control output based on the in-panel gate timing, wherein the control circuit switches between different in-panel gate timings of the in-panel gate circuit in response to different input timings of the image data; and A data transmission circuit, coupled to the control circuit and the data processing circuit, is used to transmit the timing control output and the data masking signal to the display panel. The data masking signal is output to the source drive circuit of the display panel. The data masking signal controls the source drive circuit to mask the odd line data in each even frame of the image data and drive only the even line data, and controls the source drive circuit to mask the even line data in each odd frame of the image data and drive only the odd line data.

2. The timing controller circuit as claimed in claim 1, wherein the timing controller circuit has only a single timing controller, and the single timing controller is used to control the gate driving and data driving of all sub-pixels of the display panel, and includes the data receiving circuit, the timing detection circuit, the control circuit and the data transmission circuit.

3. The timing controller circuit as claimed in claim 1, wherein the timing control output includes a first start pulse signal and a second start pulse signal; the first start pulse signal is used to activate a plurality of first shift registers corresponding to a plurality of odd-numbered gate lines in the gate circuit within the panel; the second start pulse signal is used to activate a plurality of second shift registers corresponding to a plurality of even-numbered gate lines in the gate circuit within the panel; and the plurality of odd-numbered gate lines and the plurality of even-numbered gate lines are coupled to a plurality of gates in the display panel.

4. The timing controller circuit as claimed in claim 3, wherein the timing control output further includes a plurality of clock signals, and the plurality of clock signals are used to drive the plurality of odd gate lines and the plurality of even gate lines through the plurality of first shift registers and the plurality of second shift registers.

5. The timing controller circuit of claim 1, wherein, in response to the input timing of the image data, the timing control output controls the in-panel gate circuit to sequentially turn on each of all the gates of the display panel.

6. The timing controller circuit as claimed in claim 5, wherein the input timing of the image data is 8Kx4K@60Hertz(Hz).

7. The timing controller circuit of claim 1, wherein, in response to the input timing of the image data, the timing control output controls the gate circuit within the panel to sequentially and simultaneously turn on at least two of all the gates of the display panel.

8. The timing controller circuit of claim 7, wherein the sub-pixels corresponding to the at least two gates simultaneously display the same sub-pixel data transmitted by the data transmission circuit in the image data.

9. The timing controller circuit of claim 7, wherein the input timing of the image data is 8Kx2K@120Hertz(Hz).

10. The timing controller circuit of claim 7, wherein the frame rate of the display panel is increased by at least 2 times.

11. A timing controller circuit for controlling at least an in-panel gate circuit in a display panel, the timing controller circuit comprising: Data receiving circuit, used to receive image data; A timing detection circuit is coupled to the data receiving circuit and is used to detect the input timing of the image data; A data processing circuit is coupled to the timing detection circuit and performs data masking processing on the image data according to the input timing of the image data to generate a data masking signal. A control circuit, coupled to the timing detection circuit, is used to determine the in-panel gate timing of the in-panel gate circuit based on the input timing of the image data, and to generate a timing control output based on the in-panel gate timing. as well as A data transmission circuit, coupled to the control circuit and the data processing circuit, is used to transmit the timing control output and the data masking signal to the display panel. The data masking signal is output to the source drive circuit of the display panel, and the data masking signal controls the source drive circuit to mask the odd line data and drive only the even line data in each even frame of the image data, and controls the source drive circuit to mask the even line data and drive only the odd line data in each odd frame of the image data.

12. The timing controller circuit of claim 11, wherein the timing controller circuit includes a master timing controller and a slave timing controller; the master timing controller is used to control the gate driving of all sub-pixels of the display panel and to control the data driving of a portion of the sub-pixels among all the sub-pixels of the display panel; the master timing controller includes the data receiving circuit, the timing detection circuit, the data processing circuit, the control circuit, and the data transmission circuit; and the slave timing controller is used to control the data driving of another portion of the sub-pixels among all the sub-pixels of the display panel.

13. The timing controller circuit of claim 11, wherein the charging time for each data line of the display panel is increased by a factor of 2.

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