Apparatus and method for multi-level signaling with data-over-command functionality

Abstract

The present disclosure relates to apparatuses and methods for multi-level signaling with data-over-command functionality. A semiconductor device can implement data-over-command functionality on a multi-level signaling data bus architecture. The multi-level signaling data bus architecture can support a multi-level communication architecture that includes a plurality of channels each including conversion of M bit streams to N multi-level signals, where M is greater than N. A bit stream includes a plurality of bits provided in series, where each bit of the bit stream is provided over a period of time. The multi-level signaling data bus is adapted to transmit data using a first set of assigned states of the data bus and to transmit commands using at least a second assigned state of the data bus.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to devices and methods for multi-level signaling with data-over-command functionality. BACKGROUND

[0002] The pursuit of making computing systems more powerful and more efficient has led to advances in interface communication to improve throughput without increasing and, ideally, reducing energy consumption. Generally, as clock speeds increase, the data transition time on an interface bus needs to be increased to match the faster clock speed. Future double data rate (DDR) dynamic random access memory (DRAM) performance targets will soon exceed the DRAM transistor switching capability. Some systems have implemented data encoding and specialized, multi-level (e.g., more than two levels) bus architectures to increase the throughput over an interface bus. However, these specialized architectures can increase cost and complexity, can require additional input / output (I / O) pins, and can be limited to data transmission over a data bus. SUMMARY

[0003] In one aspect, the present disclosure relates to a device comprising: a driver circuit configured to encode a set of data bit streams during a first time period for simultaneous transmission to a receiving apparatus via a set of multi-level signal lines of a data bus, wherein during a second time period, the driver circuit is configured to encode a special action command for transmission to the receiving apparatus via the set of multi-level signal lines of the data bus, wherein the special action command indicates an action to be performed by the receiving apparatus, wherein a count of the set of data bit streams is greater than the count of the set of multi-level signal lines.

[0004] In another aspect, the present disclosure relates to a device comprising: a receiver circuit configured to determine a state of a set of multi-level signal lines of a data bus, wherein in response to the state of the set of multi-level signal lines of the data bus having one of a first set of assigned states, a respective bit of each of a set of data bit streams is recovered, wherein in response to the state of the set of multi-level signal lines of the data bus having a second assigned state different from any of the first set of assigned states, a special action command is recovered and an action indicated by the special action command is caused to be performed, wherein a count of the set of data bit streams is greater than the count of the set of multi-level signal lines.

[0005] In another aspect, the disclosure relates to a method comprising: during a first time period: encoding a set of data bit streams at a driver circuit of a first semiconductor device for simultaneous transmission to a second semiconductor device via a set of multi-level signal lines of a data bus; and transmitting the set of encoded data bit streams on the set of multi-level signal lines of the data bus, wherein a count of the set of data bit streams is greater than the count of the set of multi-level signal lines; and during a second time period: encoding a special action command for transmission to the second semiconductor device via the set of multi-level signal lines of the data bus, wherein the special action command indicates an action to be performed by the receiving device; and transmitting the encoded special action command on the set of multi-level signal lines of the data bus. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a block diagram of a device according to embodiments of the disclosure.

[0007] Figure 2 is a schematic block diagram of a semiconductor device 200 according to embodiments of the disclosure.

[0008] Figure 3 is a block diagram of a device 300 for a multi-level communication architecture comprising a pair of signal lines according to embodiments of the disclosure.

[0009] Figure 4 is an encoding map 400 for encoding three bit streams on two signal lines configured to be driven using a multi-level communication architecture according to embodiments of the disclosure.

[0010] Figure 5 is a schematic diagram of a driver 500 for a multi-level communication architecture according to embodiments of the disclosure.

[0011] Figure 6 is an exemplary timing diagram 600 depicting a data mask command on a data bus using a multi-level communication architecture according to embodiments of the disclosure.

[0012] Figure 7 is an exemplary timing diagram 700 depicting a data byte mask command on a data bus using a multi-level communication architecture according to embodiments of the disclosure.

[0013] Figures 8A to 8C depicts an exemplary command architecture on a data bus according to embodiments of the disclosure.

[0014] Figure 9 depicts exemplary tables 901, 902, and 903 showing a pair of signal line currents for each encoded 3-bit value in a multi-level signal data bus architecture according to embodiments of the disclosure. DETAILED DESCRIPTION

[0015] Certain details are set forth below to provide a sufficient understanding of embodiments of the disclosure. However, it will be clear to one skilled in the art that embodiments of the disclosure can be practiced without these specific details. In other instances, well-known structures, materials, and techniques have not been described in detail in order to avoid obscuring the disclosure. Specific embodiments of the present disclosure are described herein with reference to the drawings. Various modifications and changes can be made thereto by those skilled in the art without departing from the broader scope of the disclosure as set forth in the appended claims along with the

[0016] Examples described herein relate to data over command implementations on a multi-level signaling data bus architecture. For example, some input / output (I / O) bus architectures can support a multi-level communication architecture that includes multiple channels. In some embodiments, each channel can be single-ended and can include a single signal line. In other embodiments, each channel can include more than one signal line. For example, an I / O bus can support a channel that includes converting M bit streams to N multi-level signals, where M is greater than N. A bit stream includes a plurality of bits provided in series, where each bit of the bit stream is provided over a period of time. The N multi-level signals can be transmitted over the I / O bus. In one example, 3 bit streams can be converted to 2 tri-level signals. In another example, pulse amplitude modulation (PAM) can be used to convert 2, 3, or 4 bit streams to a single multi-level signal having, for example, 4, 8, 16, etc. levels. Typically, these bit streams can be used to communicate data between devices. However, in some examples, the bit streams can also be implemented to communicate certain commands over the I / O bus by encoding various commands (e.g., pinless data masking, peak current reduction, power reduction, faster bus toggling via proximity on-die termination (ODT) control, loopback functionality, error handling, refresh operations, or any combination thereof) by utilizing an unassigned state. The use of an unassigned state of a multi-level signal on an I / O bus can enhance the capabilities of a semiconductor device without having to rely solely on commands routed over a command bus.

[0017] Figure 1is a block diagram of a device 100 according to embodiments of the present disclosure. The device 100 can include a first device 110 that communicates with a second device 120 over an input / output (I / O) bus. The first device 110 can include I / O interface circuitry 112 that includes driver circuitry 114 for communicating over the I / O bus as well as receiver and decoder circuitry 116. The second device 120 can include I / O interface circuitry 122 that includes driver circuitry 124 for communicating over the I / O bus as well as receiver and decoder circuitry 126. The I / O bus can support a multi-level communication architecture that includes a plurality of channels. In some embodiments, each channel can be single-ended and can include a single signal line. In other embodiments, each channel can include more than one signal line. In one embodiment, the first device 110, the second device 120, and the I / O bus can support a communication that includes converting M bit streams to N multi-level signals, where M is greater than N. A bit stream includes a plurality of bits that are provided serially, where each bit of the bit stream is provided over a period of time. For example, a first bit is provided over a first time period, and a second bit is provided over a second time period that is after the first time period, and a third bit is provided over a third time period that is after the second time period, and so on. The successive bits that are provided in this serial manner represent a stream of bits. The N multi-level signals can be transmitted over the I / O bus. In one example, 3 bit streams can be converted to 2 tri-level signals. In another example, pulse amplitude modulation (PAM) can be used to convert 2, 3, or 4 bit streams to a single multi-level signal having, for example, 4, 8, 16, etc. levels. In some examples, the first device 110 can include a memory controller or a processing system and / or the second device 120 can include a memory that includes volatile memory and / or non-volatile memory. In some examples, the second device 120 can include a dynamic random access memory (DRAM), such as a double data rate (DDR) DRAM or a low power DDR DRAM. However, it should be noted that a memory is not a necessary component of the present disclosure. Rather, the present disclosure can be applied to any two or more devices on-chip or off-chip that communicate with each other using multi-level signaling.

[0018] The driver circuitry 114 can include circuitry that applies bit stream conversion to a set of M bit streams to generate N multi-level signals and drives the N multi-level signals as channels on the I / O bus. Similarly, the driver circuitry 124 can include circuitry that applies bit stream conversion to a set of M bit streams to generate N multi-level signals and drives the N multi-level signals as channels on the I / O bus. In some examples, the driver circuitry 114 can include modifications to existing DDR drivers to drive multi-level signals onto channels of the I / O bus.

[0019] For each channel, receiver and decoder circuit 116 can include a decoder configured to recover the set of M bit streams by decoding the N multi-level signals received over the channel of the I / O bus as provided by driver circuit 124. Further, receiver and decoder circuit 126 can include a decoder configured to recover the set of M bit streams by decoding the N multi-level signals received over the channel of the I / O bus as provided by driver circuit 114. In some embodiments, receiver and decoder circuit 116 and receiver and decoder circuit 126 can include comparator and decoding logic to recover the set of M bit streams.

[0020] In operation, first device 110 and second device 120 can communicate over the I / O bus to transfer information, such as data, addresses, commands, etc. Although the I / O bus is shown as bidirectional, the I / O can also be a unidirectional bus. I / O interface circuit 112 and I / O interface circuit 122 can implement a multi-level communication architecture. In a multi-level communication architecture, a symbol is sent over a channel during a symbol period. A symbol can be a single value on a signal line of the channel, or can be a combination of values provided on multiple signal lines of the channel. A symbol can represent a channel state. A receiver can determine an output signal value based on the values transmitted on the signal lines of the channel. In a single-ended architecture, the signal line value can be compared to one or more reference values to determine the output signal value. The receiver has a period of time for determining and latching the output signal value from the time the output signal transitions to the current value to the time the output signal transitions to the next value. The transition time can be determined based on a clock signal and based on setup and hold times for a transition from one value to another. In a multi-level communication architecture with a fixed slew rate or fixed rise / fall times, inherent jitter can occur due to different amplitude offsets (e.g., from VH to VL versus from VMID to VH or VL). The amount of jitter can be based on the slew rate, rise / fall times, multi-level amplitude values, or combinations thereof. In some instances, the transition time can also be affected by process, voltage, and temperature variations.

[0021] In an example, driver circuit 114 can generate a symbol for a channel by converting bits from each of the M bit streams into N multi-level signals. The symbol can be transmitted to receiver and decoder circuit 126 via N signal lines of the I / O bus. Receiver and decoder circuit 126 can detect the levels on the N signal lines and decode the levels to retrieve the bits from each of the M streams. By using multi-level signal lines, more data can be transmitted during a symbol period compared to using binary signal line levels. In an example, M is 3 and N is 2, and the signal lines of the I / O bus are capable of being driven to three independent levels. In another example, M is 2 and N is 1, and the signal lines of the I / O bus are capable of being driven to four independent levels (e.g., in a PAM implementation). The communication protocol between driver circuit 124 and receiver and decoder circuit 116 can be similar to the communication protocol between encoder and driver circuit 114 and receiver and decode circuit 126. Driver circuit 114 can include a DRAM driver that has been segmented to drive multiple (e.g., more than 2) voltage levels on the signal lines.

[0022] In some examples, certain signal lines on the I / O bus can be dedicated to data bit stream transmission between first device 110 and second device 120. However, in some examples, driver circuits 114 and 124 and receiver and decoders 116 and 126 can each be adapted to communicate certain special action commands (e.g., no pin data mask, peak current reduction, power reduction, faster bus turnarounds via near on-die termination (ODT) control, loopback functionality, error handling, refresh operations, or any combination thereof) by utilizing unassigned transmission states, through signal lines dedicated to data bit stream transmission. The use of unassigned states of multi-level signals on the I / O bus can enhance the capabilities of the semiconductor device without having to rely solely on commands routed through a command bus.

[0023] Figure 2is a schematic block diagram of a semiconductor device 200 according to embodiments of the present disclosure. For example, the semiconductor device 200 can include a chip 235. The chip 235 can include a clock input circuit 205, an internal clock generator 207, an address command input circuit 215, an address decoder 220, a command decoder 225, a plurality of row decoders 230, a memory cell array 245 including sense amplifiers 250 and pass gates 295, a plurality of column decoders 240, a plurality of read / write amplifiers 265, input / output (I / O) circuitry 270, cold data sense circuitry 271, and a voltage generator 290. The semiconductor device 200 can include a plurality of external terminals including address and command terminals coupled to a command / address bus 210, clock terminals CK and / CK, data terminals DQ, DQS, and DM, and power supply terminals VDD, VSS, VDDQ, and VSSQ. The chip 235 can be mounted on a substrate, such as a memory module substrate, a motherboard, or the like.

[0024] The memory cell array 245 includes a plurality of banks BANK0-N, each bank BANK0-N including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The number of banks BANK0-N can include 2, 4, 8, 16, or any other number of banks. Each of the banks BANK0-N can be divided into two or more memory planes (e.g., column planes), which can be selected by a column select CS signal from the column decoders 240. In some examples, each of the banks BANK0-N can include 2, 4, 8, 16, 32, etc. column planes. Selection of word lines WL for each bank is performed by a corresponding row decoder 230, and selection of bit lines BL is performed by a corresponding column decoder 240. A plurality of sense amplifiers 250 are located for their corresponding bit lines BL and are coupled to at least one respective local I / O line, which is further coupled to a respective one of at least two main I / O line pairs via pass gates TG 295 acting as switches.

[0025] The address / command input circuit 215 can receive address signals and bank address signals from the outside at the command / address terminals via the command / address bus 210 and transmit the address signals and bank address signals to the address decoder 220. The address decoder 220 can decode the address signals received from the address / command input circuit 215 and provide a row address signal XADD to the row decoders 230 and a column address signal YADD to the column decoders 240. The address decoder 220 can also receive the bank address signals and provide the bank address signals BADD to the row decoders 230 and the column decoders 240.

[0026] The address / command input circuit 215 can receive command signals from external (e.g., a memory controller 205, for example) at command / address terminals via a command / address bus 210 and provide the command signals to the command decoder 225. The command decoder 225 can decode the command signals and generate various internal command signals. For example, the internal command signals can include row command signals for selecting a word line, read or write commands, and / or column command signals for selecting a bit line.

[0027] When a read command is issued and an activate and read command (ACT / RW) is supplied to the row address and column address in time, read data is read out from the memory cells in the memory cell array 245 designated by the row address and column address. The read / write amplifier 265 can receive the read data DQ and provide the read data DQ to the IO circuit 270. The IO circuit 270 can provide the read data DQ to external via data terminals DQ along with a data strobe signal at DQS and / or a data mask signal at DM. The IO circuit 270 can include a multi-level signal driver 271 configured to encode and drive multi-level voltages on the signal lines on the output data bus to the data terminals DQ. The multi-level signal driver 271 can include Figure 1 an output encoder and driver circuit 114 and / or an output encoder and driver circuit 124.

[0028] Similarly, when a write command is issued and an ACT and write command R / W is supplied to the row address and column address in time, and then the IO circuit 270 can receive write data at the data terminals DQ, a data strobe signal at DQS and / or a data mask signal at DM, and provide the write data to the memory cell array 245 via the read / write amplifier 265. Thus, the write data can be written into the memory cells designated by the row address and column address. To receive and decode the write data, the IO circuit 270 can include a multi-level signal receiver 272 configured to receive and decode multi-level voltages on the signal lines on the input data bus. The multi-level signal receiver 272 can include Figure 1 a receiver and decoder circuit 116 and / or a receiver and decode circuit 126.

[0029] However, in some examples, the multi-level signal drivers 271 and the multi-level signal receivers 272 of the I / O circuit 270 can be configured to communicate (e.g., transmit and / or receive, respectively) certain special action commands over the DQ terminals by encoding various special action commands (e.g., no-pin data mask, peak current reduction, power reduction, faster bus turnarounds via near on-die termination (ODT) control, loopback function, error handling, refresh operation, or any combination thereof) by utilizing unassigned signal lines to encode states. The use of unassigned states of the multi-level signals on the DQ data terminals can enhance the capabilities of the semiconductor device without having to rely solely on commands routed over the command and address bus 210.

[0030] Turning to the explanation of the external terminals included in the semiconductor device 200, the clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal, including the complementary external clock signal, can be supplied to the clock input circuit 205. The clock input circuit 205 can receive the external clock signal and generate an internal clock signal ICLK. The clock input circuit 205 can provide the internal clock signal ICLK to the internal clock generator 207. The internal clock generator 207 can generate a phase-controlled internal clock pulse signal LCLK based on the received internal clock signal ICLK and a clock enable signal CKE from the address / command input circuit 215. Although not limited thereto, a DLL circuit can be used as the internal clock generator 207. The internal clock generator 207 can provide the phase-controlled internal clock signal LCLK to the IO circuit 270. The IO circuit 270 can use the phase-controlled internal clock signal LCLK as a timing signal for determining the output timing of read data.

[0031] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to the voltage generator circuit 290. The voltage generator circuit 290 can generate various internal voltages VPP, VOD, VARY, VPERI, and the like based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the row decoder 230, the internal voltages VOD and VARY are mainly used in the sense amplifiers 250 included in the memory cell array 245, and the internal voltage VPERI is used in many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. The IO circuit 270 can receive the power supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ can be the same voltages as the power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used for the IO circuit 270.

[0032] Figure 3is a block diagram of a device 300 for a multi-level communication architecture including a pair of signal lines according to embodiments of the present disclosure. The device 300 can include a signal driver 314 coupled to a receiver 326 via an I / O bus. The signal driver 314 can be implemented in the driver circuit 114 and / or the driver circuit 124 of Figure 1 and the receiver 326 can be implemented in the receiver and decoder circuit 116 and / or the receiver and decoder circuit 126 of Figure 1 .

[0033] The signal driver 314 can include an encoder 330 coupled to a driver 340 and a driver 342. The encoder 330 can be configured to receive the bit streams ATX, BTX, and CTX. The encoder 330 can encode ATX, BTX, and CTX to provide XI, X2, Yl, and Y2 control signals. The driver 340 can receive the XI and X2 control signals and can drive voltages on the X signal lines of the I / O bus based on the XI and X2 control signals. The driver 342 can receive the Yl and Y2 control signals and can drive voltages on the Y signal lines of the I / O bus based on the Yl and Y2 control signals. Thus, the signal driver 314 can convert the ATX, BTX, and CTX bit streams to two multi-level signals that will be driven on the I / O bus.

[0034] The receiver 326 can include comparators 350, 352, 354, and 356 coupled to a decoder 360. The comparators 350 and 352 can be configured to receive signals from the X signal lines of the I / O bus and the comparators 354 and 356 can be configured to receive signals from the Y signal lines of the I / O bus. The comparator 350 can compare the signals of the X signal lines to a high reference signal HIREF to provide a Zl signal to the decoder 360. The comparator 352 can compare the signals of the X signal lines to a low reference signal LOREF to provide a Z2 signal to the decoder 360. The comparator 354 can compare the signals of the Y signal lines to the HIREF signal to provide a Z3 signal to the decoder 360. The comparator 354 can compare the signals of the Y signal lines to the LOREF signal to provide a Z4 signal to the decoder 360. The decoder 360 can include logic to generate ARX, BRX, and CRX bit streams based on the Zl, Z2, Z3, and Z4 signals from the comparators 350, 352, 354, and 356, respectively. The ARX, BRX, and CRX signals can be logical equivalents of the data transmitted by the ATX, BTX, and CTX signals.

[0035] In operation, the ATX, BTX, and CTX signals can be three bit streams to be transmitted over the I / O bus. Rather than sending each bit stream on a separate signal line, the signal driver 314 can encode the ATX, BTX, and CTX signals to be transmitted over two signal lines using a multi-level signal. For example, the encoder 330 can receive the ATX, BTX, and CTX signals, and during each symbol period, can encode a symbol in the form of X1, X2, Y1, and Y2 control signals to control the driver to drive the pair of signal lines of the I / O bus to respective voltages. Although Figure 3 The embodiments described in the Summary provide for encoding three bit streams ATX, BTX, and CTX that are merged, but in other embodiments, one bit stream can be provided, and three consecutive bits can be provided as three data bits for encoding. For example, every third bit of data from the bit stream can be provided as a first data bit, every third bit of data of a subsequent bit can be provided as a second data bit, and every third bit of yet another subsequent bit can be provided as a third data bit to provide three data bits for encoding from one bit stream.

[0036] The encoder 330 can include control logic to provide each of the X1, X2, Y1, and Y2 control signals. The driver 340 can drive the voltage on the X signal line of the I / O bus in response to the X1 and X2 control signals. The driver 342 can drive the voltage on the Y signal line of the I / O bus in response to the Y1 and Y2 control signals. The voltages driven by the driver 340 and the driver 342 can be one of three levels.

[0037] The comparators 350 and 352 can receive the voltage from the X signal line, and the comparators 354 and 356 can receive the voltage from the Y signal line. The comparator 350 can provide a Z1 signal based on a comparison between the voltage of the X signal line and the REFHI voltage. The comparator 352 can provide a Z2 signal based on a comparison between the voltage of the X signal line and the REFLO voltage. The comparator 354 can provide a Z3 signal based on a comparison between the voltage of the Y signal line and the REFHI voltage. The comparator 356 can provide a Z4 signal based on a comparison between the voltage of the X signal line and the REFHI voltage. The decoder 360 can include decoding logic to generate ARX, BRX, and CRX signals based on the Z1, Z2, Z3, and Z4 signals.

[0038] The ARX, BRX, and CRX signals can be provided to downstream circuitry for processing, such as being processed as data to be stored at a memory or data that has been retrieved from a memory. However, in some examples, the ARX, BRX, and CRX can also be configured to communicate certain commands over the DQ terminals by utilizing the unassigned states to encode various commands, such as no pin data masking, peak current reduction, power reduction, faster bus toggling via near on-die termination (ODT) control, loopback functionality, error handling, refresh operations, or any combination thereof. The use of unassigned states of the multi-level signals on the DQ data terminals can enhance the capabilities of the semiconductor device without having to rely solely on commands routed over the command and address buses.

[0039] Although Figure 3 The apparatus 300 depicts encoding three bit streams to be transmitted over two multi-level signal lines of an I / O bus, but the apparatus 300 can be altered to include additional or fewer bit streams, more or fewer than two signal lines, and the ability to drive more than three voltage levels on each signal line.

[0040] Figure 4 is an encoding map 400 for encoding three bit streams on two signal lines configured to be driven using a multi-level communication architecture according to embodiments of the present disclosure. The encoding map 400 can be used by the encoder 330 of Figure 2 The encoder 330 of FIG. 3A can use the encoding map 400 to encode the ATX, BTX, and CTX bit streams as multi-level signals to be driven on the X and Y signal lines of the I / O bus via the driver 340 and the driver 342, respectively. The encoding map 400 includes a first table 410 including possible logical combinations of the A, B, and C signals and a second table 420 including exemplary unique multi-level encodings of the X and Y signal lines for each logical combination of the A, B, and C signals. For example, when the A, B, and C bit streams each have a logical value of zero (e.g., row 1 of the first table 410), the X and Y signals can be driven to a low voltage. In another example, if the A bit stream has a logical value of zero and the B and C bit streams have a logical value of one, the X signal can be driven to an intermediate voltage and the Y signal can be driven to a high voltage. It should be appreciated that different mappings can be implemented to encode the A, B, and C signals on the X and Y signals as long as each unique logical combination of the A, B, and C signals maps to a unique combination of voltages on the X and Y signals. For example, the A, B, and C bit streams having a logical value of zero can map to the X and Y signals having a high voltage instead of a low voltage, and the A, C, and B bit streams having a logical value of one can be mapped to the X and Y signals having a low voltage instead of a high voltage.

[0041] In some examples, certain combinations of states of the A, B, and C signals can be provided to downstream circuitry for processing, such as being processed as data to be stored at a memory or data retrieved from a memory. However, in some examples, A, B, and C can also be configured to communicate certain commands over the data bus by encoding various commands with unassigned data states. Examples of commands to be encoded can include pinless data masking, peak current reduction, power reduction, faster bus toggling via near on-die termination (ODT) control, loopback functionality, error handling, refresh operations, or any combination thereof. The use of unassigned states of the multi-level signals on the DQ data terminals can enhance the capabilities of the semiconductor device without having to rely solely on commands routed over the command and address buses.

[0042] Figure 5 is a schematic diagram of a driver 500 for a multi-level communication architecture according to embodiments of the present disclosure. The driver 500 can include an X signal line driver 510 configured to drive an XOUT signal to an X signal line based on XI and X2 control signals and a Y signal line driver 520 configured to drive a YOUT signal to a Y signal line based on Yl and Y2 control signals. The X signal line driver 510 can be implemented in the driver 340 of Figure 1 of FIG. 1 14 and / or 124 and / or Figure 3 of FIG. 1 14 and / or 124 and / or Figure 1 of FIG. 1 14 and / or 124 and / or Figure 3 of FIG. 1 14 and / or 124 and / or

[0043] The X signal line driver 510 can include an X1 signal line driver 512 and an X2 signal line driver 514 coupled in parallel between a high supply voltage and a low supply voltage. The X1 signal line driver 512 can be configured to drive a voltage on the XOUT signal in response to an X1 control signal. For example, the X1 signal line driver 512 can drive the XOUT signal to a high voltage via a pull-up (e.g., p-type) transistor in response to the X1 control signal having a low logic value, and can drive the XOUT signal to a low voltage via a pull-down (e.g., n-type) transistor in response to the X1 control signal having a high logic value. Similarly, the X2 signal line driver 514 can be configured to drive a voltage on the XOUT signal in response to an X2 control signal. For example, the X2 signal line driver 514 can drive the XOUT signal to a high voltage via a pull-up transistor in response to the X2 control signal having a low logic value, and can drive the XOUT signal to a low voltage via a pull-down transistor in response to the X2 control signal having a high logic value. The combination of the X1 signal line driver 512 and the X2 signal line driver 514 can drive the XOUT signal to three logic voltage values, e.g., low, medium, and high. For example, when both the X1 signal line driver 512 and the X2 signal line driver 514 are driving the XOUT to a high voltage, the XOUT signal can have a high voltage. When both the X1 signal line driver 512 and the X2 signal line driver 514 are driving the XOUT to a low voltage, the XOUT signal can have a low voltage. When one of the X1 signal line driver 512 or the X2 signal line driver 514 is driving the XOUT to a high voltage, and the other is driving the XOUT to a low voltage, the XOUT signal can have an intermediate voltage level.

[0044] The Y signal line driver 520 can include a Yl signal line driver 522 and a Y2 signal line driver 524 coupled in parallel between the high supply voltage and the low supply voltage. The Yl signal line driver 522 can be configured to drive a voltage on the YOUT signal in response to a Yl control signal. For example, the Yl signal line driver 522 can drive the YOUT signal to the high voltage via a pull-up transistor in response to the Yl control signal having a low logic value, and can drive the YOUT signal to the low voltage via a pull-down transistor in response to the Yl control signal having a high logic value. Similarly, the Y2 signal line driver 524 can be configured to drive a voltage on the YOUT signal in response to a Y2 control signal. For example, the Y2 signal line driver 524 can drive the YOUT signal to the high voltage via a pull-up transistor in response to the Y2 control signal having a low logic value, and can drive the YOUT signal to the low voltage via a pull-down transistor in response to the Y2 signal having a high logic value. Similar to the operation of the X signal line driver 510, the combination of the Yl signal line driver 522 and the Y2 signal line driver 524 can drive the YOUT signal to three logic voltage values, such as low, mid, and high.

[0045] In operation, the X signal line driver 510 and the Y signal line driver 520 can drive one of three voltages to the XOUT and YOUT signals, respectively. The X signal line driver 510 can drive the XOUT signal in response to the Xl and X2 control signals, and the Y signal line driver 520 can drive the YOUT signal in response to the Yl and Y2 control signals. In an example, when the Xl control signal has a low logic value, the pull-up transistor of the Xl signal line driver 512 is enabled to couple the high supply voltage to the XOUT signal, and the pull-down transistor is disabled. When the Xl control signal has a high logic value, the pull-up transistor of the Xl signal line driver 512 is disabled, and the pull-down transistor is enabled to couple the low supply voltage to the XOUT signal. The operation of the X2 signal line driver 514, the Yl signal line driver 522, and the Y2 signal line driver 524 in response to the X2, Yl, and Y2 control signals, respectively, can be similar to the Xl signal line driver 512 in response to the Xl control signal. The XOUT signal can be a combination of the voltages driven by the Xl signal line driver 512 and the X2 signal line driver 514. The YOUT signal can be a combination of the voltages driven by the Yl signal line driver 522 and the Y2 signal line driver 524. The XOUT and YOUT signals can have a high voltage VH, a low voltage VL, or a mid voltage VMID between the high and low supply voltages. The mid voltage can be achieved when the Xl signal line driver 512 (or the Yl signal line driver 522) and the X2 signal line driver 514 (or the Y2 signal line driver 524) are driving different voltages (e.g., one drives the high supply voltage and the other drives the low supply voltage).

[0046] Figure 6 This is an exemplary timing diagram 600 depicting a data pair masking command on a data bus using a multi-level communication architecture according to an embodiment of the present disclosure. (As shown in...) Figure 6 As shown, each of the four driver circuits 610(1) to (4) can drive three corresponding bits on two corresponding signal lines. In some instances, driver circuits 610(1) to (4) can... Figure 1 The driver circuits 114 and / or 124, Figure 2 Multi-level signal driver circuit 271 Figure 3 Driver circuit 314 Figure 5 The signal depicted in timing diagram 600 may be implemented in driver 500 or any combination thereof. For example, the signal may be received by one or more receiver circuits (e.g., ...). Figure 1 Receiver circuits 116 and / or 126 Figure 2 Multi-level signal receiver circuit 272 Figure 3 The receiver circuit 316 or any combination thereof consumes power.

[0047] As shown in timing diagram 600, during the first transmission burst from time T0 to T1 (e.g., the first transmission burst period), each of the four driver circuits 610(1) to (4) can serially transmit a corresponding first set of data. The corresponding first set of data may comprise four individual 3-bit data groups serially transmitted via two corresponding signal lines. In some instances, it may be based on... Figure 4 Table 400 encodes a 3-bit data group on two signal lines.

[0048] At time T1, a second transmission burst (e.g., the start of the second transmission burst period) may begin transmitting the second set of data. However, at time T1, the first driver circuit 610(1) may transmit a data pair masking command, which may be encoded as two signals driven to a logic high value (“H”). In response to the data pair masking command, the receiver (e.g., Figure 1 Receiver circuits 116 and / or 126 Figure 2 Multi-level signal receiver circuit 272 Figure 3 The receiver circuit 316 (or any combination thereof) can shield any data received via the first pair of signal lines corresponding to the first driver circuit 610 (1). In some instances, in response to a data pair shielding command, the receiver can shield data received via the first pair of signal lines of the data bus during and / or after a second transmission burst. In other instances, in response to a data pair shielding command, the receiver can shield data received via the first pair of signal lines of the data bus during the first transmission burst. Each of the three remaining driver circuits 610 (2) to (4) can serially transmit the corresponding second set of data to be decoded by the receiver circuit.

[0049] In some instances, a data pair masking command can be configured such that it must be enabled or activated for each transmission burst. In other instances, once enabled, the data pair masking command may remain enabled until a second data pair masking command is received from the corresponding driver circuits 610(1) to (4). Timing diagram 600 is exemplary. Without departing from the scope of this disclosure, the data pair masking command may be implemented in different multilevel communication architectures. In some instances, without departing from the scope of this disclosure, a transmission burst may contain more or fewer than four data groups of serial transmission, and / or a data bus may contain more or fewer than eight signal lines (e.g., and corresponding driver circuits). Finally, without departing from the scope of this disclosure, different unassigned codes associated with the data bus may be used to implement the data pair masking command.

[0050] although Figure 6 The description refers to transmitting a data pair masking command during the initial time period of the second transmission burst. However, it should be understood that, without departing from the scope of this disclosure, the data pair masking command may also be transmitted during the end time period of the second transmission burst or during the middle time period of the second transmission burst. If a data pair masking command is received during the end time period of the second transmission burst, then data bits received through the first pair of signal lines before the data pair masking command during the second transmission burst can be masked. If a data pair masking command is received during the middle time period of the second transmission burst, then data bits received through the first pair of signal lines before and after the data pair masking command during the second transmission burst can be masked.

[0051] Figure 7 This is an exemplary timing diagram 700 depicting a data byte masking command on a data bus using a multi-level communication architecture according to an embodiment of the present disclosure. (As shown in...) Figure 7 As shown, each of the four driver circuits 710(1) to (4) can drive three corresponding bits on two corresponding signal lines. In some instances, driver circuits 710(1) to (4) can... Figure 1 The driver circuits 114 and / or 124, Figure 2 Multi-level signal driver circuit 271 Figure 3 Driver circuit 314 Figure 5 The signal depicted in timing diagram 700 may be implemented in driver 500 or any combination thereof. For example, the signal may be received by one or more receiver circuits (e.g., ...). Figure 1 Receiver circuits 116 and / or 126 Figure 2 Multi-level signal receiver circuit 272 Figure 3 The receiver circuit 316 or any combination thereof consumes power.

[0052] As shown in timing diagram 700, during a first transmission burst from time TO to Tl, each of the four driver circuits 710(1) through (4) can serially transmit a respective first set of data. The respective first set of data can include four individual 3-bit data groups serially transmitted over two respective signal lines. In some examples, the 3-bit data groups can be encoded on the two signal lines based on Figure 4 Table 400 of FIG. 4.

[0053] At time Tl, a second transmission burst can begin transmitting a second set of data. However, at time Tl, the first driver circuit 610(1) can transmit a data byte mask command, which can be encoded as two signals driven to a logic high value ("H"). In response to the data byte mask command, a receiver (e.g., receiver circuit 116 and / or 126 of FIG. 1, Figure 1 receiver circuit 316 of FIG. 3, or any combination thereof) can mask data received over the signal lines of the data bus (e.g., including data transmitted by all driver circuits 710(1) through (4)). In some examples, in response to the data byte mask command, the receiver can mask data received over the signal lines of the data bus during and / or after the second transmission burst. In other examples, in response to the data byte mask command, the receiver can mask data received over the signal lines of the data bus during the first transmission burst. Figure 2 Figure 3 In some examples, the data byte mask command can be set such that it must be enabled or activated for each transmission burst. In other examples, once enabled, the data byte mask command can remain enabled until a second data byte mask command is received from the respective driver circuits 710(1) through (4). In some examples, the data byte mask command can be transmitted by a designated one of the driver circuits 710(1) through (4). In other examples, the data byte mask command can be transmitted by any or all of the driver circuits 710(1) through (4).

[0054] Timing diagram 700 is exemplary. The data byte mask command can be implemented in different multi-level communication architectures without departing from the scope of the present disclosure. In some examples, a transmission burst can include more or fewer than four data groups, and / or a data bus can include more or fewer than 8 signal lines (e.g., and corresponding driver circuits) without departing from the scope of the present disclosure. Finally, the data byte mask command can be implemented using different unassigned codes associated with a data bus without departing from the scope of the present disclosure.

[0055] Although

[0056] Although Figure 7 ​The description describes transmitting a data byte masking command during the initial time period of the second transmission burst. However, it should be understood that, without departing from the scope of this disclosure, the data byte masking command may also be transmitted during the end time period of the second transmission burst or during the middle time period of the second transmission burst. If a data byte masking command is received during the end time period of the second transmission burst, then data bits received through all signal lines before the data byte masking command during the second transmission burst can be masked. If a data byte masking command is received during the middle time period of the second transmission burst, then data bits received through all signal lines before and after the data byte masking command during the second transmission burst can be masked.

[0057] Figures 8A to 8C An exemplary data bus command architecture is described according to embodiments of the present disclosure. Figure 8A A first timing diagram 800 is depicted according to an embodiment of the present disclosure, showing a situation where no command has been received on the data bus. Figure 8B A second timing diagram 801 depicts a data bus receiving a command according to an embodiment of the present disclosure. As shown in... Figure 8A and 8B As shown, each of the four driver circuits 810(1) to (4) can drive three corresponding bits on two corresponding signal lines. In some instances, driver circuits 810(1) to (4) can... Figure 1 The driver circuits 114 and / or 124, Figure 2 Multi-level signal driver circuit 271 Figure 3 Driver circuit 314 Figure 5 The signals depicted in timing diagrams 800 and 801 may be implemented in driver 500 or any combination thereof. For example, the signals may be received by one or more receiver circuits (e.g., ...). Figure 1 Receiver circuits 116 and / or 126 Figure 2 Multi-level signal receiver circuit 272 Figure 3 The receiver circuit 316 or any combination thereof consumes power.

[0058] As shown in both timing diagrams 800 and 801, during the first transmission burst from time T0 to T1, each of the four driver circuits 810(1) to (4) can serially transmit a corresponding first set of data. The corresponding first set of data may contain eight individual 3-bit data groups serially transmitted via two corresponding signal lines. In some instances, it may be based on... Figure 4 Table 400 encodes a 3-bit data group on two signal lines.

[0059] refer to Figure 8AAt time T1, driver circuits 810(1) to (4) can switch all signal lines to logic low values ​​to indicate the end of the burst without any special action.

[0060] refer to Figure 8B At time T1, one or more of the driver circuits 810(1) to (4) can transition the signal line to a logic high value to command the receiver (e.g., Figure 1 Receiver circuits 116 and / or 126 Figure 2 Multi-level signal receiver circuit 272 Figure 3 The receiver circuit 316 or any combination thereof performs special actions.

[0061] Figure 8C Table 803 depicts possible implementations of encoding specific action commands according to embodiments of the present disclosure. A may correspond to a signal line associated with driver circuit 810(1), B may correspond to a signal line associated with driver circuit 810(2), C may correspond to a signal line associated with driver circuit 810(3), and D may correspond to a signal line associated with driver circuit 810(4).

[0062] In the first example shown in Table 803, driver circuits 810(1) to (4) can drive all signal lines to A, B, C, and D to low logic values ​​(e.g., as in...). Figure 8A In the timing diagram 800, a special action is indicated as not to be taken. In the second example shown in Table 803, driver circuits 810 (1) to (4) can drive all pairs of signal lines A, B, C, and D to issue a special action command. In some instances, the special action can be predefined (for example, in the mode register). In other instances, the subsequent data bit group following the special action command provides the special action to be taken.

[0063] In the third example shown in Table 803, each of the driver circuits 810(1) to (4) can individually drive its corresponding A, B, C, and D signal lines to a logic high value to issue different corresponding special action commands. For example, the first driver circuit 810(1) can drive the A signal line to a logic high value to issue a first predefined special action command, and the second driver circuit 810(2) can drive the B signal line to a logic high value to issue a second predefined special action command different from the first predefined special action command, and so on. In this third example, driver circuits 8101(1) to (4) may be able to drive four different special action commands. In some examples, the four special action commands may be mutually exclusive (e.g., only one can be set at a time). In other examples, two or more of the special action commands may be sent simultaneously.

[0064] In the fourth and fifth examples shown in Table 803, the first driver circuit 810(1) can drive its respective pair A signal line to a logic high value to activate a special action command (e.g., a special action command flag), and the remaining driver circuits 810(2)-(4) can encode a particular special action to be taken in the respective pair B, pair C, or pair D signal lines. For example, in the fourth example, the remaining driver circuits 810(2)-(4) can encode a particular special action by individually driving two of the respective pair B, pair C, or pair D signal lines to the same value (e.g., driving both signal lines to a logic high value or driving both signal lines to a logic low value). In this fourth example, there are 8 possible different combinations of HH or LL across the pair B, pair C, and pair D signal lines, and each combination can encode a different predefined action to be taken. Thus, in response to the pair A signal line being set to HH, a receiver can decode the HH and LL combinations of the pair B, pair C, and pair D signal lines to determine the particular action to be taken.

[0065] The fifth example is similar to the fourth example, except that the remaining driver circuits 810(2)-(4) are not limited to driving only HH or LL on the respective pair B, pair C, and pair D signal lines. Instead, the remaining driver circuits 810(2)-(4) can individually drive any H or L combination of the respective pair B, pair C, and pair D signal lines. In this fifth example, there are 64 possible different combinations of H and L across the six signal lines making up the pair B, pair C, and pair D signal lines, and each combination can encode a different predefined action to be taken. Thus, in response to the pair A signal line being set to HH, a receiver can decode the H and L combinations of the pair B, pair C, and pair D signal lines to determine the particular action to be taken.

[0066] In some examples, the data-pair mask command can be set such that it must be enabled or activated for each transmission burst. In other examples, once enabled, the data-pair mask command can remain enabled until a second data-pair mask command is received from the respective driver circuits 610(1)-(4). The timing diagram 600 is exemplary. The data-pair mask command can be implemented in different multi-level communication architectures without departing from the scope of the present disclosure. In some examples, a transmission burst can include more or fewer than four serial transmissions of data groups, and / or the data bus can include more or fewer than 8 signal lines (e.g., and corresponding driver circuits) without departing from the scope of the present disclosure. Finally, the data-pair mask command can be implemented using different unassigned codes associated with the data bus without departing from the scope of the present disclosure.

[0067] In some examples, the special action can include a pinless data mask (e.g., as referenced to FIG. 1). Figure 5 and 6described), peak current reduction, power reduction, faster bus turnarounds via proximity on-die termination (ODT) control, loopback functionality (e.g., triggering the memory device to transmit information back to the host over the data bus in response to received data), error handling (e.g., providing error detection codes to the host), refresh operations, or any combination thereof. In one example, the special action command can cause the memory device to shut down or enter an idle mode.

[0068] In an example, rather than basing ODT control on the state of the memory device (e.g., read, write, idle, etc.) flowing through the command bus, the on-data-bus command architecture can be used to directly enable / disable and / or configure the ODT of the memory device by providing a special action command encoded with a particular ODT setting.

[0069] In one example, the on-data-bus command architecture can be implemented to stagger the refreshing of memory of a memory module (e.g., memory module 200) during a module-level refresh. For example, using the fourth and fifth examples, the host controller can individually control when each memory or each memory sub-group of a memory module begins refreshing by providing a module refresh command on the command bus and, in parallel, a special action command on the data bus encoded with an identifier assigned to the particular memory of the memory module. This example will reduce peak current consumption by staggering when each memory begins a refresh operation on the memory module. Figure 2

[0070] Although Figure 8A and 8B depicts a special action command transmitted during an initial time period of the second transmission burst period, it should be appreciated that a data byte mask command can be transmitted at an ending time period of the second transmission burst period or at an intermediate time period of the second transmission burst period without departing from the scope of the present disclosure.

[0071] In yet another example, the special action command can be implemented using a data bus inversion (DBI) algorithm, for example, to reduce the total power of the signals transmitted over the data bus. Figure 9 Exemplary tables 901, 902, and 903 depicting a pair of signal line currents for each encoded 3-bit value in a multi-level signal data bus architecture in accordance with an embodiment of the present disclosure. Figure 9 ​The depicted multi-level signal architecture is a 3-bit architecture on a 2-pin data bus. Table 901 depicts each possible bit combination of three bits, table 902 depicts a multi-level signal line encoding of the bit combinations (e.g., high logic value (voltage), low logic value (voltage), or intermediate logic value (voltage)), and table 903 depicts the amount of current consumed by the transmission. As shown in tables 901, 902, and 903, a few specific bit combinations (e.g., blOO, blOl, and bl l l) can result in peak current consumption (e.g., 2I) because it causes both the X and Y signal lines to be driven into one of the intermediate or high voltage levels. Accordingly, a DBI algorithm can be implemented to cause the bits to be inverted in some manner to reduce the amount of current, and thus the power consumed during transmission. Tables 901, 902, and 903 are exemplary, and it should be appreciated that different encodings can be implemented without departing from the scope of the disclosure. Moreover, as noted above, the command implementation scheme on a data bus can be applied to any multi-level data bus architecture, including a 4-bit architecture on three signal lines or pins, a PAM architecture, etc.

[0072] From the foregoing, it will be appreciated that, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications can be made without deviating from the spirit and scope of the disclosure. Accordingly, the disclosure is not limited except as by the appended claims.

Claims

1. An apparatus comprising: a driver circuit configured to encode a set of data bit streams during a first time period for simultaneous transmission to a receiving device via a set of multi-level signal lines of a data bus, wherein during a second time period, the driver circuit is configured to encode a special action command for transmission to the receiving device via the set of multi-level signal lines of the data bus, wherein the special action command indicates an action to be performed by the receiving device, wherein a count of the set of data bit streams is greater than the count of the set of multi-level signal lines.

2. The apparatus of claim 1, wherein the driver circuit includes a set of drivers each configured to drive a respective one of the set of multi-level signal lines based on the encoded set of data bit streams during the first time period, wherein the set of drivers are each further configured to drive the respective one of the set of multi-level signal lines based on the encoded special action command during the second time period.

3. The apparatus of claim 1, wherein during the second time period, the driver circuit is configured to encode an on-die termination command as the special action command for transmission to the receiving device via the set of multi-level signal lines.

4. The apparatus of claim 1, wherein during the second time period, the driver circuit is configured to encode an interleaved refresh command as the special action command for transmission to the receiving device via the set of multi-level signal lines, the interleaved refresh command including an identifier corresponding to the receiving device of a memory module including a plurality of other receiving devices.

5. The apparatus of claim 4, further comprising a command driver configured to provide a module-level refresh command for transmission to the receiving device via a command bus.

6. The apparatus of claim 1, further comprising a second driver circuit configured to encode a second set of data bit streams during the first time period for simultaneous transmission to the receiving device via a second set of multi-level signal lines of the data bus, wherein during the second time period, the second driver circuit is configured to encode a second special action command for transmission to the receiving device via the second set of multi-level signal lines of the data bus, wherein the second special action command indicates a second action to be performed by the receiving device, the second action being different than the action indicated by the special action command.

7. The apparatus of claim 1, further comprising a second driver circuit configured to encode a second set of data bit streams during the first time period for simultaneous transmission to the receiving device via a second set of multi-level signal lines of the data bus, wherein during the second time period, the second driver circuit is configured to encode a special action flag command for transmission to the receiving device via the second set of multi-level signal lines of the data bus, wherein the special action flag command causes the receiving device to decode the special action command.

8. The apparatus of claim 1, wherein during the first time period, the driver circuit is configured to encode the set of data bit streams based on a first set of assigned states of the set of multi-level signal lines for simultaneous transmission to the receiving device via the set of multi-level signal lines, wherein during the second time period, the driver circuit is configured to encode the special action command based on at least a second assigned state of the set of multi-level signal lines that is mutually exclusive from any of the first set of assigned states for transmission to the receiving device via the set of multi-level signal lines.

9. The apparatus of claim 1, wherein the set of data bit streams includes at least three bit streams and the set of multi-level signal lines includes at least two signal lines.

10. The apparatus of claim 1, wherein the special action command includes at least one of a data bus inversion command, a loopback command that directs the receiving device to provide a response to the set of data bit streams, or an error handling command.

11. The apparatus of claim 1, wherein the first time period precedes the second time period.

12. The apparatus of claim 1, wherein the second time period precedes the first time period.

13. The apparatus of claim 1, wherein the first time period and the second time period occur during a same transmission burst period having a plurality of time periods.

14. The apparatus of claim 1, wherein the first time period occurs during a first transmission burst period having a first plurality of time periods and the second time period occurs during a second transmission burst period having a second plurality of time periods.

15. The apparatus of claim 1, wherein the second time period occurs during an initial time period of a transmission burst period having a plurality of time periods including the initial time period.

16. The apparatus of claim 1, wherein the second time period occurs during a last time period of a transmission burst period having a plurality of time periods including the last time period.

17. The apparatus of claim 1, wherein the second time period occurs after the initial time period and before the last time period of a transmission burst period having a plurality of time periods including the initial time period and the last time period.

18. An apparatus comprising: a receiver circuit configured to determine a state of a set of multi-level signal lines of a data bus, wherein in response to the state of the set of multi-level signal lines of the data bus having one of a first set of assigned states, respective bits of each of a set of data bit streams are recovered, wherein in response to the state of the set of multi-level signal lines of the data bus having a second assigned state different from any of the first set of assigned states, a special action command is recovered and execution of an action indicated by the special action command is caused, wherein a count of the set of data bit streams is greater than the count of the set of multi-level signal lines.

19. The apparatus of claim 18, wherein the receiver circuit includes a set of receivers each configured to receive a respective one of the set of multi-level signal lines.

20. The apparatus of claim 18, wherein the receiver circuit is configured to configure an on-die termination in response to the special action command being an on-die termination command.

21. The apparatus of claim 18, wherein during a module-level refresh, the receiver circuit is configured to initiate a refresh operation in response to receiving an identifier associated with the receiver circuit included in the special action command.

22. The apparatus of claim 21, further comprising a command decoder configured to receive a module-level refresh command via a command bus.

23. The apparatus of claim 18, further comprising a second receiver circuit configured to determine a state of a second set of multi-level signal lines of the data bus, wherein in response to the state of the second set of multi-level signal lines of the data bus having one of the first set of assigned states, respective bits of each of a second set of data bit streams are recovered, wherein in response to the state of the second set of multi-level signal lines of the data bus having a third assigned state different from any of the first set of assigned states, a second special action command different from the special action command is recovered and execution of a second action indicated by the second special action command is caused.

24. The apparatus of claim 18, wherein the special action command is a special action flag command, the apparatus further comprising a second receiver circuit configured to determine a state of a second set of multi-level signal lines of the data bus, wherein in response to the state of the set of multi-level signal lines of the data bus having the second assigned state, a particular special action is recovered based on the state of the second set of multi-level signal lines and execution of the particular special action indicated by the state of the second set of multi-level signal lines is caused.

25. A method comprising: during a first time period: encoding, at a driver circuit of a first semiconductor device, a set of data bit streams for simultaneous transmission to a second semiconductor device via a set of multi-level signal lines of a data bus; and and transmitting encoded sets of data bit streams over the set of multi-level signal lines of the data bus, wherein a count of the sets of data bit streams is greater than the count of the set of multi-level signal lines; and during a second time period: encoding a special action command for transmission to the second semiconductor device via the set of multi-level signal lines of the data bus, wherein the special action command indicates an action to be performed by the second semiconductor device; and transmitting the encoded special action command over the set of multi-level signal lines of the data bus.

26. The method of claim 25, wherein during the second time period, a die-terminated command is encoded as the special action command for transmission to the second semiconductor device via the set of multi-level signal lines.

27. The method of claim 25, wherein during the second time period, an interleaved refresh command is encoded as the special action command for transmission to the second semiconductor device via the set of multi-level signal lines, the interleaved refresh command including an identifier of the second semiconductor device corresponding to a memory module including a plurality of other second semiconductor devices.

28. The method of claim 27, wherein during the second time period, a module-level refresh command is provided from the first semiconductor device to the second semiconductor device via a command bus.

29. The method of claim 25, further comprising: during the first time period: encoding a second set of data bit streams at a second driver circuit of the first semiconductor device for simultaneous transmission to the second semiconductor device via a second set of multi-level signal lines of the data bus; and transmitting the encoded second set of data bit streams over the second set of multi-level signal lines of the data bus; and during the second time period: encoding a second special action command for transmission to the second semiconductor device via the second set of multi-level signal lines of the data bus, wherein the second special action command indicates a second action to be performed by the second semiconductor device, the second action being different than the action indicated by the special action command; and transmitting the encoded second special action command over the second set of multi-level signal lines of the data bus.

30. The method of claim 25, further comprising: during the first time period: encoding a second set of data bit streams at a second driver circuit of the first semiconductor device for simultaneous transmission to the second semiconductor device via a second set of multi-level signal lines of the data bus; and transmitting the encoded second set of data bit streams over the second set of multi-level signal lines of the data bus; and during the second time period: encoding a special action flag command for transmission to the second semiconductor device via the second set of multi-level signal lines of the data bus, wherein the special action flag command causes the second semiconductor device to decode the special action command; and transmitting the encoded special action flag command over the second set of multi-level signal lines of the data bus. transmitting the encoded special action command flag on the second set of multi-level signal lines of the data bus.

31. The method of claim 25, wherein the set of data bit streams includes at least three bit streams, and the set of multi-level signal lines includes at least two signal lines.

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