Storage device and data recovery method thereof

Abstract

The application discloses a storage device and a data recovery method thereof. The storage device comprises a memory, a controller and a power supply. The controller comprises a first detection module, a retry module and a restart module. The first detection module is used for judging whether the memory is abnormal. The retry module is used for performing a predetermined number of retry operations. The restart module is used for controlling the memory to be powered off and powered on after a preset time. The memory completes the discharge operation within the preset time, so as to avoid the controller from repeatedly performing the retry operation and improve the service life of the memory.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a storage device and a data recovery method thereof. Background Technology

[0002] When memory malfunctions, such as feature configuration errors, reset state errors, or the presence of uncorrectable error checking codes (UECCs), existing technologies typically employ software processes for exception handling. These processes include re-executing feature configuration, re-executing reset operation lines, and using a retry table to correct UECCs. However, if these methods fail to remove the memory malfunction, the memory will repeatedly perform exception handling, thus impacting its lifespan. Summary of the Invention

[0003] In view of the above situation, the present invention provides a storage device and a data recovery method thereof, aiming to solve the problem in the prior art that the lifespan of the memory is affected when the anomaly cannot be eliminated.

[0004] This invention provides a storage device, including a memory, a controller, and a power supply; the controller includes:

[0005] The first detection module is used to determine whether the memory is abnormal;

[0006] The retry module is used to perform a predetermined number of retry operations; and

[0007] The restart module is used to control the memory to power off and to control the memory to power on after a preset time; wherein the memory completes the discharge operation within the preset time.

[0008] The present invention also proposes a data recovery method for a storage device, the storage device including a memory, a controller, and a power supply; the controller including a first detection module, a retry module, and a restart module; the data recovery method includes:

[0009] The first detection module determines whether the memory is abnormal;

[0010] When the memory malfunctions, the retry module performs a predetermined number of retry operations;

[0011] The first detection module determines whether the memory remains abnormal after the retry operation;

[0012] When the memory sustains an abnormality, the restart module controls the power supply to stop outputting the supply voltage to the memory; and

[0013] The restart module controls the power supply to output the supply voltage to the memory after a preset time; wherein, the memory completes the discharge operation within the preset time.

[0014] The aforementioned storage device and its data recovery method limit the number of retries through the retry module, thereby preventing the controller from repeatedly performing retry operations, thus improving the lifespan of the memory. Furthermore, by powering off and restarting the memory when it remains abnormal after the last retry operation, the abnormality during the memory reading process can be eliminated. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a storage device according to a preferred embodiment of the present invention.

[0017] Figure 2 for Figure 1 A schematic diagram of the controller module described herein.

[0018] Figure 3 This is a flowchart of a data protection method according to a preferred embodiment of the present invention.

[0019] Figure 4 for Figure 3 Detailed flowchart of step S12.

[0020] Explanation of main component symbols

[0021] Storage device 1

[0022] Memory 10

[0023] Controller 20

[0024] Power supply 40

[0025] Communication bus 50

[0026] First detection module 21

[0027] Retry module 22

[0028] Restart module 23

[0029] Steps S11-S15

[0030] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that when a component is considered to be "connected" to another component, it can be directly connected to the other component or may also have a component that is centrally located. When a component is considered to be "set" on another component, it can be directly set on the other component or may also have a component that is centrally located.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] The specific embodiments of the storage device and data protection method of the present invention will now be described with reference to the accompanying drawings.

[0035] Please see Figure 1 This is a schematic diagram of the storage device 1. The storage device 1 includes a memory 10, a controller 20, a power supply 40, and a communication bus 50.

[0036] The memory 10 is used to store data. The memory 10 is a non-volatile memory, such as at least one of embedded multimedia cards (EMMC), storage cards (SD), USB flash drives, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory, but is not limited thereto.

[0037] The controller 20 can control the memory 10 based on requests from external devices (e.g., a host, CPU, or AP). For example, the controller 20 can send data to the memory 10 for storage or read data stored in the memory 10 based on requests from external devices. The controller 20 can also exchange data with the memory 10 based on requests from external devices. In at least one embodiment of the present invention, both the controller 20 and the memory 10 can be implemented using a single chip, a package, or a module.

[0038] The power supply 40 is used to output a power supply voltage to the memory 10 and the controller 20. In at least one embodiment of the present invention, the power supply 40 can output different power supply voltages according to the needs of the memory 10 and the controller 20.

[0039] The communication bus 50 is used to establish data communication between the memory 10 and the controller 20.

[0040] Please refer to the following: Figure 2 This is a schematic diagram of the controller 20. The controller 20 includes a first detection module 21, a retry module 22, and a restart module 23.

[0041] The first detection module 21 is used to determine whether the memory 10 is abnormal.

[0042] In at least one embodiment of the present invention, the first detection module 21 determines whether the memory 10 is abnormal based on the status code provided by the memory 10 when the memory 10 performs a specified operation. Wherein, if the status code is a first preset code, the memory 10 is identified as abnormal. In at least one embodiment of the present invention, the first preset code is a pass status code, and the specified operation can be a reset operation or a parameter setting operation. The first detection module 21 is further configured to determine whether the memory 10 is abnormal by reading whether the data is an error correction code (ECC) when the memory 10 performs an error correction operation. If the read data is the ECC, the memory 10 is identified as abnormal.

[0043] The retry module 22 is used to perform a predetermined number of retry operations. In at least one embodiment of the present invention, when the memory 10 malfunctions, the retry module 22 performs the predetermined number of retry operations. The retry module 22 is also used to determine whether the memory 10 performs a specified operation. When the memory 10 performs the specified operation, the predetermined number is set to one. When the memory 10 does not perform the specified operation, the retry module 22 further determines whether the memory 10 performs the error correction operation. When the memory 10 performs the error correction operation, the retry module 22 sets the predetermined number to the rated number corresponding to the error correction operation. The rated number can be set according to the number of detection parameters in the error correction table used in the error correction operation.

[0044] The first detection module 21 is further configured to determine whether the memory 10 remains abnormal after the retry operation. When the memory 10 performs the error correction operation and the read data is the ECC, the first detection module 21 identifies that the memory 10 remains abnormal and identifies that there is an Uncorrectable Error Correcting Code (UECC) in the memory 10.

[0045] The restart module 23 is used to control the memory 10 to power off and then control the memory 10 to power on after a preset time to achieve a restart operation.

[0046] In at least one embodiment of the present invention, when the memory 10 remains abnormal after performing the predetermined number of retry operations, the restart module 23 controls the power supply 40 to stop outputting the supply voltage to the memory 10 to achieve a power-off operation of the memory 10, and controls the power supply 40 to output the supply voltage to the memory 10 after the preset time to achieve a power-on operation of the memory 10. During the preset time, the memory 10 performs a discharge operation, and completes the discharge operation within the preset time. The preset time is related to the discharge resistance in the discharge circuit of the memory 10. The larger the resistance value of the discharge resistor in the memory 10, the longer the preset time. In at least one embodiment of the present invention, the preset time is 50 milliseconds.

[0047] The storage device 1 described above, by limiting the number of retries through the retry module 22, can avoid the controller 20 from repeatedly performing retry operations and improve the service life of the memory 10. Furthermore, if the memory 10 remains abnormal after the last retry operation, the memory 10 can be powered off and restarted to eliminate the abnormality of the memory 10 during the data reading process.

[0048] Please refer to the following: Figure 3 This is a flowchart of a data protection method for storage device 1. In at least one embodiment of the present invention, the storage device 1 may include... Figure 1 or Figure 2 More or fewer other hardware or software, or different component configurations. The data protection method includes the following steps:

[0049] S11. The first detection module 21 determines whether the memory 10 is abnormal.

[0050] In at least one embodiment of the present invention, the first detection module 21 determines whether the memory 10 is abnormal based on the status code provided by the memory 10 when the memory 10 performs a specified operation. Wherein, if the status code is a first preset code, the memory 10 is identified as abnormal. In at least one embodiment of the present invention, the first preset code is a pass status code, and the specified operation can be a reset operation or a parameter setting operation. The first detection module 21 is further configured to determine whether the memory 10 is abnormal by reading whether the data is an error correction code (ECC) when the memory 10 performs an error correction operation. If the read data is the ECC, the memory 10 is identified as abnormal.

[0051] S12. When the memory 10 malfunctions, the retry module 22 performs a predetermined number of retry operations.

[0052] Please refer to the following: Figure 4 This is a detailed flowchart of step S12. In at least one embodiment of the present invention, the step of the retry module 22 performing the predetermined number of retry operations includes:

[0053] S121, The retry module 22 determines whether the memory 10 performs a specified operation;

[0054] S122. When the specified operation is performed in the memory 10, the retry module 22 sets the predetermined number of times to one.

[0055] S123. When the memory 10 does not perform the specified operation, the retry module 22 further determines whether the memory 10 performs the error correction operation;

[0056] S124. When the error correction operation is performed in the memory 10, the retry module 22 sets the predetermined number of times to the rated number of times corresponding to the error correction operation.

[0057] In at least one embodiment of the present invention, the rated number of times can be set according to the number of detection parameters in the error correction table used in the error correction operation.

[0058] S13. After the retry operation, the first detection module 21 determines whether the memory 10 remains abnormal.

[0059] In at least one embodiment of the present invention, when the memory 10 performs the error correction operation and the read data is the ECC, the first detection module 21 identifies that the memory 10 is maintaining an abnormality and identifies that there is an uncorrectable error correcting code (UECC) in the memory 10.

[0060] S14. When the memory 10 remains abnormal, the restart module 23 controls the power supply 40 to stop outputting the power supply voltage to the memory 10.

[0061] S15. After a preset time, the restart module 23 controls the power supply 40 to output the power supply voltage to the memory 10.

[0062] In at least one embodiment of the present invention, the memory 10 performs a discharge operation within the preset time period, and the memory 10 completes the discharge operation within the preset time period. The preset time is related to the discharge resistance in the discharge circuit of the memory 10. The larger the resistance value of the discharge resistor in the memory 10, the longer the preset time. In at least one embodiment of the present invention, the preset time is 50 milliseconds.

[0063] The data protection method of the storage device 1 described above, by limiting the number of retries through the retry module 22, can prevent the controller 20 from repeatedly performing retry operations and improve the service life of the memory 10. Furthermore, by powering off and restarting the memory 10 when the memory 10 remains abnormal after the last retry operation, the abnormality of the memory 10 during the data reading process can be eliminated.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage device, comprising a memory, a controller, and a power supply; the controller comprising a first detection module, a retry module, and a restart module; characterized in that, The controller includes: The first detection module is used to determine whether the memory is abnormal; The retry module is used to perform a predetermined number of retry operations; the retry module is also used to determine whether the memory performs a specified operation; when the memory performs the specified operation, the retry module sets the predetermined number of retry operations to one; when the memory does not perform the specified operation, the retry module further determines whether the memory performs an error correction operation; when the memory performs the error correction operation, the retry module sets the predetermined number of retry operations to the rated number of retry operations corresponding to the error correction operation; wherein, the rated number of retry operations can be set according to the number of detection parameters in the error correction table used by the error correction operation; the specified operation can be a reset operation or a parameter setting operation; and The restart module is used to control the memory to power off and to control the memory to power on after a preset time; wherein the memory completes the discharge operation within the preset time.

2. The storage device as claimed in claim 1, characterized in that, When the memory is abnormal, the retry module performs the retry operation a predetermined number of times; after each retry operation, the first detection module detects whether the memory remains abnormal; if the memory remains abnormal after the last retry operation, the restart module controls the power supply to stop outputting the supply voltage to the memory to realize the power-off operation of the memory, and after the preset time, controls the power supply to output the supply voltage to the memory to realize the power-on operation of the memory.

3. The storage device as claimed in claim 1, characterized in that, The first detection module determines whether the memory is abnormal based on the status code provided by the memory when the memory performs a specified operation; the first detection module is used to determine whether the memory is abnormal by reading whether the data is an error code when the memory performs an error correction operation.

4. The storage device as claimed in claim 3, characterized in that, The first detection module further identifies uncorrectable error codes in the memory when the memory maintenance is abnormal.

5. A data recovery method for a storage device, the storage device comprising a memory, a controller, and a power supply; the controller comprising a first detection module, a retry module, and a restart module; characterized in that: The data recovery method includes: The first detection module determines whether the memory is abnormal; When the memory malfunctions, the retry module performs a predetermined number of retry operations; The first detection module determines whether the memory remains abnormal after the retry operation; When the memory sustains an abnormality, the restart module controls the power supply to stop outputting power to the memory; and The restart module controls the power supply to output the supply voltage to the memory after a preset time; wherein, the memory completes the discharge operation within the preset time.

6. The data recovery method as described in claim 5, characterized in that, The steps for the retry module to perform a predetermined number of retry operations include: The retry module determines whether the memory has performed a specified operation; When the memory performs the specified operation, the retry module is configured to perform a retry operation once; When the memory does not perform the specified operation, the retry module further determines whether the memory performs an error correction operation; and When the memory performs the error correction operation, the retry module sets the number of retry operations to the rated number corresponding to the error correction operation; wherein, the rated number can be set according to the number of detection parameters in the error correction table used by the error correction operation.

7. The data recovery method as described in claim 5, characterized in that, When the memory performs a specified operation, the first detection module determines whether the memory is abnormal based on the status code provided by the memory.

8. The data recovery method as described in claim 5, characterized in that, The first detection module is used to determine whether there is an error in the memory by reading whether the data is an error code when the memory performs an error correction operation.

9. The data recovery method as described in claim 8, characterized in that, The first detection module further identifies uncorrectable error codes in the memory when the memory maintenance is abnormal.

Images