Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate, the substrate having a plurality of mutually separated fins thereon, the fins comprising a buried region, a bottom region on the buried region, and a top region on the bottom region, the fins of the bottom region having a first width dimension, the fins of the top region having a second width dimension, the first width dimension being smaller than the second width dimension; and an isolation layer on the substrate, the isolation layer covering the buried region. When the first width dimension of the fins exposed by the bottom region is small, the control effect of a subsequently formed gate on the bottom region is enhanced, thereby reducing the problem of leakage current of the fins of the bottom region. In addition, the second width dimension of the fins exposed by the top region is large, so that the conduction path of the driving current is long, thereby improving the driving performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to shrink, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, resulting in a decrease in the gate's control over the channel, and making short-channel effects (SCE) more likely to occur.

[0003] FinFETs excel at suppressing short-channel effects. The gate of a FinFET can control the fins from at least both sides, thus giving it stronger gate control over the channel compared to planar MOSFETs, which effectively suppresses short-channel effects.

[0004] However, the performance of semiconductor structures in existing technologies still needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the final semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate having a plurality of mutually discrete fins, each fin including a buried region, a bottom region located on the buried region, and a top region located on the bottom region; lateral openings located on both sides of the bottom region, wherein the horizontal lateral depth of the lateral openings is less than half the thickness of the fin; the fins in the bottom region having a first width dimension, and the fins in the top region having a second width dimension, wherein the first width dimension is smaller than the second width dimension; and an isolation layer located on the substrate, the isolation layer covering the buried region, wherein the top surface of the isolation layer is flush with the bottom surface of the bottom region.

[0007] Optionally, the height of the bottom region is 50 angstroms to 200 angstroms.

[0008] Optionally, the first width dimension is 5 to 20 angstroms smaller than the second width dimension.

[0009] Optionally, the material of the isolation layer includes silicon oxide.

[0010] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate having a plurality of mutually discrete fins, each fin including a buried region, a bottom region located on the buried region, and a top region located on the bottom region, the bottom region having a first initial width dimension, the top region having a second initial width dimension, the first initial width dimension being greater than the second initial width dimension; forming an isolation layer on the substrate, the isolation layer covering the buried region, and the top surface of the isolation layer being flush with the bottom surface of the bottom region; and surface treatment of the bottom region and the top region. The surface is subjected to a first oxidation treatment to oxidize a portion of the bottom region and a portion of the top region to form an initial first oxide layer; the initial first oxide layer is etched back until the fin sidewall surface of the bottom region is exposed to form a first oxide layer; the exposed fin surface of the bottom region is subjected to a second oxidation treatment to oxidize a portion of the fin in the bottom region to form a second oxide layer, the unoxidized fin in the bottom region has a first width dimension, the unoxidized fin in the top region has a second width dimension, the first width dimension is smaller than the second width dimension; the first oxide layer and the second oxide layer are removed.

[0011] Optionally, after the first oxidation treatment, the method further includes: implanting a first ion into the initial first oxide layer, wherein the concentration of the first ion in the initial first oxide layer decreases from the top to the bottom of the fin.

[0012] Optionally, the etching rate of the initial first oxide layer during the back etching is inversely correlated with the concentration of the first ions within the initial first oxide layer.

[0013] Optionally, the first ion includes nitrogen ions; the concentration range of the first ion within the initial first oxide layer is 1E20 atoms / cm². 2 ~1E22atoms / cm 2 .

[0014] Optionally, the height of the bottom region is 50 angstroms to 200 angstroms.

[0015] Optionally, the first width dimension is smaller than the second width dimension: 5 angstroms to 20 angstroms.

[0016] Optionally, the etching process includes: wet etching process or dry etching process.

[0017] Optionally, the etching solution in the wet etching process includes: hydrofluoric acid solution.

[0018] Optionally, the etching gas in the dry etching process includes: fluorine-based etching gas.

[0019] Optionally, the process of the first oxidation treatment includes: a thermal oxidation process.

[0020] Optionally, the process parameters of the thermal oxidation process include: oxidizing gases including oxygen and nitrogen oxides; oxidation temperature: 700 degrees Celsius to 1100 degrees Celsius; oxidation time: 10 seconds to 180 seconds.

[0021] Optionally, the second oxidation treatment process includes a chemical solution oxidation process.

[0022] Optionally, the process parameters of the chemical solution oxidation process include: the oxidation solution includes hydrogen peroxide, sulfuric acid and ozone; the oxidation temperature is 20 degrees Celsius to 100 degrees Celsius; and the oxidation time is 30 seconds to 180 seconds.

[0023] Optionally, the process for removing the first oxide layer and the second oxide layer includes: a wet etching process or a dry etching process.

[0024] Optionally, the method for forming the isolation layer includes: forming an isolation material layer on the substrate, the isolation material layer covering the fin; planarizing the isolation material layer until the top surface of the fin is exposed to form an initial isolation layer; and etching back the initial isolation layer to form the isolation layer.

[0025] Optionally, the material of the isolation layer includes silicon oxide.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] The structure of the present invention includes: a substrate having a plurality of mutually discrete fins, each fin including a buried region, a bottom region located on the buried region, and a top region located on the bottom region. The unoxidized fins in the bottom region have a first width dimension, and the unoxidized fins in the top region have a second width dimension, wherein the first width dimension is smaller than the second width dimension. When the first width dimension of the unoxidized fins in the bottom region is smaller, the control effect of the subsequently formed gate on the bottom region is enhanced, thereby reducing the leakage current problem in the bottom region fins. Furthermore, the second width dimension of the unoxidized fins in the top region is larger, resulting in a longer conduction path for the driving current, thereby improving the driving performance of the final semiconductor structure.

[0028] In the method for forming the technical solution of the present invention, a second oxidation treatment is performed on the surface of the fins exposed in the bottom region, so that the exposed portion of the fins in the bottom region is oxidized to form a second oxide layer; the unoxidized fins in the bottom region have a first width dimension, and the unoxidized fins in the top region have a second width dimension, wherein the first width dimension is smaller than the second width dimension. When the first width dimension of the unoxidized fins in the bottom region is smaller, the control effect of the subsequently formed gate on the bottom region can be enhanced, thereby reducing the leakage current problem of the fins in the bottom region. In addition, the second width dimension of the unoxidized fins in the top region is larger, resulting in a longer conduction path for the driving current, thereby improving the driving performance of the finally formed semiconductor structure.

[0029] Furthermore, after the first oxidation treatment, the method further includes: implanting first ions into the initial first oxide layer, wherein the concentration of first ions in the initial first oxide layer decreases from the top to the bottom of the fin; the etching rate of the etchback process on the initial first oxide layer is inversely correlated with the concentration of first ions in the initial first oxide layer. By implanting first ions into the initial first oxide layer, the reliability of the final semiconductor structure can be improved. Simultaneously, by utilizing the decreasing concentration of first ions in the initial first oxide layer and the inverse correlation between the etching rate of the etchback process on the initial first oxide layer and the concentration of first ions in the initial first oxide layer, it can be ensured that the initial first oxide layer on the bottom region surface is completely removed first, while the initial first oxide layer on the top region surface remains. Attached Figure Description

[0030] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0031] Figures 3 to 14 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0032] As described in the background section, the performance of existing semiconductor structures still needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0033] Please refer to Figure 1A substrate 100 is provided, the substrate 100 having a plurality of mutually discrete fins 101, each fin 101 including a buried region I, a bottom region II located on the buried region I, and a top region III located on the bottom region II. Along a direction perpendicular to the extension of the fin 100, the bottom region II has a first width dimension d1, and the top region III has a second width dimension d2, the first width dimension d1 being greater than the second width dimension d2. An isolation layer 102 is formed on the substrate 100, the isolation layer 102 covering the buried region I, and the top surface of the isolation layer 102 being lower than the top surface of the fins 101. The surfaces of the bottom region II and the top region III are oxidized so that a portion of the bottom region II and a portion of the top region III are oxidized to form an oxide layer 103.

[0034] Please refer to Figure 2 Remove the oxide layer 103 until the surfaces of the fins 101 in the bottom region II and the fins 101 in the top region III are exposed.

[0035] In this embodiment, since the oxide layer 103 formed by oxidizing the surfaces of the bottom region II and the top region III has a uniform thickness, after removing the oxide layer 103, the width of the fin 101 exposed in the bottom region II is still greater than the width of the fin 101 exposed in the top region III in the direction perpendicular to the fin extension. Furthermore, during the removal of the oxide layer 103, a certain thickness of the isolation layer 102 is also etched away, exposing part of the buried region I. The difference between the width of the exposed buried region I and the width of the fin 101 exposed in the top region III is even greater.

[0036] Because the width of the fin 101 exposed in the bottom region II and the width of the buried region I are relatively large, the control effect of the subsequently formed gate on the bottom region II is weak, making the bottom region II prone to leakage current. In addition, the width of the fin 101 exposed in the top region III is relatively small, resulting in a shorter conduction path for the drive current and poor driving performance of the semiconductor structure.

[0037] Based on this, the present invention provides a semiconductor structure and its formation method. The unoxidized bottom region of the fin has a first width dimension, and the unoxidized top region of the fin has a second width dimension, where the first width dimension is smaller than the second width dimension. When the first width dimension of the unoxidized bottom region of the fin is smaller, the control effect of the subsequently formed gate on the bottom region is enhanced, thereby reducing leakage current in the bottom region of the fin. Furthermore, the larger second width dimension of the unoxidized top region of the fin results in a longer conduction path for the driving current, thereby improving the driving performance of the final semiconductor structure.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 3 to 10 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figures 3 to 5 , Figure 3 It is a 3D diagram of a semiconductor structure. Figure 4 yes Figure 3 Schematic diagram of the cross section along line AA in the middle. Figure 5 yes Figure 4 The enlarged schematic diagram of part A shows a substrate 200 with a plurality of mutually independent fins 201. Each fin 201 includes a buried region I, a bottom region II located on the buried region I, and a top region III located on the bottom region II. The bottom region II has a first initial width dimension d1, and the top region III has a second initial width dimension d2. The first initial width dimension d1 is greater than the second initial width dimension d2.

[0041] In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200; and removing the patterned layer after forming the substrate 200.

[0042] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0043] In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0044] In this embodiment, the reason why the first initial width dimension is greater than d1 and the second initial width dimension d2 is that during the etching process of the initial substrate, as the etching depth increases, the lateral etching amount will gradually decrease, thereby reducing the amount of etching of the bottom region II. Therefore, the fin 201 formed in the end presents a trapezoidal structure.

[0045] In this embodiment, the height of the bottom region II is 50 angstroms to 200 angstroms.

[0046] Please refer to Figure 6 , Figure 6 and Figure 4 With the views aligned, an isolation layer 202 is formed on the substrate 200, the isolation layer 202 covering the buried area I, and the top surface of the isolation layer 202 being flush with the bottom surface of the bottom area II.

[0047] In this embodiment, the method for forming the isolation layer 202 includes: forming an isolation material layer (not shown) on the substrate 200, the isolation material layer covering the fin 201; planarizing the isolation material layer until the top surface of the fin 201 is exposed to form an initial isolation layer (not shown); and etching back the initial isolation layer to form the isolation layer 202.

[0048] In this embodiment, the planarization of the isolation material layer is performed using a chemical mechanical polishing process. In other embodiments, the planarization of the isolation material layer can also be performed using a wet etching process or a dry etching process.

[0049] The insulating layer 202 is made of an insulating material, including silicon oxide, silicon nitride, or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0050] Please refer to Figure 7 After the isolation layer 202 is formed, the surfaces of the bottom region II and the top region III are subjected to a first oxidation treatment so that a portion of the bottom region II and a portion of the top region III are oxidized to form an initial first oxide layer 203.

[0051] In this embodiment, the surfaces of the bottom region II and the top region III are subjected to a first oxidation treatment to form the initial first oxide layer 203. The initial first oxide layer 203 can smooth the sharp corners of the fin 201 and the substrate 200 surface, and acts as a buffer layer between the subsequently formed film layer and the substrate 200 and the fin 201 to reduce lattice mismatch. On the other hand, the initial first oxide layer 203 provides a basis for the subsequent reduction of the size of the bottom region II.

[0052] In this embodiment, the first oxidation treatment is carried out using a thermal oxidation process; the process parameters of the thermal oxidation process include: the oxidizing gas includes oxygen and nitrogen oxides; the oxidation temperature is 700 degrees Celsius to 1100 degrees Celsius; and the oxidation time is 10 seconds to 180 seconds.

[0053] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8 The enlarged schematic diagram of part B shows that after the first oxidation treatment, the initial first oxide layer 203 is implanted with first ions, and the concentration of first ions in the initial first oxide layer 203 decreases from the top to the bottom of the fin 201.

[0054] In this embodiment, by performing a first ion implantation process on the initial first oxide layer 203, the defects on the surface of the fin 201 can be further repaired, thereby improving the reliability of the finally formed semiconductor structure.

[0055] In this embodiment, the first ion is a nitrogen ion; the concentration range of the first ion within the initial first oxide layer 203 is 1E20 atoms / cm³. 2 ~1E22 atoms / cm 2 .

[0056] In this embodiment, as the implantation depth of the first ion increases, the implantation amount of the first ion gradually decreases, thereby causing the concentration of the first ion in the initial first oxide layer 203 to decrease from the top to the bottom of the fin 201.

[0057] Please refer to Figure 10 and Figure 11 , Figure 11 yes Figure 10 The enlarged schematic diagram of part C shows the initial first oxide layer 203 being etched back until the sidewall surface of the fin portion 201 in the bottom region II is exposed, forming the first oxide layer 204.

[0058] In this embodiment, the back etching process adopts a wet etching process, and the etching solution of the wet etching process includes a hydrofluoric acid solution.

[0059] In other embodiments, the etching process can also employ a dry etching process, wherein the etching gas in the dry etching process includes a fluorine-based etching gas.

[0060] In this embodiment, the etching rate of the initial first oxide layer 203 by the back etching is inversely correlated with the concentration of the first ion within the initial first oxide layer 203.

[0061] In this embodiment, by utilizing the characteristic that the concentration of the first ion in the initial first oxide layer 203 decreases from the top to the bottom of the fin 201, that is, the concentration of the first ion in the initial first oxide layer 203 on the surface of the top region III is greater than the concentration of the first ion in the initial first oxide layer 203 on the surface of the bottom region II, and that the etching rate of the back etching on the initial first oxide layer 203 is inversely correlated with the concentration of the first ion in the initial first oxide layer 203, it can be ensured that the initial first oxide layer 203 on the surface of the bottom region II is completely removed first, while the initial first oxide layer 203 on the surface of the top region III is still retained.

[0062] Please refer to Figure 12 and Figure 13 , Figure 13 yes Figure 12 The enlarged schematic diagram of part D shows that the surface of the fin 201 exposed in the bottom region II is subjected to a second oxidation treatment, so that the exposed part of the fin 201 in the bottom region II is oxidized to form a second oxide layer 205. The unoxidized fin 201 in the bottom region II has a first width dimension D1, and the unoxidized fin 201 in the top region III has a second width dimension D2. The first width dimension D1 is smaller than the second width dimension D2.

[0063] In this embodiment, a second oxidation treatment is performed on the surface of the fins 201 exposed in the bottom region II, so that the exposed portion of the fins 201 in the bottom region II is oxidized to form a second oxide layer 205. Along the extension direction perpendicular to the fins 201, the unoxidized fins 201 in the bottom region II have a first width dimension D1, and the unoxidized fins 201 in the top region III have a second width dimension D2, wherein the first width dimension D1 is smaller than the second width dimension D2. When the first width dimension D1 of the unoxidized fins 201 in the bottom region II is smaller, the control effect of the subsequently formed gate on the bottom region II is enhanced, thereby reducing the leakage current problem of the fins 201 in the bottom region II. In addition, the second width dimension D2 of the unoxidized fins 201 in the top region III is larger, resulting in a longer conduction path for the driving current, thereby improving the driving performance of the finally formed semiconductor structure.

[0064] In this embodiment, the second oxidation treatment adopts a chemical solution oxidation process; the process parameters of the chemical solution oxidation process include: the oxidation solution includes: hydrogen peroxide, sulfuric acid and ozone; oxidation temperature: 20 degrees Celsius to 100 degrees Celsius; oxidation time: 30 seconds to 180 seconds.

[0065] In this embodiment, since the chemical solution oxidation process uses an oxidizing solution to oxidize the bottom region, during the oxidation process, the oxidizing solution will accumulate in the bottom region II of the fin 201, thereby oxidizing the fin 201 exposed in the bottom region II, without affecting the top region III.

[0066] In this embodiment, the first width dimension D1 is smaller than the second width dimension D2 by 5 angstroms to 20 angstroms.

[0067] Please refer to Figure 14 Remove the first oxide layer 204 and the second oxide layer 205.

[0068] The process for removing the first oxide layer 204 and the second oxide layer 205 includes either a wet etching process or a dry etching process. In this embodiment, the process for removing the first oxide layer 204 and the second oxide layer 205 is a wet etching process.

[0069] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 14 The device includes: a substrate 200 having a plurality of mutually discrete fins 201, each fin 201 including a buried region I, a bottom region II located on the buried region I, and a top region III located on the bottom region II; lateral openings 206 located on both sides of the bottom region II, wherein the horizontal lateral depth of the lateral openings 206 is less than half the thickness of the fins 201; the fins 201 of the bottom region II having a first width dimension D1, and the fins 201 of the top region III having a second width dimension D2, wherein the first width dimension D1 is smaller than the second width dimension D2; and an isolation layer 202 located on the substrate 200, the isolation layer 202 covering the buried region I, wherein the top surface of the isolation layer 202 is flush with the bottom surface of the bottom region II.

[0070] In this embodiment, when the first width dimension D1 of the unoxidized fin 201 in the bottom region II is small, the control effect of the subsequently formed gate on the bottom region II is enhanced, thereby reducing the leakage current problem of the fin 201 in the bottom region II. Furthermore, the second width dimension D2 of the unoxidized fin 201 in the top region III is large, resulting in a longer conduction path for the driving current, thereby improving the driving performance of the final semiconductor structure.

[0071] In this embodiment, the height of the bottom region II is 50 angstroms to 200 angstroms.

[0072] In this embodiment, the first width dimension D1 is smaller than the second width dimension D2 by 5 angstroms to 20 angstroms.

[0073] In this embodiment, the material of the isolation layer 202 includes silicon oxide.

[0074] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a plurality of mutually discrete fins, each fin including a buried region, a bottom region located on the buried region, and a top region located on the bottom region, the bottom region having a first initial width dimension, the top region having a second initial width dimension, the first initial width dimension being greater than the second initial width dimension; An isolation layer is formed on the substrate, the isolation layer covering the buried area, and the top surface of the isolation layer is flush with the bottom surface of the bottom area; The surfaces of the bottom region and the top region are subjected to a first oxidation treatment, such that a portion of the bottom region and a portion of the top region are oxidized to form an initial first oxide layer; The initial first oxide layer is etched back until the fin sidewall surface of the bottom region is exposed, forming the first oxide layer; The exposed fin surface in the bottom region is subjected to a second oxidation treatment, so that the exposed portion of the fin in the bottom region is oxidized to form a second oxide layer. The unoxidized fin in the bottom region has a first width dimension, and the unoxidized fin in the top region has a second width dimension. The first width dimension is smaller than the second width dimension. Remove the first oxide layer and the second oxide layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the first oxidation treatment, the method further includes: implanting a first ion into the initial first oxide layer, wherein the concentration of the first ion in the initial first oxide layer decreases from the top to the bottom of the fin.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The etching rate of the initial first oxide layer during the re-etching process is inversely correlated with the concentration of the first ion within the initial first oxide layer.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first ion includes nitrogen ions; the concentration range of the first ion within the initial first oxide layer is 1E20 atoms / cm². 2 ~1E22atoms / cm 2 .

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The height of the bottom region is 50 angstroms to 200 angstroms.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first width dimension is smaller than the second width dimension: 5 angstroms to 20 angstroms.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process includes either wet etching or dry etching.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The etching solution used in the wet etching process includes hydrofluoric acid solution.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The etching gas used in the dry etching process includes fluorine-based etching gas.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first oxidation treatment process includes: thermal oxidation process.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process parameters of the thermal oxidation process include: oxidation gases including oxygen and nitrogen oxides; oxidation temperature: 700 degrees Celsius to 1100 degrees Celsius; oxidation time: 10 seconds to 180 seconds.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second oxidation treatment process includes: a chemical solution oxidation process.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process parameters of the chemical solution oxidation process include: the oxidation solution includes hydrogen peroxide, sulfuric acid and ozone; the oxidation temperature is 20 degrees Celsius to 100 degrees Celsius; and the oxidation time is 30 seconds to 180 seconds.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the first oxide layer and the second oxide layer includes: wet etching process or dry etching process.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the isolation layer includes: forming an isolation material layer on the substrate, the isolation material layer covering the fin; planarizing the isolation material layer until the top surface of the fin is exposed to form an initial isolation layer; and etching back the initial isolation layer to form the isolation layer.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the isolation layer includes silicon oxide.

17. A semiconductor structure formed using the method according to any one of claims 1 to 16, characterized in that, include: A substrate having a plurality of mutually independent fins, the fins including a buried region, a bottom region located on the buried region, and a top region located on the bottom region; Lateral openings located on both sides of the bottom region, wherein the horizontal lateral depth of the lateral openings is less than half the thickness of the fin; The fin in the bottom region has a first width dimension, and the fin in the top region has a second width dimension, wherein the first width dimension is smaller than the second width dimension; An isolation layer is located on the substrate, the isolation layer covers the buried area, and the top surface of the isolation layer is flush with the bottom surface of the bottom area.

18. The semiconductor structure as claimed in claim 17, characterized in that, The height of the bottom region is 50 angstroms to 200 angstroms.

19. The semiconductor structure as claimed in claim 17, characterized in that, The first width dimension is smaller than the second width dimension: 5 angstroms to 20 angstroms.

20. The semiconductor structure as claimed in claim 17, characterized in that, The material of the isolation layer includes silicon oxide.

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