Vertical cavity surface emitting semiconductor laser diode

Abstract

A vertical cavity surface emitting laser diode includes a substrate and an epitaxial stack on the substrate, the epitaxial stack including an active region, a current confinement layer, and a mode filter layer, wherein the mode filter layer has an optical aperture, the mode filter layer is oxidizable, and the mode filter layer is oxidized to form the optical aperture.

Description

Technical Field

[0001] A vertical cavity surface-emitting semiconductor laser diode (VCSEL), particularly a semiconductor laser diode having a mode filter layer, wherein the mode filter layer can be oxidized, and the optical aperture of the mode filter layer is formed by oxidizing the mode filter layer. Background Technology

[0002] Figure 1 It is a semiconductor laser diode with a small divergence angle, which is a technology currently in use. For example... Figure 1 As shown, the surface relief layer 240 with opening 241 is the uppermost layer of the semiconductor laser diode, and an oxide layer 230 with vias 231 is formed between the surface relief layer 240 and the active region 220. However, because the opening 241 of the surface relief layer 240 is formed by photolithography and etching, while the via 231 of the oxide layer 230 is formed by oxidation, the central axes of the opening 241 and the via 231 are not easily aligned precisely due to the different fabrication methods, thus increasing the divergence angle of the semiconductor laser diode. Furthermore, during mass production of semiconductor laser diodes, the degree of deviation between the central axes of the vias and openings of multiple semiconductor laser diodes is also different, resulting in inconsistent and larger divergence angles among the multiple semiconductor laser diodes.

[0003] Please refer to US Patent Publication No. 2021005788 A1. According to this patent, multiple oxide layers with different via sizes are formed between the upper DBR layer and the active region, and the divergence angle is reduced by using vias of different sizes. Although the multiple oxide layers can be synchronously oxidized to make their centers more accurately aligned, it is well known that the conductivity of the oxidized part of each oxide layer is very low (i.e., high resistance). Moreover, multiple oxide layers with high resistance are placed in the path through which most currents will inevitably flow. Therefore, the considerable resistance value accumulated by these oxide layers not only seriously affects the power conversion efficiency of the vertical cavity surface-emitting semiconductor laser diode (VCSEL), but also prolongs the pulse rise time. Therefore, VCSELs made according to this patent are not easy to generate short pulses. Summary of the Invention

[0004] In the field of VCSEL technology, current-limiting layers are typically placed near or within the active region to concentrate current flowing into a specific area, such as the center, of the active region. However, the resistance of a single current-limiting layer is quite high, so the number of current-limiting layers should not be too large. In existing VCSELs with small divergence angles, the surface relief layer is usually placed on the top layer of the VCSEL, which presents a limitation on its placement.

[0005] This paper provides a VCSEL with a small divergence angle, comprising a modal filter layer with an optical aperture. The modal filter layer is laterally oxidized, and the optical aperture of the modal filter layer is formed through an oxidation process. Therefore, the modal filter layer can be oxidized together with the current-limiting layer, so that the central axis of the current-limiting via and the central axis of the optical aperture can be aligned. As a result, not only is the divergence angle of the VCSEL reduced, but the divergence angles of multiple semiconductor laser diodes become more consistent. Furthermore, when the modal filter layer and the current-limiting layer are oxidized simultaneously, the VCSEL fabrication process is simplified and the VCSEL manufacturing yield is improved. In addition, this paper further presents some representative embodiments for reducing the influence of the modal filter layer resistance. Attached Figure Description

[0006] Figure 1 It is a semiconductor laser diode with a small divergence angle, which is a technology currently in use.

[0007] Figure 2 This is a schematic diagram of a VCSEL epitaxial chip structure according to an embodiment of this article.

[0008] Figure 3 This is a schematic diagram of a VCSEL epitaxial chip structure with a spacer layer according to an embodiment of this paper.

[0009] Figure 4a This is a schematic diagram of a VCSEL epitaxial chip structure according to an embodiment of this paper, in which a first ohmic contact layer is directly in contact with a modal filter layer.

[0010] Figure 4b It is Figure 4a A schematic diagram of a possible VCSEL semi-finished component fabricated from the VCSEL epitaxial chip structure.

[0011] Figure 4c This is a schematic diagram showing the first metal electrode of one embodiment of the present invention flush with the top surface of the VCSEL semi-finished component.

[0012] Figure 5a This is a schematic diagram of a VCSEL epitaxial chip structure in one embodiment of this paper, where the first ohmic contact layer is indirectly in contact with the modal filtering layer.

[0013] Figure 5b It is Figure 5a A schematic diagram of a possible VCSEL semi-finished component fabricated from the VCSEL epitaxial chip structure.

[0014] Figure 6a This is a schematic diagram of a VCSEL epitaxial chip structure in one embodiment of this paper, in which the first ohmic contact layer is indirectly disposed on the modal filter layer.

[0015] Figure 6b It is Figure 6aA schematic diagram illustrating the fabrication of a possible VCSEL semi-finished component using the VCSEL epitaxial chip structure. Figure 6b The first metal electrode is formed by an alloying process.

[0016] Figure 7a This is a schematic diagram of a VCSEL epitaxial chip structure in one embodiment of this paper, in which the modal filtering layer is located between two ohmic contact layers.

[0017] Figure 7b It is Figure 7a A schematic diagram of a possible VCSEL semi-finished component fabricated from the VCSEL epitaxial chip structure.

[0018] Figure 7c This is a schematic diagram of a first metal electrode (non-alloy electrode) formed by a non-alloy process to electrically connect the first ohmic contact layer and the second ohmic contact layer.

[0019] Figure 8 This is a schematic diagram of a front-emitting VCSEL epitaxial chip structure comprising multiple modal filter layers and multiple semiconductor layers, according to an embodiment of this paper.

[0020] Figure 9 This is a schematic diagram of a back-emitting VCSEL epitaxial chip structure comprising multiple modal filter layers and multiple semiconductor layers, according to an embodiment of this paper.

[0021] Figure 10a This is a schematic diagram of a VCSEL epitaxial chip structure in one embodiment of this paper, in which the modal filtering layer is set in the upper DBR layer.

[0022] Figure 10b It is Figure 10a A schematic diagram of a possible VCSEL semi-finished component fabricated from the VCSEL epitaxial chip structure.

[0023] Figure 11 This is a schematic diagram of a VCSEL semi-finished component according to one embodiment of this article.

[0024] Figure 12 This is a graph showing the LI characteristics of a VCSEL with a modal filtering layer and a VCSEL with a surface embossing layer.

[0025] Figure 13 This is a schematic diagram of a VCSEL epitaxial chip structure with a surface relief layer disposed on an ohmic contact layer (existing technology).

[0026] Figure 14 Display respectively Figure 7b VCSEL and Figure 13 A schematic diagram of the far-field profile of a VCSEL.

[0027] Explanation of main component symbols

[0028] 200 VCSEL epitaxial chip structure

[0029] 210 substrate

[0030] 220 Active Zone

[0031] 230 Oxide Layer

[0032] 231 Through Hole

[0033] 240 Surface Embossed Layer

[0034] 241 opening

[0035] 250 Metal Electrode

[0036] 1, 2, 3, 4, 5, 6, 7, 8, 9, 91 VCSEL epitaxial chip structure

[0037] 3', 3”, 4', 5', 6', 6”, 9' VCSEL semi-finished components

[0038] 10 substrate

[0039] 12 Buffer Layers

[0040] 14 Lower DBR layer

[0041] 16 Lower Spacing Layer

[0042] 30 Active Zone

[0043] 32 Upper spacer layer

[0044] 50 Current confinement layer

[0045] 60 Upper DBR layer

[0046] 70 spacer layers

[0047] 100, 101 epitaxial stacked structure

[0048] 110 First Ohmic Contact Layer

[0049] 111 Second Ohmic Contact Layer

[0050] 120 and 121 modal filtering layers

[0051] 130 First Semiconductor Layer

[0052] 131 Second Semiconductor Layer

[0053] 50A Current-Confined Through Hole

[0054] 120a optical aperture

[0055] E1 First Metal Electrode

[0056] E2 Second metal electrode. Detailed Implementation

[0057] The following description, in conjunction with illustrations and component symbols, provides a more detailed account of the embodiments of the present invention, enabling those skilled in the art to implement them after studying this specification.

[0058] The following description provides examples of specific elements and their arrangements to simplify the invention. These are merely examples and should not be construed as limiting the scope of the invention. For instance, when the description refers to one layer on top of another, it may include embodiments where the layer is in direct contact with the other layer, or embodiments where other elements or epitaxial layers are formed between them without direct contact. Furthermore, repeated reference numerals and / or symbols may be used in different embodiments; these repetitions are merely for the purpose of clearly describing some embodiments and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0059] In addition, spatial terms may be used, such as “below,” “lower,” “above,” “higher,” and similar terms, which are used to facilitate the description of the relationship between one element(s) or feature(s) in the figures and another element(s). These spatial terms include different orientations of the device in use or operation, as well as the orientations described in the figures.

[0060] This specification provides different embodiments to illustrate the technical features of different implementations. For example, the phrase "some embodiments" throughout the specification means that a particular feature, structure, or characteristic described in an embodiment is included in at least one embodiment. Therefore, the phrase "in some embodiments" appearing in different places throughout the specification does not necessarily refer to the same embodiment.

[0061] Furthermore, specific features, structures, or characteristics may be combined in one or more embodiments by any suitable method. Further, the terms “comprising,” “having,” “having,” “wherein,” or variations thereof, as used herein, are semantically similar to the term “comprising” to encompass the corresponding features.

[0062] Furthermore, a “layer” can be a single layer or contain multiple layers; and a “part” of an epitaxial layer may be one layer of that epitaxial layer or multiple adjacent layers.

[0063] In existing technologies, the buffer layer can be selectively set in the laser diode according to actual needs.

[0064] Furthermore, in some instances, the buffer layer may be made of the same material as the substrate. Whether or not a buffer layer is provided is not substantially related to the technical features or desired effects described in the following embodiments. Therefore, for the sake of brevity, the following embodiments only use a laser diode with a buffer layer as an example for illustration, without further detailing a laser diode without a buffer layer. In other words, the following embodiments, such as replacing a laser diode without a buffer layer, can also be applied.

[0065] like Figure 2 As shown, an epitaxial stacked structure 100 is epitaxially grown on the substrate 10. The epitaxial stacked structure 100 includes an active region 30 and a current confinement layer 50; although Figure 2 Other accompanying drawings may also depict epitaxial layers such as buffer layer 12, lower spacer layer 14, and upper spacer layer 32, but these epitaxial layers may be added or removed according to actual needs.

[0066] A mode filter layer 120 and a first semiconductor layer 130 are sequentially formed on the epitaxial stack structure 100. The first semiconductor layer 130 covers the mode filter layer 120 to prevent the mode filter layer 120 from oxidizing due to exposure. Figure 2 compared to, Figure 3 The VCSEL epitaxial chip structure 2 further includes a spacer layer 70, which is disposed between the upper DBR layer 60 and the modal filter layer 120. In some embodiments, the spacer layer 70 may also be disposed above the upper DBR layer 60, below the modal filter layer 20, or at other suitable locations. Furthermore, the spacer layer 70 can also be used as an ohmic contact layer. In one or more embodiments, the active region 30 includes one or more active layers (not shown). For example, when the active region includes two active layers, a tunneling interface layer must be provided between the two active layers to connect them in series. One active layer includes one or more quantum well structures. Figure 2 compared to, Figure 4a The VCSEL epitaxial chip structure 3 further includes a first ohmic contact layer 110, which is positioned between the upper DBR layer 60 and the mode filter layer 120. Regarding the current limiting layers 50, their location and number are not specified. Figure 4a For certain limitations, the current limiting layer can also be located within, above, and / or below the active region. For example, the current limiting layer can be located between the lower DBR layer and the upper DBR layer, within the upper DBR layer, or within the lower DBR layer. When both the current limiting layer and the modal filter layer are located within the upper DBR layer, the current limiting layer should be closer to the active region than the modal filter layer.

[0067] Figure 4a The VCSEL epitaxial chip structure 3 can be fabricated into various VCSEL semi-finished components, one of which is... Figure 4bThe VCSEL semi-finished component 3'. According to... Figure 4b The main current flow path is through the first metal electrode E1, the first ohmic contact layer 110, the upper DBR layer 60, and the current-limiting via 50a, before entering the active region 30; wherein, the first metal electrode E1 is in ohmic contact with the first ohmic contact layer 110. Although the resistance of the modal filter layer is high, the optical aperture 120a of the modal filter layer is not in the main current flow path, so it has little or no impact on the characteristics of the VCSEL. The arrangement and height of the first metal electrode E1 are not related to... Figure 4b For the limited purposes, it can also be as follows: Figure 4c This ensures that the top surface of the first metal electrode E1 is flush with the top surface of the VCSEL semi-finished component 3'. Figure 4a compared to, Figure 5a A second semiconductor layer 131 is disposed between the modal filter layer 120 and the first ohmic contact layer 110. The second semiconductor layer 131 is selectively disposed according to the epitaxial structure design. Figure 5b In this case, the optical aperture of 120a is not on the main current flow path. The placement of the first metal electrode E1 is not based on... Figure 5b Limited to.

[0068] Figure 6a A second semiconductor layer 131, a modal filter layer 120, a first semiconductor layer 130, and a first ohmic contact layer 110 are sequentially formed on the epitaxial stacked structure 100. The first metal electrode E1 can be formed by a non-alloy process, an alloy process, or other suitable methods. Figure 4b , 4c 5b Figure 7c or Figure 10b Some embodiments of forming the first metal electrode E1 using a non-alloy process involve removing a portion of the oxidized portion of the modal filter layer 120 to expose a portion of the surface of the first ohmic contact layer 110, and then depositing the first metal electrode on the exposed surface of the first ohmic contact layer. Figure 6b It is formed by an alloying process to create a first metal electrode (alloy electrode) that passes through one or more layers. Figure 7aA second semiconductor layer 131, a first ohmic contact layer 110, a mode filter layer 120, a first semiconductor layer 130, and a second ohmic contact layer 111 are sequentially formed on the epitaxial stacked structure 100. Preferably, the first ohmic contact layer, the semiconductor layer adjacent to the first ohmic contact layer, the second ohmic contact layer, the semiconductor layer adjacent to the second ohmic contact layer, or both of the above are further doped with appropriate elements. For example, all of the "second semiconductor layer 131, first ohmic contact layer 110, mode filter layer 120, first semiconductor layer 130, and second ohmic contact layer 111" are doped with p-type or n-type doping elements. For example, the n-type first (second) ohmic contact layer, first semiconductor layer 130, or second semiconductor layer 131 may be further doped with Si, Se, Sn (tin), Ge, or Te. The p-type first (second) ohmic contact layer, first semiconductor layer 130, or second semiconductor layer 131 may be further doped with Zn, C, or Be. The first metal electrode and / or the second metal electrode (ohmic contact metal) can be n-type or p-type. The materials of the n-type first metal electrode and / or the second metal electrode include Ge, Ge / Ni, Sn alloys, gold-germanium alloys, gold-germanium-nickel alloys, etc. The materials of the p-type first metal electrode and / or the second metal electrode include Zn, Mg, and Be alloys. In one or more embodiments, the first semiconductor layer, the second semiconductor layer, or both are selectively provided according to different practical needs.

[0069] Figure 7a The VCSEL epitaxial chip structure 6 can be fabricated into various VCSEL semi-finished components, one of which is... Figure 7b The VCSEL semi-finished component 6'. According to... Figure 7b The main path of current flow is through the first metal electrode E1, the second semiconductor layer 131, the upper DBR layer 60 and the current limiting via 50a, and then enters the active region 30'.

[0070] Figure 8 It displays a front-emitting VCSEL epitaxial chip structure. Figure 9 This displays a back-emitting VCSEL epitaxial chip structure. Figure 8 and Figure 9 Each includes two-mode filter layers 120 and 121, a first semiconductor layer 130, and a second semiconductor layer 131. Figure 9 The location and number of current-limiting layers or modal filter layers are not based on Figure 9For example, the current limiting layer can be disposed above the lower DBR layer 14 and below the upper DBR layer. The mode filter layer can be disposed below the lower DBR layer and above the substrate. As can be seen from the above, the back-emitting VCSEL epitaxial chip structure also has a mode filter layer and a current limiting layer, so the mode filter layer and the current limiting layer can of course be oxidized simultaneously or sequentially. In the case of the back-emitting VCSEL epitaxial chip structure, if both the current limiting layer and the mode filter layer are located in the lower DBR layer, the current limiting layer should be closer to the active region than the mode filter layer. In one embodiment, the substrate of the back-emitting VCSEL epitaxial chip structure can be removed, so the first metal electrode can be formed by a non-alloy process or an alloy process. For specific implementations of the non-alloy process, please refer to the following in this document. Figure 4b For related explanations and specific implementation methods of the alloying process, please refer to the preceding description. Although this article only contains... Figure 9 This illustration shows an embodiment where the modal filter layer is disposed on the back-emitting VCSEL epitaxial wafer structure 8. However, there are other representative embodiments of the modal filter layer, and these representative embodiments can be referred to the embodiments in the context (front-emitting VCSEL epitaxial wafer structure), which will not be repeated here. Figure 10a As shown, the upper DBR layer 60 of the epitaxial stacked structure 101 further includes a first ohmic contact layer 110, a mode filter layer 120, and a first semiconductor layer 130. Preferably, when the upper DBR layer 60 on the mode filter layer 120 is undoped, the light absorption rate of the upper DBR layer 60 can be reduced. In one embodiment, the first ohmic contact layer is also disposed within the upper DBR layer, while the mode filter layer can be disposed on top of the upper DBR layer. The conductive means of the first ohmic contact layer and the first metal electrode can be referred to the embodiments described above, and will not be repeated here.

[0071] Figure 10a The VCSEL epitaxial chip structure 9 can be fabricated into various VCSEL semi-finished components, one of which is... Figure 10b The VCSEL semi-finished component 9'. According to... Figure 10b The main path of current flow is through the first metal electrode E1, the first ohmic contact layer 110 and the current limiting via 50a, and then into the active region 30.

[0072] In any embodiment of this document, the current limiting layer 50 and the modal filter layer 120 can be oxidized sequentially or together. After the oxidation process is completed, the current limiting via 120a and the optical aperture 120a are formed. Figure 11 The epitaxial wafer structure is similar to Figure 6b ,but Figure 11 The epitaxial wafer structure does not have a set Figure 6bThe second semiconductor layer 131. The modal filtering layer is not limited to being disposed between the upper DBR layer and the first semiconductor layer 130. Depending on different requirements, the modal filtering layer can also be disposed within the upper DBR layer. As mentioned above, Figure 11 The first semiconductor layer can also be set or adjusted depending on different needs.

[0073] In one embodiment, the unoxidized portion of the modal filter layer is a constructive interference region, while the oxidized portion is a destructive interference region. There is an optical path difference between the constructive and destructive interference regions, which is (2n+1)λ / 4, where n is a positive integer such as 0, 1, 2, or 3, and λ is the emission wavelength of the semiconductor laser element. Under the condition of satisfying the above optical path difference, the modal filter layer does not need to be disposed above the first ohmic contact layer or the outermost layer of the semiconductor laser element, and the semiconductor laser element can still emit laser light with a small divergence angle. Depending on actual needs, the epitaxial structure can be further adjusted, such as "adjusting the composition (refractive index) or thickness of the modal filter layer itself," "adjusting the composition (refractive index) or thickness of one or more layers above the modal filter layer," "adjusting the composition (refractive index) or thickness of one or more layers between the modal filter layer and the active region," and / or other appropriate adjustments. In one or more embodiments, by simultaneously oxidizing the current-limiting layer and the modal filter layer, the central axes of the current-limiting via and the optical aperture will be aligned or nearly aligned with each other. The term "performed together" does not necessarily mean that the oxidation processes must be performed at the same time. This is because if substantially the same oxidation process and / or the same oxidation environment are used, the central axes of the current-limiting via and the optical aperture can still be aligned even if the oxidation processes are not performed simultaneously (compared to the approach used for surface relief layers).

[0074] "Mutual alignment" means that the current-limiting via and the optical aperture have the same central axis, but their outlines can be different or the same. "Nearly mutual alignment" means that the central axes of the current-limiting via and the optical aperture are very close, or the degree of misalignment between the central axes of the current-limiting via and the optical aperture is reduced compared to surface relief layers fabricated by lithography processes in the prior art. When the current-limiting via and the optical aperture have the same central axis and their outlines are circular, they will be concentric circles. When the current-limiting via and the optical aperture are concentric circles, the divergence angle of the VCSEL can be reduced. It is well known that the current-limiting via in the current-limiting layer serves to limit both current and light. Although the modal filter layer also has an optical aperture, the optical aperture of the modal filter layer is independent of current limiting. However, in some embodiments, a small portion of the bias current may pass through the optical aperture of the surface relief layer. Therefore, in this embodiment, the first metal electrode, formed using a non-alloy or alloy process, allows most of the bias current to be guided from the first metal electrode into the active region. This reduces the bias current flowing through the optical aperture of the modal filter layer, and the resistance of the surface relief layer is not too high, thus reducing the impact on the power conversion efficiency and output power of the VCSEL. In one embodiment, the material of the current-limiting layer is selected from at least one material from the group consisting of AlGaAs, AlGaAsP, AlAs, AlAsP, AlAsSb, AlAsBi, InAlAs, and InAlAsSb. In another embodiment, the material of the modal filter layer is selected from at least one material from the group consisting of AlGaAs, AlGaAsP, AlAs, AlAsP, AlAsSb, AlAsBi, InAlAs, and InAlAsSb. In one or more embodiments, the via area of ​​the current-limiting via 50a and the optical aperture 120a may be equal or unequal; preferably, when the current-limiting via is not equal to the optical aperture, it helps to reduce the divergence angle. In one embodiment, the vertical-cavity surface-emitting diode (VCSEL) is either a front-emitting or back-emitting VCSEL. In another embodiment, the oxidation process can be performed using either a mesa-type or planar-type process. In a mesa-type process, the insulation process begins from the outer side of the platform, i.e., a lateral oxidation process starting from the sides of the mode filter layer and the current-limiting layer. In a planar-type process, multiple holes are formed in the multilayer structure using dry or wet etching, distributing the holes at different locations in the current-limiting layer. The insulation process involves oxidation diffusion from the center of the holes outwards. The epitaxial stack structure 100 or 101 is fabricated using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial growth methods. Figure 12 This is a graph showing the LI characteristics of a VCSEL with a modal filtering layer and a VCSEL with a surface embossing layer. Figure 12 The term "surface relief layer - misalignment 2μm" refers to a deviation of approximately 2μm between the central axis of the opening in the surface relief layer and the central axis of the current-limited via. Figure 12 The so-called "surface relief layer" refers to a situation where there is no significant deviation between the central axis of the opening of the surface relief layer and the central axis of the current-limiting via. Figure 12 The so-called "modal filter layer" refers to a modal filter layer whose central axis is precisely aligned with the central axis of the current-limiting via. Figure 12 It is clear that VCSELs with modal filtering layers have higher light output power than VCSELs with surface embossing layers. Figure 13 This diagram shows a VCSEL epitaxial chip structure with a surface relief layer disposed on an ohmic contact layer. Figure 14 It is a display Figure 7b The far-field profile of VCSELs and Figure 13 The far-field distribution of VCSELs. Figure 7b The diameter of the optical aperture 120a is 19 μm. Figure 13 The diameter of the opening 241 in the surface relief layer 240 is also 19 μm. And... Figure 7b and Figure 13 The diameter of the vias in the current confinement layer is 20 μm. Figure 7b Far-field distribution of VCSELs and Figure 13 The far-field distribution of the VCSELs was measured under a continuous wave (CW) bias current of 10mA. For example... Figure 14 As shown, Figure 7b The divergence angle of the structure ( Figure 14 (the solid line) at 1 / e 2 Width (1 / e) 2 The width is approximately 20 degrees, while Figure 13 The divergence angle of the structure ( Figure 14 (dashed line) at 1 / e 2 The width is approximately 24 degrees. From Figure 14 It is clear that the divergence angle of the dashed line is greater than that of the solid line. Therefore, Figure 7b Structural ratio Figure 13 The structure has a small divergence angle. The above description is only for explaining preferred embodiments of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications or changes made to the present invention under the same inventive spirit should still be included within the scope of protection intended by the present invention.

Claims

1. A vertical-cavity surface-emitting semiconductor laser diode (VCSEL), comprising: A substrate; and An epitaxial stacked structure, on the substrate, includes: One active zone; The first layer is the DBR layer, above this active region; A current-limiting layer, having a current-limiting via in or under the upper DBR layer; A modal filter layer is placed above the upper DBR layer and above the current limiting layer. A first ohmic contact layer is disposed between the upper DBR layer and the modal filter layer, or disposed on the modal filter layer; as well as A first metal electrode; The modal filter layer has an optical aperture, the modal filter layer can be oxidized, the modal filter layer is formed by oxidation treatment, and the first metal electrode passes through the oxidized portion of the modal filter layer and makes ohmic contact with the first ohmic contact layer. The central axis of the current-limiting via is nearly aligned with or aligned with the central axis of the optical aperture, and the outlines of the current-limiting via and the optical aperture are circular, and the current-limiting via and the optical aperture are concentric circles.

2. The vertical-cavity surface-emitting semiconductor laser diode as described in claim 1, wherein, The current-limiting layer can be oxidized, and the current-limiting via is formed by oxidizing the current-limiting layer.

3. The vertical-cavity surface-emitting semiconductor laser diode as described in claim 1, wherein, The vertical cavity surface-emitting semiconductor laser diode also includes a spacer layer, which is disposed between the upper DBR layer and the mode filter layer, above the upper DBR layer, or below the mode filter layer.

4. The vertical-cavity surface-emitting semiconductor laser diode as described in claim 1, wherein, The vertical cavity surface-emitting semiconductor laser diode includes a first semiconductor layer disposed on the mode filter layer.

5. The vertical-cavity surface-emitting semiconductor laser diode as described in claim 1, wherein, One end of the first metal electrode is electrically in contact with the first ohmic contact layer, while the other end passes through the modal filter layer and forms an electrical contact with a semiconductor layer below the modal filter layer.

6. The vertical-cavity surface-emitting semiconductor laser diode as described in claim 1, wherein, The vertical-cavity surface-emitting semiconductor laser diode also includes a second ohmic contact layer, which is located above the first ohmic contact layer and the mode filter layer, and the mode filter layer is located between the second ohmic contact layer and the first ohmic contact layer; the two ends of the first metal electrode are electrically in contact with the first ohmic metal layer and the second ohmic metal layer, respectively.

7. The vertical-cavity surface-emitting semiconductor laser diode as described in claim 1, wherein, The vertical cavity surface-emitting semiconductor laser diode is either a front-emitting vertical cavity surface-emitting semiconductor laser diode or a back-emitting vertical cavity surface-emitting semiconductor laser diode.

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