An active-clamp flyback converter

Abstract

The application discloses an active clamp flyback converter, which comprises a first capacitor, a second capacitor and a first resistor, a first switch tube, a second switch tube and a second resistor, a transformer comprising a leakage inductance, a primary winding, a secondary winding and an auxiliary winding, a first diode and a fourth capacitor, a second diode and a third capacitor, a first depletion-mode NMOS tube and a third resistor, and a control circuit comprising a driving module and a high-voltage power-on module, wherein the high-voltage power-on module controls the gate end of the first depletion-mode NMOS tube during the chip starting process, obtains energy from a high-voltage switch node, and charges the power supply rail of the control circuit. The high-voltage power-on module realizes safe power-on by limiting the charging current during the power-on process of the control circuit, and the charging circuit is turned off after the power-on of the control circuit is completed, so that the static current of the active clamp flyback converter is reduced, and the efficiency is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power supply starting, in particular to an active clamp flyback converter. BACKGROUND

[0002] At present, global electronic products are constantly innovating, and AC-DC converters applied to USB PD fast charging have high requirements for power density and converter efficiency. Most of the current AC-DC converters adopt flyback topology. Compared with the traditional flyback converter, the active clamp flyback converter improves the utilization rate of leakage energy and can realize soft opening of the power tube, thereby effectively improving the efficiency.

[0003] The input of the conventional flyback topology system is the mains, and the bus voltage after full-bridge rectification and filtering of the voltage stabilizing capacitor can be higher than 400V. The high-voltage starting circuit of the traditional flyback converter chip adopts an off-chip resistor voltage division form to start the chip, but there is still power consumption on the resistor after the chip starts, which reduces the system efficiency. In order to improve the efficiency, a depletion mode high-voltage MOS tube controlled by the chip can be connected in series between the chip and the bus voltage, which can prevent the chip from being damaged by high bus voltage and can turn off the high-voltage power supply path after the chip starts, thereby saving power consumption. However, this high-voltage power supply method is relatively complex and poses a great challenge to the design of related circuits and chip power-on timing. SUMMARY

[0004] The purpose of the present application is to provide a general high-voltage starting circuit suitable for active clamp flyback converters and having a self-turn-off function after high-voltage power-on, so as to solve the problem of power consumption and reduction of the overall efficiency of the AC-DC converter caused by the inability to turn off after power-on of the traditional off-chip resistor voltage division type power-on.

[0005] The technical solution of the present application is as follows:

[0006] An active clamp flyback converter, characterized in that it comprises a transformer, a first switch tube, a second switch tube, a first high-voltage depletion mode NMOS tube, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first diode, a second diode, a leakage inductance, and a control circuit.

[0007] The transformer has a primary winding, a secondary winding, and an auxiliary winding, wherein the same name end of the primary winding is connected to the bus voltage through the leakage inductance.

[0008] The drain of the first switch tube is connected to the bus voltage through a circuit composed of the first resistor and the second capacitor in parallel, the gate and the source of the first switch tube are connected to the control circuit, and the source of the first switch tube is also connected to the drain of the second switch tube, the drain of the first high-voltage depletion mode NMOS tube, and the different name end of the primary winding.

[0009] The gate and the source of the second switch tube are connected to the control circuit, and the source of the second switch tube is further connected to the ground through the second resistor;

[0010] The gate and the source of the first high-voltage depletion-mode NMOS tube are connected to the control circuit, one end of the third resistor is connected to the gate of the first high-voltage depletion-mode NMOS tube, and the other end of the third resistor is connected to the source of the first high-voltage depletion-mode NMOS tube;

[0011] The anode of the second diode is connected to the opposite end of the auxiliary winding, the cathode of the second diode is connected to one end of the third capacitor and the control circuit, and the same end of the auxiliary winding and the other end of the third capacitor are connected to the ground;

[0012] The anode of the first diode is connected to the opposite end of the secondary winding, the cathode of the first diode is connected to one end of the fourth capacitor, and the same end of the secondary winding and the other end of the fourth capacitor are connected to the ground;

[0013] The control circuit comprises a driving module and a high-voltage power-on module; wherein the driving module is connected to the gate and the source of a switch tube and the gate and the source of a second switch tube; the driving module is a necessary circuit module in a traditional active clamping flyback converter, and the application does not improve it, and unnecessary description of this part is omitted;

[0014] The high-voltage power-on module comprises a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a first high-voltage PMOS tube, a second high-voltage PMOS tube, a third high-voltage PMOS tube, a fourth high-voltage PMOS tube, a fifth high-voltage PMOS tube, a second high-voltage NMOS tube, a third high-voltage NMOS tube, a fourth high-voltage NMOS tube, a fifth high-voltage NMOS tube, a first low-voltage NMOS tube, a second low-voltage NMOS tube, a first reference module, a first comparator module, a first operational amplifier module, a third Zener diode, a fourth Zener diode, a fifth Zener diode, a sixth Zener diode and a seventh Zener diode;

[0015] The opposite end of the primary winding is connected to one end of the fourth resistor and one end of the eighth resistor; the other end of the fourth resistor is connected to one end of the fifth resistor and the source of the third high-voltage PMOS tube; the other end of the eighth resistor is connected to the gate of the second high-voltage NMOS tube, the cathode of the sixth Zener diode, the drain of the first low-voltage NMOS tube and the gate of the fifth high-voltage NMOS tube; the source of the first low-voltage NMOS tube and the anode of the sixth Zener diode are connected to the ground;

[0016] The gate of the first low-voltage NMOS tube is connected to the output end of the first comparator module; the positive input end of the first comparator module is connected to one end of the thirteenth resistor and one end of the fourteenth resistor, and the negative input end of the first comparator module is connected to the reference voltage output by the first reference module;

[0017] The other end of the fifth resistor is connected to the source of the first high-voltage PMOS tube, the gate of the first high-voltage PMOS tube is connected to the one end of the sixth resistor, the one end of the seventh resistor, the anode of the third Zener diode and the gate of the second high-voltage PMOS tube, the drain of the first high-voltage PMOS tube is connected to the other end of the sixth resistor, the cathode of the third Zener diode and the source of the second high-voltage PMOS tube;

[0018] The other end of the seventh resistor is connected to the drain of the second high-voltage NMOS tube, and the source of the second high-voltage NMOS tube is connected to the ground;

[0019] The gate of the third high-voltage PMOS tube is connected to the one end of the ninth resistor, the one end of the tenth resistor, the anode of the fourth Zener diode and the gate of the fourth high-voltage PMOS tube, the drain of the third high-voltage PMOS tube is connected to the other end of the ninth resistor, the cathode of the fourth Zener diode and the source of the fourth high-voltage PMOS tube;

[0020] The other end of the tenth resistor is connected to the drain of the fourth high-voltage NMOS tube, the gate of the fourth high-voltage NMOS tube is connected to the one end of the sixteenth resistor and the drain of the second low-voltage NMOS tube, and the source of the fourth high-voltage NMOS tube is connected to the ground;

[0021] The drain of the second high-voltage PMOS tube is connected to the drain of the fourth high-voltage PMOS tube, the source of the fifth high-voltage PMOS tube, the cathode of the fifth Zener diode, the other end of the thirteenth resistor, the one end of the fifteenth resistor, the drain of the third high-voltage NMOS tube and the cathode of the second diode;

[0022] The anode of the fifth Zener diode is connected to the output of the first operational amplifier module, the gate of the fifth high-voltage PMOS tube and the drain of the fifth high-voltage NMOS tube, the negative input of the first operational amplifier module is connected to the reference voltage output by the first reference module, the positive input of the first operational amplifier is connected to the one end of the eleventh resistor and the one end of the twelfth resistor, the drain of the fifth high-voltage PMOS tube is connected to the other end of the tenth resistor and the gate of the first high-voltage depletion-mode NMOS tube, and the source of the fifth high-voltage NMOS tube and the other end of the twelfth resistor are connected to the ground;

[0023] The other end of the fourteenth resistor is connected to the ground, the other end of the fifteenth resistor is connected to the gate of the third high-voltage NMOS tube and the cathode of the seventh Zener diode, the anode of the seventh Zener diode is connected to the ground, the source of the third high-voltage NMOS tube is connected to the one end of the sixteenth resistor, the other end of the sixteenth resistor is connected to the drain of the second low-voltage NMOS tube, and the gate of the second low-voltage NMOS tube is connected to the output of the first comparator.

[0024] The beneficial effects of the present application are:

[0025] The high-voltage power-on module in the active clamp flyback converter of the application can realize the self-start of the active clamp flyback converter system under high-voltage input by detecting the power supply voltage and actively controlling the external high-voltage tube, and can close the charging path after completing the start, so as to optimize the standby power consumption and conversion efficiency of the system by reducing the static current. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A circuit structure schematic diagram of an existing active clamp flyback converter is shown.

[0027] Figure 2 A timing waveform diagram of the active clamp flyback converter is shown. Figure 1

[0028] Figure 3 A circuit structure schematic diagram of the power supply system provided by the embodiment of the application is shown.

[0029] Figure 4 A timing waveform diagram of the active clamp flyback converter is shown. Figure 3 A schematic diagram of the internal structure of the high-voltage power-on module in the active clamp flyback converter during the chip start-up process is shown.

[0030] Figure 5 A timing waveform diagram of the active clamp flyback converter during the chip start-up process is shown. Figure 3

[0031] Figure 6 A schematic diagram of the internal structure of the high-voltage power-on module in the active clamp flyback converter after the chip completes the start-up is shown. Figure 3 DETAILED DESCRIPTION

[0032] In order to facilitate the understanding of the application, the application will be described more fully below with reference to the related drawings, which show some embodiments of the application. It should be noted that the application can be realized in different forms and is not limited to the specific embodiments described herein. These embodiments are provided to better illustrate the application and make the disclosure of the application more thorough and comprehensive.

[0033] Figure 1 A circuit structure of an existing active clamp flyback converter is shown, in which the upper switch tube Q1 is the first switch tube, the lower switch tube Q2 is the second switch tube, and the key node waveform of Q1 and Q2 working in the complementary mode of the switching signal is shown. Figure 2 As shown, I LM is the excitation current on the excitation inductor Lm, and Vgs1 and Vgs2 are the driving signals of Q1 and Q2, respectively.

[0034] Reference is made to Figure 2 , Figure 1 ​​​The working principle of the active clamp flyback converter shown as follows:

[0035] At t0, Q2 transistor control signal Vgs2 is high, Q2 transistor is on.

[0036] In the period of t0-t1, Q1 transistor control signal Vgs1 is low, Q2 transistor control signal Vgs2 is high, Q1 transistor is off, and Q2 transistor is on. In this period, the active clamp flyback converter is powered from bus voltage V BULK to obtain energy and store energy through leakage inductance L k , excitation inductance L M , Q2 transistor and R2 resistor to excite transformer TR1, and excitation current I LM starts from zero and increases linearly, leakage inductance L K and excitation inductance L M store energy, and at the same time, secondary rectifier diode D1 is reverse-biased, so this stage does not supply energy to output Vo.

[0037] At t1, Q2 transistor control signal Vgs2 becomes low, and Q2 transistor is off.

[0038] In the period of t1-t2, Q1 transistor and Q2 transistor are both off, and this period is the first dead time. In this period, leakage inductance L K , excitation inductance L M , Q1 transistor drain-source capacitance and Q2 transistor drain-source capacitance will resonate, and the energy of leakage inductance Lk and excitation inductance Lm is transferred to Q1 transistor drain-source capacitance and Q2 transistor drain-source capacitance, so that V SW rises; when V SW rises to V , D1 is turned on, and the active flyback converter supplies energy to the output, where is the primary and secondary transformer turn ratio, and V D1 is the forward conduction voltage drop of secondary rectifier diode D1.

[0039] At t2, Q1 transistor control signal Vgs1 becomes high, and Q1 transistor is on.

[0040] In the period of t2-t3, Q1 transistor is on, Q2 transistor is off, secondary rectifier diode D1 is forward-biased, and the energy of excitation inductance L M is transferred to the secondary output Vo, so I LM linearly decreases; when I LM decreases to zero, secondary rectifier diode D1 is off, and the voltage across excitation inductance L M is no longer clamped by V O , at which time leakage inductance L K , excitation inductance L M and clamp capacitor C CLAMPResonance occurs, causing the excitation current I LM Resonance in the negative direction.

[0041] At time t3, the control signal Vgs1 for transistor Q1 goes low, and transistor Q1 is turned off.

[0042] During the time interval t3-t4, both transistors Q1 and Q2 are turned off. This period is the second dead time because the negative magnetizing current I... LM To continue the flow, therefore leakage inductance L K Magnetizing inductance L M The drain-source capacitances of transistors Q1 and Q2 will resonate, and the drain-source capacitance and leakage inductance L of transistor Q1 will also resonate. K And excitation inductance L M The energy is transferred to the drain-source capacitor of transistor Q2, making V SW reduce.

[0043] It should be noted that V during the first dead zone time SW The increase is due to the excitation current I at time t1, the beginning of the first dead time. LM The initial current direction is positive, i.e., I LM To V SW Node flow; V during the second dead time SW The decrease is due to the excitation current I at the beginning of the second dead time, t3. LM The initial current direction is negative, i.e., I LM From V SW Node outflow.

[0044] At time t4, V SW When the voltage drops to zero, the control signal Vgs2 for transistor Q2 goes high, achieving zero-voltage turn-on for transistor Q2. This completes one switching cycle of the active clamp flyback converter, which will then repeat the same control logic and operating process.

[0045] like Figure 3 As shown, the power supply system in this embodiment of the invention includes: an AC power supply 1, a rectifier circuit 2, and a first capacitor C. BULK 3. Flyback converter, wherein flyback converter 3 includes, but is not limited to, Figure 1 The active clamp flyback converter shown is shown.

[0046] Rectifier circuit 2 rectifies AC power supply 1 into a second voltage signal V. BULK It serves as the input to flyback converter 3. Optionally, rectifier circuit 2 can be a half-bridge rectifier or a full-bridge rectifier circuit.

[0047] In this embodiment of the invention, the flyback converter 3 is an active clamp flyback converter, which includes: a second capacitor C2, a third capacitor C3, a fourth capacitor Co, a first resistor R1, a second resistor R2, a third resistor R3, a first switch Q1, a second switch Q2, a first depletion-mode high-voltage NMOS transistor MNH1, a first rectifier diode D1, a second rectifier diode D2, a control circuit 31 including a drive module 311 and a high-voltage power-on module 312, and a primary winding Np, a secondary winding Ns, an auxiliary winding Na, and a leakage inductance L. K Transformer 33.

[0048] In this embodiment of the invention, the second voltage signal V BULK The second capacitor C2 and the first resistor R1 are connected in parallel to the drain of the first switching transistor Q1. The gate and source terminals of the first switching transistor are connected to the drive module 311. The source terminal of the first switching transistor is also connected to the third voltage signal V. SW Second voltage signal V BULK Also through the series leakage inductance L K The primary winding Np is connected to the third voltage signal V. SW The gate and source terminals of the second switching transistor are connected to the drive module 311, and the source terminal of the second switching transistor is connected to the primary reference ground through the second resistor R2.

[0049] During the same switching cycle of the flyback converter 3, the first switch Q1 and the second switch Q2 are turned on in a time-sharing manner to realize the transfer of the second voltage signal V. BULK Energy is obtained from the primary winding Np and transferred to the secondary side of the flyback converter 3 to output Vo. Optionally, the first switch Q1 and the second switch Q2 can be NMOS transistors or N-type GaN transistors.

[0050] The secondary side of the flyback converter 3 includes a secondary winding Ns, a first rectifier diode D1, and a fourth capacitor Co. The anode of the first rectifier diode D1 is connected to the opposite-named terminal of the secondary winding Ns, and the cathode of the first rectifier diode D1 is connected to the output Vo of the flyback converter 3. The anode of the fourth capacitor Co is connected to the output Vo of the flyback converter 3, and the cathode of the fourth capacitor Co is connected to the secondary reference ground. The same-named terminal of the secondary winding is connected to the secondary reference ground. In one possible embodiment, the output Vo of the flyback converter 3 is connected to a load, and the load receives a second voltage signal V from the flyback converter 5. BULK The power is obtained from the load and transmitted to the output of the flyback converter. In one possible embodiment, the output of the flyback converter 5 is connected to the load through a BUS switch controlled by the PD fast charging chip, thereby controlling the power of the power received by the load. Optionally, the BUS switch can be an NMOS transistor or an N-type GaN transistor.

[0051] The auxiliary winding Na of transformer 33 has its same-name terminal connected to the primary reference ground and its opposite-name terminal connected to the anode of the second diode. The cathode of the second diode is connected to the anode of the third capacitor, and the cathode of the third capacitor is connected to the primary reference ground. After the chip is started, the auxiliary winding Na is responsible for supplying power to the chip's power rail VDD.

[0052] The control circuit 31 generates control signals Vgs1 and Vgs2 for the first switch Q1 and the second switch Q2, and uses the drive module 311 to drive Q1 and Q2 to control their switching states, where Vgs1 = VG1 - VS1 and Vgs2 = VG2 - VS2.

[0053] The control circuit 31 includes a high-voltage power-on module 312. The function of this module is to generate a sixth voltage signal HVG to control the gate terminal of the first depletion-type NMOS transistor MNH1 based on the voltage values ​​of the fourth voltage signal VDD (the fourth voltage signal VDD serves as part of the power rail of the control circuit 31) and the fifth voltage signal SWS during the chip startup process.

[0054] The chip startup described in this invention refers to the process whereby, after the AC power supply 1 rises from zero to the effective value of the AC mains voltage and the AC voltage frequency, the flyback converter 3 starts based on the second voltage signal V rectified by the rectifier circuit 2. BULK The positive power rail VDD of the control circuit 31 is charged to the chip operating voltage VDD. (ON) This process. In a common embodiment for practical applications, the effective value of the AC mains voltage is 110V to 230V, and the frequency of the AC mains voltage is 50Hz to 60Hz. In one possible embodiment, the positive power rail VDD supplies power not only to the control circuit 31, but also to other modules on the primary side of the flyback converter 3.

[0055] During chip startup, both transistors Q1 and Q2 are turned off. The current flowing through the primary winding Np and the first depletion-mode high-voltage NMOS transistor MNH1, charging VDD, is much smaller than the current flowing through the primary winding Np when the flyback converter 3 is operating normally. Therefore, the third voltage signal V can be approximated as... SW During chip startup, it is approximately equal to the second voltage signal V. BULK (V BULK In a common practical application embodiment, the AC power supply 1 and rectifier circuit 2 can be 150-400V after being powered on.

[0056] The third resistor R3 is a large resistor, which serves as a setter, making the initial voltage values ​​of HVG and SWS equal when the chip starts up. That is, the initial value of Vgs of the first depletion-type NMOS transistor MNH1 is zero, and the threshold voltage Vth of the depletion-type NMOS transistor is less than zero. Therefore, the initial state of the first depletion-type NMOS transistor MNH1 when the chip starts up is the on state.

[0057] The drain of the first high-voltage depletion NMOS transistor MNH1 is connected to the second voltage signal V SW Because V SW The voltage value during the chip startup process is much higher than the gate voltage value of MNH1, so if MNH1 is turned on, it works in the saturation region, and the source voltage SWS of MNH1 is determined by the gate voltage HVG of MNH1 and the drain-source current I DS1 Thus, the voltage value of the fifth voltage signal SWS connected to the high-voltage power-on module 312 is limited, and the chip is protected from being broken down by the high voltage V SW .

[0058] The first high-voltage depletion NMOS transistor MNH1 works in the saturation region during the chip startup process, and its drain-source current I DS1 satisfies:

[0059]

[0060] where β1 is a constant related to the device characteristics of MNH1 itself, V TH_MNH1 is the threshold voltage of MNH1. In one possible application example, MNH1 uses a 600V voltage (drain-source voltage) depletion NMOS with a model number of BSS126 from Infineon, and its threshold voltage has a typical value of -2V, a minimum value of -2.7V, and a maximum value of -1.6V.

[0061] Figure 4 The specific circuit structure of the high-voltage power-on module 312 is shown, where BG1 is a first bandgap reference source, V BIAS is a coarse power rail generated inside the high-voltage power-on module 312, COMP1 is a first comparator, and EA1 is a first operational amplifier.

[0062] Referring to Figure 5 , in combination with Figure 3 , Figure 4 The working principle of the high-voltage power-on module 312 is as follows:

[0063] At time t0, Figure 3 The AC power supply 1 and the rectifier circuit 2 complete the power-on of V BULK , and V BULK reaches a steady-state value, and HVG and SWS are both 0V.

[0064] In the time period from t0 to t1, Figure 3 Vgs of MNH1 in the high-voltage power-on module 312 is greater than V TH_MNH1 , and MNH1 works in the saturation region; during this time period, V TH_MNH1 <SWS<V TH_MNH2 , where V TH_MNH2The threshold voltage of MNH2 is Vth, and VDD = 0V, so MNH2 and MNH4 are both off, R6 and R9 short the gate-source of MPH2 and MPH4 respectively, so MPH2 and MPH4 are off, and in the high-voltage power-on module 312, SWS has no path to the primary side reference ground, so the channel current IDS1 of MNH1 charges SWS, and SWS rises.

[0065] At t1, SWS rises to V TH_MNH2 , MNH2 and MNH5 are on, and current flows through R6 and R7.

[0066] In the period from t1 to t2, SWS continues to rise, so that the Vgs of MNH2 increases, the drain-source current of MNH2 increases, the current flowing through R6 increases, and the gate voltages of MPH1 and MPH2 gradually decrease, so that MPH1 and MPH2 are turned on, providing a first current path between SWS and VDD, so that VDD rises, wherein R4 and R5 act as current limiters; at the same time, the continuous rise of SWS also increases the Vgs of MNH5, and the drain-source current of MNH5 increases, thereby pulling down the gate of MPH5, and the pull-down capability of MNH5 is stronger, so that the output of the first operational amplifier EA1 cannot control the gate of MPH5.

[0067] At t2, VDD rises to |V TH_MPH5 | (the absolute value of the threshold voltage of MPH5), MPH5 is turned on, and a second current path between VDD and HVG is provided.

[0068] Further, R4 is an on-chip resistor, and its current capacity is usually limited, and in order to ensure the safety of high-voltage power-on, the charging current of high-voltage power-on needs to be reduced, and in a common embodiment in actual application, the drain-source current I DS1 of the first high-voltage depletion NMOS transistor MNH1 is several mA. In a possible application example, MNH1 uses a 600V voltage-withstanding (drain-source voltage-withstanding) depletion NMOS transistor of the BSS126 type from Infineon, and for equation (1), the β value of BSS126 is large, and it can be approximately considered that when I DS1 is of the order of several mA, its V GS ≈V TH_MNH1 , that is, during high-voltage power-on, HVG ≈ SWS - |V TH_MNH1 |.

[0069] In the period from t2 to t3, SWS continues to rise, the first current path causes VDD to continue to rise with SWS, and the second current path causes HVG to continue to rise with VDD, when the source-drain voltage V SD_MPH1 of MPH1 is equal to the forward conduction voltage drop of its body diode, the body diode of MPH1 is turned on, and the source-drain voltage VSD_MPH1 is clamped to its body diode forward conduction voltage drop.

[0070] At time t3, VDD rises to V TH_MNH3 +V TH_MNH4 , MNH3 and MNH4 turn on, where V TH_MNH3 is the threshold voltage of MNH3, V TH_MNH4 is the threshold voltage of MNH4.

[0071] During the time period t3 to t4, SWS, VDD and HVG continue to rise, so that the V GS of MNH4 increases, the drain-source current of MNH4 increases, the current flowing through R9 increases, the gate voltage of MPH3 and MPH4 gradually decreases, so that MPH3 and MPH4 turn on, providing a third current path between SWS and VDD, accelerating the rising speed of VDD, when the source-drain voltage V SD_MPH3 of MPH3 equals its body diode forward conduction voltage drop, the body diode of MPH3 turns on, the source-drain voltage V SD_MPH3 of MPH3 is clamped to its body diode forward conduction voltage drop.

[0072] At time t4, D3 reverse breakdown, thus protecting the gate-source of MPH2 from breakdown. The source voltage V B of MPH2 = V D3 +V R7 , where V D3 is the reverse breakdown voltage of D3, V R7 is the voltage across R7, so the voltage value of V B can follow the rising of SWS without being clamped by D3, VDD can follow V B , i.e. VDD can follow the rising of SWS, so that HVG also follows the rising of SWS. At the same time, because the body diode of MPH1 turns on, the gate-source voltage V GS_MPH1 of MPH1 = -V D3 -V bd_MPH1 , where V bd_MPH1 is the forward conduction voltage drop of the body diode of MPH1, so the gate-source voltage of MPH1 is also clamped and no longer decreases, protecting the gate-source of MPH1 from breakdown.

[0073] During the time period t4 to t5, SWS, VDD and HVG continue to rise.

[0074] At time t5, D4 reverse breakdown, thus protecting the gate-source of MPH4 from breakdown. The source voltage V C of MPH4 = V D3 +V R7 , where V D4 is the reverse breakdown voltage of D4, V R10V C The voltage value of V GS_MPH3 = -V D4 -V bd_MPH3 , where V bd_MPH3 is the forward voltage drop of the body diode of MPH3, so the gate-source voltage of MPH3 is also clamped and no longer decreases, protecting the gate-source of MPH3 from breakdown.

[0075] In the time period from t5 to t6, SWS, VDD and HVG continue to rise.

[0076] At time t6, VDD rises to the reverse breakdown voltage V D7 of D7, D7 reversely breaks down, the gate of MNH3 is clamped to V D7 , so V BIAS and V2 are less than V D7 -V TH_MNH3 , thus protecting the devices connected to V BIAS and V2 from the high voltage of the rising VDD; V BIAS is the rough power supply rail to supply the first bandgap reference source BG1 and the first comparator COMP1, V REF is the bandgap reference voltage output of BG1 connected to the inverting input of COMP1, the non-inverting input of COMP1 is connected to the resistor voltage division value V1 of VDD, at this moment V REF is greater than V1, so the output V EN of COMP1 is low, MN1 and MN2 are still off. Meanwhile, D5 reversely breaks down, protecting the gate-source of MPH5 from breakdown.

[0077] In the time period from t6 to t7, SWS, VDD and HVG continue to rise.

[0078] At time t7, VDD rises to the chip working voltage VDD (ON) , the resistor voltage division value V1 of VDD is greater than V REF , the output V EN of the first comparator COMP1 flips high, MN1 and MN2 turn on; MN1 pulls down the gate of MNH2, turning off MNH2, no current flows through R6 and R7, MPH2 is turned off, the first current path from SWS to VDD is turned off; MN1 simultaneously pulls down the gate of MNH5, turning off MNH5, the output of the first operational amplifier EA1 restores the regulating ability to the gate of MPH5; MN2 pulls down the gate of MNH4, turning off MNH4, no current flows through R9 and R10, MPH4 is turned off, the third current path from SWS to VDD is turned off; at this moment, the voltage value of HVG is HVG ENDSince the current path from SWS to VDD is completely shut off, Figure 3 No current flows through MNH1, so MNH1 is turned off, and its gate-source voltage is equal to V. TH_MNH1 That is, SWS = HVG - V TH_MNH1 At this point, the chip has been powered on at high voltage.

[0079] The HVG voltage value determined by the negative feedback loop consisting of EA1, MPH5, R11, and R12 after the chip starts up can be expressed as:

[0080]

[0081] After the chip starts up, the auxiliary winding Na is responsible for supplying power to VDD. Figure 3 The active clamp flyback converter 3 in the middle operates at Figure 2 During the time period t2 to t3 shown, when transistor Q1 is on and transistor Q2 is off, the voltage V at the opposite terminal of the auxiliary winding Na is... Na_n >VDD+V D2 V D2 The forward voltage drop of D2 causes D2 to conduct, and the auxiliary winding will supply power to VDD. At this time, V Na_n The expression is:

[0082]

[0083] Furthermore, in one possible embodiment, VDD (ON) >V Na_n Therefore, after the chip has finished powering on, such as Figure 3 As shown:

[0084] During the time interval from t7 to t8, the auxiliary winding Na does not supply power to VDD. The control circuit 31 relies on the energy stored in C3 to maintain the chip's operation, and VDD decreases. The HVG voltage value is greater than the HVG voltage value determined by the negative feedback loop composed of EA1, MPH5, R12, and R13. Under the regulation of the negative feedback loop, HVG decreases, and SWS follows HVG's decrease.

[0085] At time t8, HVG decreases to SWS dropped to

[0086] During the time interval from t8 to t9, HVG and SWS remain unchanged, while VDD continues to decrease.

[0087] At time t9, VDD <V Na_n -V D2 And the flyback converter operates at Figure 2 During the time period from t2 to t3, the auxiliary winding Na is responsible for supplying power to VDD.

[0088] After t9, when the flyback converter works in Figure 2 VDD drops as shown in the period of t0 to t1 or t3 to t4; when the flyback converter works in Figure 2 the period of t2 to t3, Figure 3 D2 in the period of t2 to t3 turns on, the auxiliary winding Na supplies power to VDD, and VDD rises to the maximum value of:

[0089]

[0090] In one possible embodiment, the VDD voltage value determined by the auxiliary winding Na after the chip starts is 20V, and the HVG voltage value determined by the negative feedback loop composed of EA1, MPH5, R11, R12 in Figure 4 MNH1 turns on, then SWS is always less than 12V-V TH_MNH1 When the flyback converter works in Figure 2 the period of t0 to t1, V SW is 0V, MNH1 works in the linear region, and SWS is also 0V, Figure 4 the source-drain of some MOS tubes in the high-voltage power-on module 312 is interchanged, Figure 6 the circuit structure of the high-voltage power-on module 312 in this case is shown, and its working principle is as follows:

[0091] Figure 6 the working states of the first bandgap reference source BG1, the first comparator COMP1, MN1, MNH2, D6, MNH4, EA1, D5, MNH5, MPH5, D7, MNH3, and MN2 in Figure 3 are the same as those of the devices at the t7 moment shown in Figure 4

[0092] VDD>SWS>HVG in Figure 6 the source-drain of the corresponding devices in Figure 4 is interchanged, and the four MOS tubes are all turned off, wherein the body diodes of MPH2 and MPH4 turn on, and the drain ends of MPH1 and MPH3 are the voltage drift regions, which bear the voltage difference from VDD to SWS.

[0093] In summary, the present application samples the chip power supply VDD and the source end SWS of the external power tube during the power-on process of the flyback converter control chip, according to the voltage values, opens the first current path and the third current path from SWS to VDD and the second circuit path from VDD to the gate end HVG of the external power tube in time, and realizes the switching from the switching node V SWThe energy is obtained by an external depletion type high voltage NMOS transistor MNH1 to charge the chip power supply VDD to VDD (ON) , and the charging current of VDD is controlled in time during the chip power-on process, which ensures the reliability of the chip power-on. Further, by detecting that the voltage value of the chip VDD is greater than VDD (ON) , it is judged that the chip power-on is completed, and the current path from SWS to VDD is turned off, which reduces the static power consumption compared with the traditional off-chip resistance power-on, thereby improving the efficiency of the flyback converter.

[0094] Finally, it should be noted that: obviously, the above embodiments are only examples for clearly illustrating the present application, and are not limitations on the embodiments. For ordinary skilled persons in the art, other different forms of changes or variations can be made on the basis of the above description. Here, it is not necessary and impossible to exhaust all the embodiments. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An active-clamp flyback converter, characterized in that, The transformer, the first switch tube, the second switch tube, the first high-voltage depletion mode NMOS tube, the first resistor, the second resistor, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor, the first diode, the second diode, the leakage inductance and the control circuit are included. The transformer has a primary winding, a secondary winding and an auxiliary winding, wherein the same name end of the primary winding is connected to the bus voltage through the leakage inductance. The drain of the first switch tube is connected to the bus voltage through the circuit composed of the first resistor and the second capacitor in parallel, the gate and the source of the first switch tube are connected to the control circuit, and the source of the first switch tube is also connected to the drain of the second switch tube, the drain of the first high-voltage depletion mode NMOS tube and the different name end of the primary winding. The gate and the source of the second switch tube are connected to the control circuit, and the source of the second switch tube is also connected to the ground through the second resistor. The gate and the source of the first high-voltage depletion mode NMOS tube are connected to the control circuit, one end of the third resistor is connected to the gate of the first high-voltage depletion mode NMOS tube, and the other end of the third resistor is connected to the source of the first high-voltage depletion mode NMOS tube. The different name end of the auxiliary winding is connected to the anode of the second diode, the cathode of the second diode is connected to the control circuit and one end of the third capacitor, and the same name end of the auxiliary winding and the other end of the third capacitor are connected to the ground. The different name end of the secondary winding is connected to the anode of the first diode, the cathode of the first diode is connected to one end of the fourth capacitor, and the same name end of the secondary winding and the other end of the fourth capacitor are connected to the ground. The control circuit includes a driving module and a high-voltage power-on module; wherein the gate and the source of a switch tube and the gate and the source of the second switch tube are connected to the driving module. The high-voltage power-on module includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a first high-voltage PMOS tube, a second high-voltage PMOS tube, a third high-voltage PMOS tube, a fourth high-voltage PMOS tube, a fifth high-voltage PMOS tube, a second high-voltage NMOS tube, a third high-voltage NMOS tube, a fourth high-voltage NMOS tube, a fifth high-voltage NMOS tube, a first low-voltage NMOS tube, a second low-voltage NMOS tube, a first reference module, a first comparator module, a first operational amplifier module, a third Zener diode, a fourth Zener diode, a fifth Zener diode, a sixth Zener diode and a seventh Zener diode. The different name end of the primary winding is connected to one end of the fourth resistor and one end of the eighth resistor; the other end of the fourth resistor is connected to one end of the fifth resistor and the source of the third high-voltage PMOS tube; the other end of the eighth resistor is connected to the gate of the second high-voltage NMOS tube, the cathode of the sixth Zener diode, the drain of the first low-voltage NMOS tube and the gate of the fifth high-voltage NMOS tube; the source of the first low-voltage NMOS tube and the anode of the sixth Zener diode are connected to the ground. The gate of the first low-voltage NMOS tube is connected to the output end of the first comparator module; the positive input end of the first comparator module is connected to one end of the thirteenth resistor and one end of the fourteenth resistor, and the negative input end of the first comparator module is connected to the reference voltage output by the first reference module. The other end of the fifth resistor is connected to the source of the first high-voltage PMOS tube, the gate of the first high-voltage PMOS tube is connected to the one end of the sixth resistor, the one end of the seventh resistor, the anode of the third Zener diode and the gate of the second high-voltage PMOS tube, the drain of the first high-voltage PMOS tube is connected to the other end of the sixth resistor, the cathode of the third Zener diode and the source of the second high-voltage PMOS tube; The other end of the seventh resistor is connected to the drain of the second high-voltage NMOS tube, and the source of the second high-voltage NMOS tube is connected to the ground; The gate of the third high-voltage PMOS tube is connected to the one end of the ninth resistor, the one end of the tenth resistor, the anode of the fourth Zener diode and the gate of the fourth high-voltage PMOS tube, the drain of the third high-voltage PMOS tube is connected to the other end of the ninth resistor, the cathode of the fourth Zener diode and the source of the fourth high-voltage PMOS tube; The other end of the tenth resistor is connected to the drain of the fourth high-voltage NMOS tube, the gate of the fourth high-voltage NMOS tube is connected to the one end of the sixteenth resistor and the drain of the second low-voltage NMOS tube, and the source of the fourth high-voltage NMOS tube is connected to the ground; The drain of the second high-voltage PMOS tube is connected to the drain of the fourth high-voltage PMOS tube, the source of the fifth high-voltage PMOS tube, the cathode of the fifth Zener diode, the other end of the thirteenth resistor, the one end of the fifteenth resistor, the drain of the third high-voltage NMOS tube and the cathode of the second diode; The anode of the fifth Zener diode is connected to the output of the first operational amplifier module, the gate of the fifth high-voltage PMOS tube and the drain of the fifth high-voltage NMOS tube; the negative input of the first operational amplifier module is connected to the reference voltage output by the first reference module, the positive input of the first operational amplifier is connected to the one end of the eleventh resistor and the one end of the twelfth resistor; the drain of the fifth high-voltage PMOS tube is connected to the other end of the tenth resistor and the gate of the first high-voltage depletion-mode NMOS tube; the source of the fifth high-voltage NMOS tube and the other end of the twelfth resistor are connected to the ground; The other end of the fourteenth resistor is connected to the ground; the other end of the fifteenth resistor is connected to the gate of the third high-voltage NMOS tube and the cathode of the seventh Zener diode, the anode of the seventh Zener diode is connected to the ground; the source of the third high-voltage NMOS tube is connected to the one end of the sixteenth resistor; the other end of the sixteenth resistor is connected to the drain of the second low-voltage NMOS tube, and the gate of the second low-voltage NMOS tube is connected to the output of the first comparator.

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