A high efficiency slew rate enhanced fully differential operational transconductance amplifier

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to a high-efficiency swing rate enhanced full-differential operational transconductance amplifier. The circuit of the application comprises an input signal following circuit, an alternating current signal coupling circuit and an operational transconductance amplifier main circuit. The input signal following circuit effectively reduces the output impedance by adding local negative feedback, and ensures effective following of the input signal under the condition that the load current changes greatly. The alternating current signal coupling circuit adopts a complementary gate-source short MOS tube structure, ensures high impedance under the condition that the internal node swing is large, thereby realizing good alternating current coupling characteristics, and improving current utilization rate and small signal performance. The operational transconductance amplifier main circuit adopts a following circuit to expand the signal amplitude between the input tube gate and source, and under the condition of a large signal, the current-voltage conversion ratio is improved to 4 times of that of the traditional structure, and is no longer limited by the fixed tail current.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a high-efficiency slew rate enhanced fully differential operational transconductance amplifier. Background Technology

[0002] Fully differential operational transconductance amplifiers (LCAs) are core modules in various analog circuits and are widely used in data conversion, reference generation, image sensing, and many other applications. The primary function of a LCA is to convert voltage to current, and it can also be used as a buffer / gain module by adding external feedback.

[0003] The efficiency (FOM) of a fully differential operational transconductance amplifier largely determines the power consumption of the entire analog chip. Its small-signal characteristics and slew rate together determine the settling speed of the amplifier-based analog circuit, and thus the high-frequency characteristics of the analog chip.

[0004] Traditional fully differential operational transconductance amplifiers, such as Figure 1 As shown, its principle is to generate high gain through two-stage amplification. The first stage mainly converts the voltage signal into a current signal through the input transistor pair and restores the amplified voltage signal across the load. The second stage mainly achieves large-swing voltage amplification through a common-source structure. However, the traditional structure, due to the use of a fixed tail current source, has a severely limited slew rate, resulting in unsatisfactory large-signal speed and slow overall settling time, which cannot meet the needs of high-speed applications. In addition, the fixed current bias structure at the output end has low current utilization, resulting in low energy efficiency, insufficient small-signal performance, and increased overall power consumption. Summary of the Invention

[0005] To address the problems of low efficiency and low slew rate in traditional fully differential operational transconductance amplifiers, this invention proposes a high-efficiency, slew rate-enhanced fully differential operational transconductance amplifier, such as... Figure 2 As shown. This invention employs a signal follower circuit with partial negative feedback, effectively reducing output impedance and ensuring effective tracking of the input signal even under significant load current variations. Simultaneously, connecting the output terminals of the signal follower circuit—the sources of the third NMOS transistor M3 and the fourth NMOS transistor M4—to the sources of the input pair transistors amplifies the signal amplitude between the gate and source of the input transistors. Furthermore, under large signal conditions, this increases the current-to-voltage conversion ratio to four times that of the traditional structure, eliminating the limitation of a fixed tail current. Additionally, the first-stage amplifier load utilizes partial positive feedback to achieve negative resistance characteristics, significantly increasing the slew rate of this node and thus achieving a high slew rate in the output stage under low power consumption, improving overall efficiency. The MOS transistors in this invention are biased in the subthreshold region, further enhancing efficiency.

[0006] In addition, to address the issue of low output stage efficiency in traditional fully differential operational transconductance amplifiers, this invention introduces an AC signal coupling circuit to improve the current utilization of the output stage; and proposes a complementary gate-source short-circuit MOS transistor structure to ensure high impedance even with a large internal node swing, thereby maintaining good AC coupling characteristics under large swing and improving small-signal performance.

[0007] The technical solution of this invention is:

[0008] A high-efficiency slew rate enhanced fully differential operational transconductance amplifier includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth PMOS transistor M19, a twentieth NMOS transistor M20, a twenty-first NMOS transistor M21, and a twenty-second NMOS transistor M22; a first resistor R1; a second resistor R2; a first capacitor C1; a second capacitor C2; a first current source I1; a second current source I2; a third current source I3; and a fourth current source I4.

[0009] The gate of the first NMOS transistor M1 is connected to the gate of the third NMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the gate of the fourth NMOS transistor M4; the gate of the fifth NMOS transistor M5 is connected to the drain of the third NMOS transistor M3 and the negative terminal of the first current source I1; the gate of the sixth NMOS transistor M6 is connected to the drain of the fourth NMOS transistor M4 and the negative terminal of the second current source I2; the gate of the seventh NMOS transistor M7 is connected to the source of the fifth NMOS transistor M5 and the positive terminal of the third current source I3; the gate of the eighth NMOS transistor M8 is connected to the source of the sixth NMOS transistor M6 and the positive terminal of the fourth current source I4; the gate of the ninth PMOS transistor M9 is connected to the drain of the second NMOS transistor M2, the drain of the tenth PMOS transistor M10, the drain of the twelfth PMOS transistor M12, the gate of the fourteenth PMOS transistor M14, one end of the second capacitor C2, and one end of the second resistor R2; the gate of the tenth PMOS transistor M10 is connected to the drain of the first NMOS transistor M1 and the gate of the ninth PMOS transistor M9. The drain of M9, the drain of the eleventh PMOS transistor M11, the gate of the thirteenth PMOS transistor M13, one end of the first capacitor C1, and one end of the first resistor R1; the gate of the eleventh PMOS transistor M11 is connected to the gate of the twelfth PMOS transistor M12, the other end of the first resistor R1, and the other end of the second resistor R2; the gate of the fifteenth NMOS transistor M15 is connected to the other end of the first capacitor C1, the source of the seventeenth NMOS transistor M17, and the drain of the seventeenth NMOS transistor M17; the sixteenth... The gate of NMOS transistor M16 is connected to the other end of the second capacitor C2, the source of the eighteenth PMOS transistor M18, and the gate of the eighteenth PMOS transistor M18; the gate of the nineteenth PMOS transistor M19 is connected to the source of the nineteenth PMOS transistor M19, the gate of the twentieth NMOS transistor M20, and the source of the twentieth NMOS transistor M20; the gate of the twenty-first NMOS transistor M21 is connected to the bias voltage Vcmfb, and the gate of the twenty-second NMOS transistor M22 is connected to the bias voltage Vcmfb.

[0010] The source of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2, the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, the drain of the seventh NMOS transistor M7, and the drain of the eighth NMOS transistor M8; the sources of the seventh NMOS transistor M7, the eighth NMOS transistor M8, the fifteenth NMOS transistor M15, the sixteenth NMOS transistor M16, the twenty-first NMOS transistor M21, and the twenty-second NMOS transistor M22 are all connected to ground; the sources of the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, and the fourteenth PMOS transistor M14 are all connected to the power supply;

[0011] The drains of the fifth NMOS transistor M5 and the sixth MOS transistor M6 are both connected to the power supply; the drain of the thirteenth PMOS transistor M13 is connected to the drain of the fifteenth NMOS transistor M15 and the drain of the twenty-first NMOS transistor M21; the drain of the fourteenth PMOS transistor M14 is connected to the drain of the sixteenth NMOS transistor M16 and the drain of the twenty-second NMOS transistor M22; the drain of the seventeenth NMOS transistor M17 is connected to the drain of the nineteenth PMOS transistor M19; and the drain of the eighteenth PMOS transistor M18 is connected to the drain of the twentieth NMOS transistor M20.

[0012] The beneficial effects of this invention are as follows:

[0013] This invention employs a signal follower circuit with partial negative feedback, effectively reducing output impedance and ensuring effective tracking of the input signal even under significant load current variations. Simultaneously, the output terminals of the signal follower circuit—namely, the sources of the third NMOS transistor M3 and the fourth NMOS transistor M4—are connected to the sources of the input transistor pair. This amplifies the signal amplitude between the gate and source of the input transistors and, under large signal conditions, increases the current-to-voltage conversion ratio to four times that of traditional structures, eliminating the limitation of a fixed tail current. Furthermore, the first-stage amplifier load utilizes partial positive feedback to achieve negative resistance characteristics, and a fixed resistor is introduced to ensure that the first-stage output node maintains a large impedance even with large swing amplitudes. This significantly increases the swing amplitude of the node, thereby achieving a high slew rate characteristic with low power consumption and improving overall efficiency.

[0014] Furthermore, this invention introduces an AC signal coupling circuit, improving the current utilization of the output stage. It also proposes a complementary gate-source short-circuit MOS transistor structure to ensure high impedance even with large internal node swings, thereby providing good AC coupling characteristics under large swings, improving small-signal performance, and accelerating circuit setup.

[0015] The MOS transistor in this invention is biased in the subthreshold region, which further improves efficiency. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0017] Figure 1 This is a schematic diagram of the circuit structure of a traditional fully differential operational transconductance amplifier.

[0018] Figure 2 This is a schematic diagram of the specific circuit structure of a high-efficiency slew rate enhanced fully differential operational transconductance amplifier proposed in this invention in an embodiment.

[0019] Figure 3 This is a schematic diagram showing a simulation comparison of the settling time and slew rate of the high-efficiency slew rate enhanced fully differential operational transconductance amplifier of the present invention and a traditional fully differential operational transconductance amplifier. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0021] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. For example, "first connection terminal" and "second connection terminal" of a capacitor and resistor simply refer to two connection terminals of the capacitor and resistor, and the first connection terminal and the second connection terminal can be interchanged.

[0022] like Figure 2 As shown, this invention proposes a high-efficiency slew rate enhanced fully differential operational transconductance amplifier, comprising a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth PMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth PMOS transistor M19, a twentieth NMOS transistor M20, a twenty-first NMOS transistor M21, a twenty-second NMOS transistor M22, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first current source I1, a second current source I2, a third current source I3, and a fourth current source I4.

[0023] The gate of the first NMOS transistor M1 is connected to the gate of the third NMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the gate of the fourth NMOS transistor M4; the gate of the fifth NMOS transistor M5 is connected to the drain of the third NMOS transistor M3 and the negative terminal of the first current source I1; the gate of the sixth NMOS transistor M6 is connected to the drain of the fourth NMOS transistor M4 and the negative terminal of the second current source I2; the gate of the seventh NMOS transistor M7 is connected to the source of the fifth NMOS transistor M5 and the positive terminal of the third current source I3; the gate of the eighth NMOS transistor M8 is connected to the source of the sixth NMOS transistor M6 and the positive terminal of the fourth current source I4; the gate of the ninth PMOS transistor M9 is connected to the drain of the second NMOS transistor M2, the drain of the tenth PMOS transistor M10, the drain of the twelfth PMOS transistor M12, the gate of the fourteenth PMOS transistor M14, one end of the second capacitor C2, and one end of the second resistor R2; the gate of the tenth PMOS transistor M10 is connected to the drain of the first NMOS transistor M1 and the gate of the ninth PMOS transistor M9. The drain of transistor M9, the drain of the eleventh PMOS transistor M11, the gate of the thirteenth PMOS transistor M13, one end of the first capacitor C1, and one end of the first resistor R1 are connected. The gate of the eleventh PMOS transistor M11 is connected to the gate of the twelfth PMOS transistor M12, the other end of resistor R1, and the other end of resistor R2. The gate of the fifteenth NMOS transistor M15 is connected to the other end of the first capacitor C1, the source of the seventeenth NMOS transistor M17, and the drain of the seventeenth NMOS transistor M17. The sixteenth NMOS transistor M15... The gate of OS transistor M16 is connected to the other end of the second capacitor C2, the source of the eighteenth PMOS transistor M18, and the gate of the eighteenth PMOS transistor M18. The gate of the nineteenth PMOS transistor M19 is connected to the source of the nineteenth PMOS transistor M19, the gate of the twentieth NMOS transistor M20, and the source of the twentieth NMOS transistor M20. The gate of the twenty-first NMOS transistor M21 is connected to the bias voltage Vcmfb. The gate of the twenty-second NMOS transistor M22 is connected to the bias voltage Vcmfb.

[0024] The source of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2, the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, the drain of the seventh NMOS transistor M7, and the drain of the eighth NMOS transistor M8. The sources of the seventh NMOS transistor M7, the eighth NMOS transistor M8, the fifteenth NMOS transistor M15, the sixteenth NMOS transistor M16, the twenty-first NMOS transistor M21, and the twenty-second NMOS transistor M22 are all connected to ground. The sources of the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, and the fourteenth PMOS transistor M14 are all connected to ground.

[0025] The drains of the fifth NMOS transistor M5 and the sixth MOS transistor M6 are both connected to the power supply. The drain of the thirteenth PMOS transistor M13 is connected to the drain of the fifteenth NMOS transistor M15 and the drain of the twenty-first NMOS transistor M21. The drain of the fourteenth PMOS transistor M14 is connected to the drain of the sixteenth NMOS transistor M16 and the drain of the twenty-second NMOS transistor M22. The drain of the seventeenth NMOS transistor M17 is connected to the drain of the nineteenth PMOS transistor M19. The drain of the eighteenth PMOS transistor M18 is connected to the drain of the twentieth NMOS transistor M20.

[0026] The cutoff frequency of the AC signal coupling circuit formed by the first capacitor C1, the seventeenth NMOS transistor M17, and the nineteenth PMOS transistor M19 is half of the open-loop GBW of the main amplifier.

[0027] The cutoff frequency of the AC signal coupling circuit formed by the second capacitor C2, the eighteenth PMOS transistor M18, and the twentieth NMOS transistor M20 is half of the open-loop GBW of the main amplifier.

[0028] This invention employs a signal follower circuit with local negative feedback, which effectively reduces the output impedance and ensures effective tracking of the input signal even when the load current changes significantly.

[0029] The present invention connects the output terminal of the signal follower circuit, namely the source of the third NMOS transistor M3 and the source of the fourth NMOS transistor M4, to the source of the input pair transistors, thereby expanding the signal amplitude between the gate and source of the input transistors and increasing the current-to-voltage conversion ratio to four times that of the traditional structure under large signal conditions, no longer being limited by the fixed tail current.

[0030] The first-stage amplifier load uses local positive feedback to achieve negative resistance characteristics, and a fixed resistor is introduced to ensure that the first-stage output node still has a large impedance under large swing, which greatly increases the swing amplitude of the node, thereby achieving a large slew rate characteristic under low power consumption and improving overall efficiency.

[0031] This invention introduces an AC signal coupling circuit, improving the current utilization of the output stage. Furthermore, it proposes a complementary gate-source short-circuit MOS transistor structure to ensure high impedance even with large internal junction swings, thereby providing excellent AC coupling characteristics under large swings, improving small-signal performance, and accelerating circuit setup.

[0032] The MOS transistor in this invention is biased in the subthreshold region, which further improves efficiency.

[0033] See Figure 3As shown, the dashed line represents the settling curve of the conventional operational transconductance amplifier, while the solid line represents the settling curve of the operational transconductance amplifier of this invention. Simulation results show that the conventional operational transconductance amplifier has a very slow settling time, approximately 140µs, with a slew rate (SR) of 9kV / s. Furthermore, achieving the slew rate of this invention requires extremely high power consumption with the conventional structure. In the example of this invention, the settling time is significantly reduced compared to the conventional structure, completing the settling within approximately 30µs, with a slew rate of approximately 7mV / s. Compared to the conventional structure, this invention greatly reduces circuit power consumption and improves efficiency.

[0034] Furthermore, under the conditions of a differential input signal swing of 350mV, a power supply voltage of 1.5V, and a load of 100pF, the characteristics of the two structures are as follows: the conventional operational transconductance amplifier consumes 1.62uA of current, has a GBW of 19kHz, a PM of 89deg, an open-loop gain of 32dB, a slew rate of 9.14kV / s, a large-signal efficiency (FOML) of 0.376, and a small-signal efficiency (FOMS) of 0.78; while the high-efficiency slew rate enhanced fully differential operational transconductance amplifier of this invention consumes 1.039uA of current, has a GBW of 24kHz, a PM of 89deg, an open-loop gain of 42dB, a slew rate of 7.1MV / s, a large-signal efficiency (FOML) of 455.6, and a small-signal efficiency (FOMS) of 1.54.

[0035] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-efficiency slew rate enhanced fully differential operational transconductance amplifier, characterized in that, It includes the following transistors: first NMOS transistor M1, second NMOS transistor M2, third NMOS transistor M3, fourth NMOS transistor M4, fifth NMOS transistor M5, sixth NMOS transistor M6, seventh NMOS transistor M7, eighth NMOS transistor M8, ninth PMOS transistor M9, tenth PMOS transistor M10, eleventh PMOS transistor M11, twelfth PMOS transistor M12, thirteenth PMOS transistor M13, fourteenth PMOS transistor M14, fifteenth NMOS transistor M15, sixteenth NMOS transistor M16, seventeenth NMOS transistor M17, eighteenth PMOS transistor M18, nineteenth PMOS transistor M19, twentieth NMOS transistor M20, twenty-first NMOS transistor M21, twenty-second NMOS transistor M22; first resistor R1; second resistor R2; first capacitor C1; second capacitor C2; first current source I1; second current source I2; third current source I3; and fourth current source I4. The gate of the first NMOS transistor M1 is connected to the gate of the third NMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the gate of the fourth NMOS transistor M4; the gate of the fifth NMOS transistor M5 is connected to the drain of the third NMOS transistor M3 and the negative terminal of the first current source I1; the gate of the sixth NMOS transistor M6 is connected to the drain of the fourth NMOS transistor M4 and the negative terminal of the second current source I2; the gate of the seventh NMOS transistor M7 is connected to the source of the fifth NMOS transistor M5 and the positive terminal of the third current source I3; the gate of the eighth NMOS transistor M8 is connected to the source of the sixth NMOS transistor M6 and the positive terminal of the fourth current source I4; the gate of the ninth PMOS transistor M9 is connected to the drain of the second NMOS transistor M2, the drain of the tenth PMOS transistor M10, the drain of the twelfth PMOS transistor M12, the gate of the fourteenth PMOS transistor M14, one end of the second capacitor C2, and one end of the second resistor R2; the tenth PMOS transistor... The gate of transistor M10 is connected to the drain of the first NMOS transistor M1, the drain of the ninth PMOS transistor M9, the drain of the eleventh PMOS transistor M11, the gate of the thirteenth PMOS transistor M13, one end of the first capacitor C1, and one end of the first resistor R1; the gate of the eleventh PMOS transistor M11 is connected to the gate of the twelfth PMOS transistor M12, the other end of the first resistor R1, and the other end of the second resistor R2; the gate of the fifteenth NMOS transistor M15 is connected to the other end of the first capacitor C1, the source of the seventeenth NMOS transistor M17, and the gate of the seventeenth NMOS transistor M17; the gate of the sixteenth NMOS transistor M16 is connected to the other end of the second capacitor C2, the source of the eighteenth PMOS transistor M18, and the gate of the eighteenth PMOS transistor M18; the gate of the nineteenth PMOS transistor M19 is connected to the source of the nineteenth PMOS transistor M19, the gate of the twentieth NMOS transistor M20, and the source of the twentieth NMOS transistor M20. The gate connection bias voltage Vcmfb of the 21st NMOS transistor M21, and the gate connection bias voltage Vcmfb of the 22nd NMOS transistor M22; The source of the first NMOS transistor M1 is connected to the source of the second NMOS transistor M2, the source of the third NMOS transistor M3, the source of the fourth NMOS transistor M4, the drain of the seventh NMOS transistor M7, and the drain of the eighth NMOS transistor M8; the sources of the seventh NMOS transistor M7, the eighth NMOS transistor M8, the fifteenth NMOS transistor M15, the sixteenth NMOS transistor M16, the twenty-first NMOS transistor M21, and the twenty-second NMOS transistor M22 are all connected to ground; the sources of the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth PMOS transistor M13, and the fourteenth PMOS transistor M14 are all connected to the power supply; The drains of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are both connected to the power supply; the drain of the thirteenth PMOS transistor M13 is connected to the drain of the fifteenth NMOS transistor M15 and the drain of the twenty-first NMOS transistor M21; the drain of the fourteenth PMOS transistor M14 is connected to the drain of the sixteenth NMOS transistor M16 and the drain of the twenty-second NMOS transistor M22; the drain of the seventeenth NMOS transistor M17 is connected to the drain of the nineteenth PMOS transistor M19; and the drain of the eighteenth PMOS transistor M18 is connected to the drain of the twentieth NMOS transistor M20.

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