Analog-to-digital converter calibration system and method

Abstract

The present invention provides techniques for facilitating calibration of an analog-to-digital converter. In one example, a method includes, for each of a plurality of time instances, generating a first ramp signal that begins at the time instance relative to a corresponding start of a first counter signal, and generating a corresponding comparator output signal based on the first ramp signal and a first threshold signal. The method also includes capturing a corresponding first value of the first ramp signal in response to a transition of the corresponding comparator output signal. The method also includes determining a corresponding second counter value of a second counter signal based on the corresponding first value. The method also includes determining a scaling factor based on the second counter value and the time instance. Each first value is associated with the same counter value of the first counter signal. Related devices and systems are also provided.

Description

Technical Field

[0001] One or more embodiments relate generally to analog-to-digital conversion and, more particularly, for example, to analog-to-digital converter calibration systems and methods. Background Art

[0002] An imaging system can include an array of detectors arranged in rows and columns, with each detector acting as a pixel to generate a portion of a two-dimensional image. For example, a single detector in the detector array captures an associated pixel value. There are a variety of image detectors, such as visible light image detectors, infrared image detectors, or other types of image detectors that can be arranged in an image detector array for capturing images. As an example, multiple sensors can be arranged in an image detector array to detect electromagnetic (EM) radiation of a desired wavelength. In some cases, such as for infrared imaging, readout of image data captured by the detectors can be performed in a time-division multiplexed manner by a readout integrated circuit (ROIC). The readout image data can be transmitted to other circuits, such as for processing, storage, and / or display. In some cases, the combination of the detector array and the ROIC can be referred to as a focal plane array (FPA). Advances in FPA and image processing process technology have led to increased capabilities and complexity of the resulting imaging systems. Summary of the Invention

[0003] In one or more embodiments, a method includes, for each time instance of a plurality of time instances, generating a first ramp signal that starts at the time instance relative to a corresponding start of a first counter signal; generating a corresponding comparator output signal based on the first ramp signal and a first threshold signal, wherein the corresponding comparator output signal is associated with a first state or a second state; capturing a corresponding first value of the first ramp signal in response to a transition of the corresponding comparator output signal from the first state to the second state; and determining a corresponding second counter value of a second counter signal based on the corresponding first value. The method further includes determining a scaling factor based on the second counter value and the plurality of time instances. Each of the first values ​​is associated with the same counter value of the first counter signal.

[0004] In one or more embodiments, a system includes an analog-to-digital converter and a logic device. The analog-to-digital converter is configured to, for each time instance of a plurality of time instances: generate a first ramp signal that starts at the time instance relative to a corresponding start of a first counter signal; generate a corresponding comparator output signal based on the first ramp signal and a first threshold signal, wherein the corresponding comparator output signal is associated with a first state or a second state; capture a corresponding first value of the first ramp signal in response to a transition of the corresponding comparator output signal from the first state to the second state; and determine a corresponding second counter value of a second counter signal based on the corresponding first value. The logic device is configured to determine a scaling factor based on the second counter value and the plurality of time instances. Each of the first values ​​is associated with the same counter value of the first counter signal.

[0005] The scope of the present disclosure is defined by the claims, which are incorporated herein by reference. By considering the following detailed description of one or more embodiments, those skilled in the art will gain a more complete understanding of the embodiments of the present disclosure, as well as realize additional advantages thereof. Reference will be made to the accompanying drawings, which will first be briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of an example imaging system is shown, in accordance with one or more embodiments of the present disclosure.

[0007] Figure 2 A block diagram of an example image sensor assembly is shown, in accordance with one or more embodiments of the present disclosure.

[0008] Figure 3 A block diagram of an example analog-to-digital converter and associated image sensor circuitry is shown, in accordance with one or more embodiments of the present disclosure.

[0009] Figure 4 and 5 Each shows a graph associated with the operation of an analog-to-digital converter according to one or more embodiments of the present disclosure.

[0010] Figure 6 Signal waveforms associated with the operation of an analog-to-digital converter according to one or more embodiments of the present disclosure are shown.

[0011] Figure 7A A graph is shown in accordance with one or more embodiments of the present disclosure, wherein a first ramp is initiated at a different time relative to a counter to facilitate analog-to-digital converter calibration.

[0012] Figure 7B The present invention shows one or more embodiments of the present invention. Figure 7A Another representation of the graph of .

[0013] Figure 8 Shown is a graph with example calibration data for determining calibration factors according to one or more embodiments of the present disclosure.

[0014] Figure 9 A graph is shown in which a best linear fit is determined based on calibration data, in accordance with one or more embodiments of the present disclosure.

[0015] Figure 10 A graph is shown in which a non-linear curve is determined based on calibration data, according to one or more embodiments of the present disclosure.

[0016] Figure 11 A flow chart illustrating an example process for facilitating calibration of an analog-to-digital converter according to one or more embodiments of the present disclosure is shown.

[0017] Figure 12 A flow chart illustrating an example process for applying a calibration factor according to one or more embodiments of the present disclosure is shown.

[0018] The embodiments of the present disclosure and their advantages are best understood by reference to the following detailed description. It should be noted that the sizes of the various components and the distances between these components are not drawn to scale in the drawings. It should be understood that similar reference numerals are used to identify similar elements shown in one or more figures. DETAILED DESCRIPTION

[0019] The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configuration in which the subject technology can be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for providing a thorough understanding of the subject technology. However, it will be clear and obvious to those skilled in the art that the subject technology is not limited to the specific details set forth herein and can be practiced using one or more embodiments. In one or more instances, structures and components are shown in block diagram form to avoid confusing the concept of the subject technology. One or more embodiments disclosed in this subject are illustrated by one or more drawings and / or described in conjunction with one or more drawings and are set forth in the claims.

[0020] Various systems and methods are provided for facilitating calibration of an analog-to-digital converter (ADC). The ADC may include an integrator, a comparator, a counter circuit, and a memory device. The ADC may receive an analog signal and generate a digital representation of the analog signal. In some cases, the analog signal may include a detector signal (e.g., a detector voltage, a detector current) generated by a detector of an imaging system in response to incident EM radiation. Each comparator may generate a comparator output signal based on a reference signal and a comparator input signal associated with a corresponding detector signal (e.g., a corresponding detector from a detector array). In some cases, the comparator input signal may be a signal output by the integrator. The reference signal may be generated by a reference generator. In some cases, the reference signal may be a fixed signal (e.g., a fixed voltage level). In one aspect, the integrated output signal of the integrator may ramp (e.g., up or down), while synchronously, the counter circuit begins adjusting (e.g., incrementing) a counter value (e.g., also referred to as a digital count value or simply a count value). The comparator output signal may be associated with a first state or a second state. For example, the comparator output signal may be associated with a first state when the reference signal does not exceed the integrator output signal and a second state when the reference signal exceeds the integrator output signal, or vice versa.

[0021] In some embodiments, an ADC may be provided in an imaging system (e.g., an infrared imaging system). The imaging system may include an ADC, a detector array, and readout circuitry. In some cases, the ADC may be implemented as part of the detector array or the readout circuitry. The imaging system may be configured to capture infrared image data associated with a scene using an image sensor device (e.g., a detector array of an FPA). The image sensor device includes detectors (e.g., also referred to as detector pixels, detector elements, or simply pixels). Each detector pixel may detect incident EM radiation and generate infrared image data indicative of the detected EM radiation of the scene. In some cases, the image sensor array is configured to detect infrared radiation (e.g., thermal infrared radiation). For a pixel of an infrared image (e.g., a thermal infrared image), each output value of the pixel may represent / provide and / or correspond to a temperature, a digital count value, a percentage of a full temperature range, or generally any value that can be mapped to a temperature. For example, a digital count value of 13,000 output by a pixel may represent a temperature of 160°C. Thus, the captured infrared image data may indicate or be used to determine the temperature of objects, people, and / or other features / aspects in the scene.

[0022] In some embodiments, the ADC is a multi-range ADC. In some aspects, the multi-range ADC can facilitate fast conversion of analog input signals. The quality factor of the ADC may include monotonicity and differential nonlinearity (DNL) without missing or redundant codes. Appropriate calibration can be performed to allow multiple ranges to be combined with accuracy so that the final / combined ADC output is monotonic and without any missing codes. A monotonic code without missing codes can have a DNL between -1 and +1. In some cases, calibration can be performed off-chip of the ADC. Calibration can be performed to account for errors associated with the slopes used by the ADC to convert the analog input signals. Such errors can be associated with mismatches (e.g., gain factor mismatches) between the first and second slopes of a given column of the detector array and / or between different columns of the detector array.

[0023] In a dual-slope ADC (e.g., also known as a dual-slope ADC), a first ramp can be swept across a signal range to determine a first set of bits (e.g., most significant bits (MSBs)) of a digital representation of an analog signal, and then a second ramp can be swept across to determine a second set of bits (e.g., least significant bits (LSBs)) of the digital representation. Note that each of the first and second ramps can be a linear ramp or a nonlinear ramp. If the slopes of the two ramps do not match (e.g., the first ramp and / or the second ramp are not at their respective predetermined values), non-monotonicity (e.g., missing codes) may occur.

[0024] In some embodiments, a calibration can be performed on the dual slope ADC to determine a scaling factor (e.g., also referred to as a calibration factor) to be applied to the count value (e.g., corresponding to the MSB) to correct for a mismatch (e.g., a gain mismatch) between the first slope and the second slope. Correcting such a mismatch can avoid redundant or missing codes. The calibration can be based on a relationship between the start of the first slope and the start of the first counter. Depending on the application / implementation, the start of the first slope can be the time when the first slope begins to ramp up or down. Depending on the application / implementation, the start of the first counter can be the time when the first counter begins to increment or decrement. Due to mismatches between the columns of the detector array, a calibration can be performed to determine a corresponding scaling factor for each column.

[0025] As an example of the effects of mismatch, consider a 14-bit dual slope ADC. The 14-bit dual slope ADC can digitize an analog input signal into a 14-bit output, where 5 of the 14 bits form the MSB associated with the digital representation of the analog input signal, and the remaining 9 bits form the LSB associated with the digital representation. The MSB may correspond to the value represented by the MSB. raw The MSB count value is represented by the LSB, and the LSB may correspond to the LSB raw The total value SADC (e.g., also known as ADC conversion value) provides a digital representation of the analog signal and is determined based on the MSB count value and the LSB count value. The nominal scaling factor applied to the MSB count value is 512 because each MSB count has a weight of 512 LSB counts. Therefore, the total value S ADC Can be made by S ADC =MSB raw ×512+LSB raw supply.

[0026] In some aspects, the LSB has an extra bit for redundancy (e.g., the fifteenth bit of the ADC output) to account for errors associated with the first ramp and / or the second ramp and / or errors between the two ramps (e.g., mismatch). For example, if the slope of the second ramp is 10% lower than the nominal / expected slope of the second ramp (e.g., the slope that the second ramp is designed to have), then each LSB count substantially covers a step size that is smaller than the expected slope of the second ramp. In this regard, instead of the second ramp covering 512 counts (e.g., from nine bits), the second ramp can instead cover 512×1.1=563 counts. This value of 563, which is greater than 512, is achievable because the LSB has an extra bit for redundancy, allowing a total raw LSB output of up to 1024. With the value 563 and equation S ADC =MSB raw ×512+LSB raw Redundant counting may occur if, for example, the MSB raw =0 and LSB raw =563 or MSB raw =1 and LSB raw =51. MSB raw and LSB raw Both of these combinations result in the MSB of raw ×512+LSB raw =S ADC , the same count value is 563.

[0027] Calibration can be performed to determine the MSB raw The scaling factor is 564 (e.g., instead of the nominal 512). With this calibration, the total value can be represented by the MSB raw ×564+LSB raw Provided by MSB raw =0 and LSB raw =563, the total value is 563. raw =1 and LSB raw =51, the total value is 615. Therefore, the MSB raw and LSBraw As another example, if the MSB is counted when the MSB raw LSB counts LSB when converted to 1 raw =0, the total value is 564, so there is no redundant or missing code.

[0028] Calibration using the methods and systems disclosed herein can be used in conjunction with devices and systems such as infrared imaging systems, visible light imaging systems, imaging systems with visible and infrared imaging capabilities, shortwave infrared (SWIR) imaging systems, light detection and ranging (LIDAR) imaging systems, radar detection and ranging (RADAR) imaging systems, millimeter wave (MMW) imaging systems, ultrasound imaging systems, x-ray imaging systems, microscopy systems, mobile digital cameras, video surveillance systems, video processing systems, or other systems or devices that may need to obtain image data in one or more portions of the EM spectrum. Furthermore, in some embodiments, such calibration can generally be used in any device or system that includes an ADC for digitizing analog signals.

[0029] Referring now to the accompanying drawings, Figure 1 A block diagram of an example imaging system 100 is shown, according to one or more embodiments of the present disclosure. However, not all depicted components are required, and one or more embodiments may include additional components not shown. The arrangement and types of components may be changed without departing from the spirit or scope of the claims as described herein. Additional components, different components, and / or fewer components may be provided.

[0030] According to embodiments of the present disclosure, an imaging system 100 may be used to capture and process images. The imaging system 100 may represent any type of imaging system that detects one or more ranges (e.g., bands) of EM radiation and provides representative data (e.g., one or more still image frames or video image frames). The imaging system 100 may include an imaging device 105. As non-limiting examples, the imaging device 105 may be or may include: an infrared camera, a visible light camera, a tablet computer, a laptop computer, a personal digital assistant (PDA), a mobile device, a desktop computer, or other electronic device, or a portion thereof. The imaging device 105 may include a housing (e.g., a camera body) that at least partially surrounds the components of the imaging device 105, for example, to facilitate compactness and protection of the imaging device 105. For example, Figure 1 The solid line frame marked as 105 in FIG. 1 may represent the housing of the imaging device 105. The housing may include Figure 1, and / or different components of the imaging device 105 are depicted within the solid box in FIG. In embodiments, the imaging system 100 may include a portable device and may be incorporated into, for example, a vehicle or non-mobile device where images need to be stored and / or displayed. The vehicle may be a land-based vehicle (e.g., a car, truck), a sea-based vehicle, an aircraft (e.g., an unmanned aerial vehicle (UAV)), a space vehicle, or generally any type of vehicle that can incorporate (e.g., be mounted within, mounted on, etc.) the imaging system 100. In another example, the imaging system 100 can be coupled to various types of fixed locations (e.g., a home security installation, a campsite or outdoor installation, or other locations) via one or more types of mounts.

[0031] According to one embodiment, the imaging device 105 includes a logic device 110, a memory component 115, an image capture component 120 (e.g., an imager, an image sensor device), an image interface 125, a control component 130, a display component 135, a sensing component 140, and / or a network interface 145. According to various embodiments, the logic device 110 includes one or more of the following: a processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a single-core processor, a multi-core processor, a microcontroller, a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)), an application specific integrated circuit (ASIC), a digital signal processing (DSP) device, or other logic device, one or more memories and / or processing devices for storing executable instructions (e.g., software, firmware, or other instructions), and / or any other suitable combination of processing devices and / or memories for executing instructions to perform any of the various operations described herein. The logic device 110 can be configured by hardwiring, executing software instructions, or a combination of both to perform the various operations discussed herein for embodiments of the present disclosure. Logic device 110 can be configured to interface with and communicate with various other components of imaging system 100 (e.g., 115, 120, 125, 130, 135, 140, 145, etc.) to perform such operations. In one aspect, logic device 110 can be configured to perform various system control operations (e.g., to control the communication and operation of various components of imaging system 100) and other image processing operations (e.g., debayering, sharpening, color correction, offset correction, bad pixel replacement, data conversion, data transformation, data compression, video analysis, etc.). In one embodiment, logic device 110 can determine a scaling factor (e.g., also referred to as a calibration factor) for application to an ADC.

[0032] In one embodiment, memory component 115 includes one or more memory devices configured to store data and information, including infrared image data and information. Memory component 115 may include one or more different types of memory devices, including volatile and non-volatile memory devices, such as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile random access memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, a hard drive, and / or other types of memory. As described above, logic device 110 may be configured to execute software instructions stored in memory component 115 to perform method and process steps and / or operations. Logic device 110 and / or image interface 125 may be configured to store images or digital image data captured by image capture component 120 in memory component 115. In some embodiments, memory component 115 may store count values ​​(e.g., MSB count values, LSB count values), scaling factors, and / or other data related to ADC calibration.

[0033] In some embodiments, a separate machine-readable medium 150 (e.g., a memory such as a hard drive, compact disk, digital video disk, or flash memory) can store software instructions and / or configuration data that can be executed or accessed by a computer (e.g., a logic device or processor-based system) to perform various methods and operations, such as those associated with processing image data. In one aspect, the machine-readable medium 150 can be portable and / or located separately from the imaging device 105, with the stored software instructions and / or data provided to the imaging device 105 by coupling the machine-readable medium 150 to the imaging device 105 and / or by the imaging device 105 downloading the stored software instructions and / or data from the machine-readable medium 150 (e.g., via a wired link and / or a wireless link). It should be understood that the various modules can be integrated in software and / or hardware as part of the logic device 110, wherein the code for the modules (e.g., software or configuration data) is stored, for example, in the memory component 115.

[0034] The imaging device 105 may be a video and / or still camera for capturing and processing images and / or video of a scene 175. In this regard, the image capture component 120 of the imaging device 105 may be configured to capture images (e.g., still and / or video images) of the scene 175 in a particular spectrum or modality. The image capture component 120 includes image detector circuitry 165 (e.g., visible light detector circuitry, thermal infrared detector circuitry) and readout circuitry 170 (e.g., ROIC). For example, the image capture component 120 may include an IR imaging sensor (e.g., an IR imaging sensor array) configured to detect IR radiation in the near, mid, and / or far IR spectrum and provide an IR image (e.g., IR image data or signal) representative of the IR radiation from the scene 175. For example, the image detector circuitry 165 may capture (e.g., detect, sense) IR radiation having a wavelength ranging from approximately 700 nm to approximately 2 mm, or a portion thereof. For example, in some aspects, image detector circuit 165 can be sensitive to (e.g., better detect) SWIR radiation, mid-wave IR (MWIR) radiation (e.g., EM radiation having a wavelength of 2 μm to 5 μm), and / or long-wave IR (LWIR) radiation (e.g., EM radiation having a wavelength of 7 μm to 14 μm), or any desired IR wavelength (e.g., typically in the range of 0.7 μm to 14 μm). In other aspects, image detector circuit 165 can capture radiation from one or more other bands of EM frequencies (e.g., visible light, ultraviolet light, etc.).

[0035] Image detector circuitry 165 can capture image data (e.g., infrared image data) associated with scene 175. To capture a detector output image, image detector circuitry 165 can detect image data (e.g., in the form of EM radiation) of scene 175 received through aperture 180 of imaging device 105 and generate pixel values ​​for an image based on scene 175. An image can be referred to as a frame or image frame. In some cases, image detector circuitry 165 can include a detector array (e.g., also referred to as a pixel array) that can detect radiation of a particular wavelength band, convert the detected radiation into an electrical signal (e.g., a voltage, current, etc.), and generate pixel values ​​based on the electrical signals. Each detector in the array can capture a corresponding portion of the image data and generate a pixel value based on the corresponding portion captured by the detector. The pixel values ​​generated by the detector can be referred to as the detector output. As non-limiting examples, each detector can be a photodetector, such as an avalanche photodiode, an infrared photodetector, a quantum well infrared photodetector, a microbolometer, or other detector capable of converting EM radiation (e.g., of a particular wavelength) into pixel values. The detector array can be arranged in rows and columns.

[0036] The detector output image can be, or can be considered to be, a data structure that includes pixels and is a representation of image data associated with scene 175, wherein each pixel has a pixel value representing EM radiation emitted or reflected from a portion of scene 175 and received by a detector that generates the pixel value. Depending on the context, a pixel can refer to a detector of image detector circuit 165 that generates the associated pixel value, or a pixel (e.g., pixel position, pixel coordinates) of a detector output image formed by the generated pixel value. In one example, the detector output image can be an infrared image (e.g., a thermal infrared image). For a thermal infrared image (e.g., also referred to as a thermal image), each pixel value of the thermal infrared image can represent the temperature of the corresponding portion of scene 175. In another example, the detector output image can be a visible light image.

[0037] In one aspect, the pixel value generated by the image detector circuit 165 can be represented based on a digital count value generated based on an electrical signal obtained from converting the detected radiation. For example, where the image detector circuit 165 includes or is otherwise coupled to an ADC circuit, the ADC circuit can generate a digital count value based on the electrical signal. In some embodiments, the ADC circuit can be a multi-range ADC circuit, such as a dual-slope ADC circuit. For an ADC circuit that can use 14 bits to represent an electrical signal, the digital count value can range from 0 to 16383. In such a case, the pixel value of the detector can be a digital count value output from the ADC circuit. In other cases (e.g., where there is no ADC circuit), the pixel value can be analog in nature, with its value being or indicating the value of the electrical signal. As an example, for infrared imaging, a greater amount of IR radiation incident on and detected by the image detector circuit 165 (e.g., an IR image detector circuit) is associated with a higher digital count value and a higher temperature.

[0038] Readout circuitry 170 may serve as an interface between image detector circuitry 165, which detects image data, and logic device 110, which processes the detected image data read out by readout circuitry 170, wherein the transfer of data from readout circuitry 170 to logic device 110 is facilitated by image interface 125. An image capture frame rate may refer to the rate at which image detector circuitry 165 sequentially detects / outputs images and readout circuitry 170 provides the images to logic device 110 (e.g., images output by the detector per second). Readout circuitry 170 may read out pixel values ​​generated by image detector circuitry 165 based on an integration time (e.g., also referred to as an integration period).

[0039] In various embodiments, the combination of image detector circuit 165 and readout circuit 170 may be, include, or together provide an FPA. In some aspects, image detector circuit 165 may be a thermal image detector circuit including an array of microbolometers, and the combination of image detector circuit 165 and readout circuit 170 may be referred to as a microbolometer FPA. In some cases, the array of microbolometers may be arranged in rows and columns. The microbolometers may detect IR radiation and generate pixel values ​​based on the detected IR radiation. For example, in some cases, the microbolometers may be thermal IR detectors that detect IR radiation in the form of heat energy and generate pixel values ​​based on the amount of heat energy detected. The microbolometers may absorb incident IR radiation and produce a corresponding temperature change in the microbolometer. This temperature change is associated with a corresponding change in the resistance of the microbolometer. With each microbolometer acting as a pixel, a two-dimensional image or pictorial representation of the incident IR radiation may be generated by converting the resistance change of each microbolometer into a time-multiplexed electrical signal. This conversion may be performed by the ROIC. Microbolometer FPAs can include IR detection materials such as amorphous silicon (a-Si), vanadium oxide (VO x ), combinations thereof, and / or other detection materials. In one aspect, for a microbolometer FPA, the integration time can be or can indicate the time interval during which the microbolometer is biased. In this case, a longer integration time can be associated with a higher IR signal gain, but less IR radiation is collected. The IR radiation can be collected by the microbolometer as heat energy.

[0040] In some cases, image capture component 120 may include one or more optical components and / or one or more filters. Optical components may include one or more windows, lenses, mirrors, beam splitters, beam couplers, and / or other components for directing and / or focusing radiation onto image detector circuitry 165. Optical components may include components each formed from a material and appropriately arranged according to desired transmission characteristics (e.g., desired transmission wavelength and / or ray transfer matrix characteristics). Filters may be adapted to pass radiation of certain wavelengths while substantially blocking radiation of other wavelengths. For example, image capture component 120 may be an IR imaging device that includes one or more filters adapted to pass IR radiation of certain wavelengths while substantially blocking IR radiation of other wavelengths (e.g., MWIR filters, thermal IR filters, and narrowband filters). In this example, such filters may be used to customize image capture component 120 to increase sensitivity to a desired band of IR wavelengths. In one aspect, when an IR imaging device is customized to capture thermal IR images, the IR imaging device may be referred to as a thermal imaging device. Other imaging devices, including IR imaging devices customized to capture infrared IR images outside the thermal range, may be referred to as non-thermal imaging devices.

[0041] In one specific, non-limiting example, the image capture component 120 may include an IR imaging sensor of an FPA having a detector responsive to IR radiation including near infrared (NIR), SWIR, MWIR, LWIR, and / or very long wave IR (VLWIR) radiation. In some other embodiments, the image capture component 120 may alternatively or additionally include a complementary metal oxide semiconductor (CMOS) sensor or a charge coupled device (CCD) sensor that may be found in any consumer camera (e.g., a visible light camera).

[0042] In some embodiments, imaging system 100 includes a shutter 185. Shutter 185 can be operated to selectively insert into the optical path between scene 175 and image capture component 120 to expose or block aperture 180. In some cases, shutter 185 can be moved (e.g., slid, rotated, etc.) manually (e.g., by a user of imaging system 100) and / or via an actuator (e.g., controllable by logic device 110 in response to user input or autonomously, such as at the discretion of logic device 110 to perform calibration of imaging device 105). When shutter 185 is out of the optical path to expose aperture 180, electromagnetic radiation from scene 175 can be received by image detector circuitry 165 (e.g., through one or more optical components and / or one or more filters). As a result, image detector circuitry 165 captures an image of scene 175. Shutter 185 can be referred to as being in an open position or simply as open. When shutter 185 is inserted into the optical path to block aperture 180, electromagnetic radiation from scene 175 is blocked from being received by image detector circuitry 165. Thus, image detector circuit 165 captures an image of shutter 185. Shutter 185 can be referred to as being in a closed position or simply as closed. In some cases, shutter 185 can block aperture 180 during the calibration process, wherein shutter 185 can function as a uniform blackbody (e.g., a substantially uniform blackbody). For example, shutter 185 can function as a single temperature source or a substantially single temperature source. In some cases, shutter 185 can be temperature controlled to provide a temperature-controlled uniform blackbody (e.g., presenting a uniform radiation field to image detector circuit 165). For example, in some cases, the surface of shutter 185 imaged by image detector circuit 165 can be achieved by a uniform blackbody coating. In some cases, such as for imaging devices without a shutter or with a damaged shutter or with a replacement for shutter 185, the housing or case of imaging device 105, a lens cover, a covering, a wall of a room, or other suitable object / surface can be used to provide a uniform blackbody (e.g., a substantially uniform blackbody) and / or a single temperature source (e.g., a substantially single temperature source).

[0043] Other imaging sensors that may be included in the image capture component 120 include photon mixer device (PMD) imaging sensors or other time-of-flight (ToF) imaging sensors, LIDAR imaging devices, RADAR imaging devices, millimeter imaging devices, positron emission tomography (PET) scanners, single photon emission computed tomography (SPECT) scanners, ultrasound imaging devices, or other imaging devices operating in a specific modality and / or spectrum. It should be noted that some of these imaging sensors that are configured to capture images in a specific modality and / or spectrum (e.g., infrared spectrum, etc.) are more likely to produce images with low-frequency shadows when compared to, for example, general CMOS-based or CCD-based imaging sensors or other imaging sensors, imaging scanners, or imaging devices of different modalities.

[0044] The image or digital image data corresponding to the image provided by the image capture component 120 can be associated with a corresponding image size (also referred to as pixel size). Image size or pixel size generally refers to the number of pixels in the image, for example, for a two-dimensional image, it can be expressed as width multiplied by height, or in other appropriate ways for the relevant size or shape of the image. Thus, an image having an original resolution can be resized to a smaller size (e.g., having fewer pixel dimensions) to, for example, reduce the cost of processing and analyzing the image. A filter (e.g., a non-uniformity estimate) can be generated based on an analysis of the resized image. The filter can then be resized to the original resolution and size of the image before being applied to the image.

[0045] In some embodiments, the image interface 125 may include appropriate input ports, connectors, switches, and / or circuitry configured to interface with an external device (e.g., remote device 155 and / or other device) to receive images (e.g., digital image data) generated by or otherwise stored at the external device. In one aspect, the image interface 125 may include a serial interface and telemetry lines for providing metadata associated with the image data. The received image or image data may be provided to the logic device 110. In this regard, the received image or image data may be converted into signals or data suitable for processing by the logic device 110. For example, in one embodiment, the image interface 125 may be configured to receive analog video data and convert it into suitable digital data to provide to the logic device 110.

[0046] Image interface 125 may include various standard video ports, which may be connected to a video player, a camera, or other device capable of generating a standard video signal, and may convert the received video signal into digital video / image data suitable for processing by logic device 110. In some embodiments, image interface 125 may also be configured to interface with image capture component 120 and receive images (e.g., image data) from image capture component 120. In other embodiments, image capture component 120 may interface directly with logic device 110.

[0047] In one embodiment, the control component 130 includes a user input and / or interface device, such as a rotatable knob (e.g., a potentiometer), a button, a slider, a keyboard, and / or other device, which is suitable for generating user input control signals. The logic device 110 can be configured to sense control input signals from the user via the control component 130 and respond to any sensed control input signals received therefrom. As generally understood by those skilled in the art, the logic device 110 can be configured to interpret such control input signals as values. In one embodiment, the control component 130 can include a control unit (e.g., a wired or wireless handheld control unit) having buttons suitable for interacting with the user and receiving user input control values. In one embodiment, the buttons and / or other input mechanisms of the control unit can be used to control various functions of the imaging device 105, such as calibration initiation and / or related controls, shutter control, autofocus, menu activation and selection, field of view, brightness, contrast, noise filtering, image enhancement, and / or various other functions.

[0048] In one embodiment, display component 135 comprises an image display device (e.g., a liquid crystal display (LCD)) or various other types of commonly known video displays or monitors. Logic device 110 can be configured to display image data and information on display component 135. Logic device 110 can be configured to retrieve image data and information from memory component 115 and display any retrieved image data and information on display component 135. Display component 135 can include display circuitry that logic device 110 can utilize to display image data and information. Display component 135 can be adapted to receive image data and information directly from image capture component 120, logic device 110, and / or image interface 125, or the image data and information can be transmitted from memory component 115 via logic device 110. In some aspects, control component 130 can be implemented as part of display component 135. For example, a touch screen of imaging device 105 can provide both control component 130 (e.g., for receiving user input via taps and / or other gestures) and display component 135 for imaging device 105.

[0049] In one embodiment, as will be appreciated by those skilled in the art, sensing component 140 includes one or more sensors of various types, depending on the application or implementation requirements. The sensors of sensing component 140 provide data and / or information to at least logic device 110. In one aspect, logic device 110 can be configured to communicate with sensing component 140. In various embodiments, sensing component 140 can provide information regarding environmental conditions (e.g., outdoor temperature), lighting conditions (e.g., daytime, nighttime, dusk, and / or dawn), humidity levels, specific weather conditions (e.g., sun, rain, and / or snow), distances (e.g., laser rangefinders or time-of-flight cameras), and / or whether a tunnel or other type of enclosure has been entered or exited. Sensing component 140 can represent conventional sensors generally known to those skilled in the art for monitoring various conditions (e.g., environmental conditions) that may affect the image data provided by image capture component 120 (e.g., the appearance of the image).

[0050] In some embodiments, sensing component 140 (e.g., one or more sensors) may include devices that relay information to logic device 110 via wired and / or wireless communications. For example, sensing component 140 may be adapted to receive information from satellites via local broadcast (e.g., radio frequency (RF)) transmissions, via mobile or cellular networks, and / or via information beacons within infrastructure (e.g., traffic or highway information beacon infrastructure), or various other wired and / or wireless technologies. In some embodiments, logic device 110 may use information (e.g., sensory data) obtained from sensing component 140 to modify the configuration of image capture component 120 (e.g., adjust light sensitivity levels, adjust the orientation or angle of image capture component 120, adjust aperture, etc.). Sensing component 140 may include temperature sensing components to provide temperature data (e.g., one or more measured temperature values) of various components of imaging device 105 (e.g., image detection circuitry 165 and / or shutter 185). As non-limiting examples, temperature sensors may include thermistors, thermocouples, thermopiles, pyrometers, and / or other suitable sensors for providing temperature data.

[0051] In some embodiments, the various components of the imaging system 100 may be distributed across a network 160 and communicate with each other via the network 160. In this regard, the imaging device 105 may include a network interface 145 configured to facilitate wired and / or wireless communication between the various components of the imaging system 100 via the network 160. In such embodiments, components may also be replicated if required by the specific application of the imaging system 100. That is, components configured for the same or similar operations may be distributed across the network. Furthermore, if desired, all or part of any of the various components may be implemented using appropriate components of a remote device 155 (e.g., a conventional digital video recorder (DVR), a computer configured for image processing, and / or other device) that communicates with the various components of the imaging system 100 via the network interface 145 via the network 160. Thus, for example, all or part of the logic device 110, all or part of the memory component 115, and / or all or part of the display component 135 may be implemented or replicated at the remote device 155. In some embodiments, the imaging system 100 may not include an imaging sensor (e.g., image capture component 120), but rather receive images or image data from an imaging sensor that is located separately and remotely from the logic 110 and / or other components of the imaging system 100. It will be appreciated that many other combinations of distributed implementations of the imaging system 100 are possible without departing from the scope and spirit of the present disclosure.

[0052] Furthermore, in various embodiments, various components of imaging system 100 may be combined and / or implemented or not implemented as desired or depending on the application or requirements. In one example, logic device 110 may be combined with memory component 115, image capture component 120, image interface 125, display component 135, sensing component 140, and / or network interface 145. In another example, logic device 110 may be combined with image capture component 120 such that certain functions of logic device 110 are performed by circuitry (e.g., a processor, microprocessor, logic device, microcontroller, etc.) within image capture component 120.

[0053] Figure 2 A block diagram of an example image sensor assembly 200 is shown in accordance with one or more embodiments of the present disclosure. However, not all of the depicted components are required, however, and one or more embodiments may include additional components not shown in the figure. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims as described herein. Additional components, different components, and / or fewer components may be provided. In one embodiment, the image sensor assembly 200 may be an FPA, for example, implemented as Figure 1 The image capturing component 120 is configured to:

[0054] The image sensor assembly 200 includes a unit cell array 205, column multiplexers 210 and 215, column amplifiers 220 and 225, a row multiplexer 230, a control bias and timing circuit 235, a digital-to-analog converter (DAC) 240, and a data output buffer 245. In some aspects, operations of the unit cell array 205 and other components and / or operations related thereto can be performed based on a system clock and / or synchronization signal (e.g., a line synchronization (LSYNC) signal). The unit cell array 205 includes an array of unit cells. In one aspect, each unit cell can include a detector (e.g., a pixel) and interface circuitry. The interface circuitry of each unit cell can provide an output signal, such as an output voltage or output current, in response to a detection signal (e.g., a detection current, a detection voltage) provided by the detector of the unit cell. The output signal can indicate the magnitude of EM radiation received by the detector and can be referred to as image pixel data or simply image data. The column multiplexer 215, the column amplifier 220, the row multiplexer 230, and the data output buffer 245 can be used to provide output signals from the unit cell array 205 as data output signals on data output lines 250. The output signals on the data output lines 250 can be provided to components downstream of the image sensor assembly 200, such as processing circuitry (e.g., Figure 1 logic device 110), memory (e.g., Figure 1 Memory component 115), a display device (e.g., Figure 1 135) and / or other components that facilitate processing, storage, and / or display of the output signals. The data output signal can be an image formed by the pixel values ​​of the image sensor assembly 200. In this regard, the column multiplexer 215, the column amplifier 220, the row multiplexer 230, and the data output buffer 245 can collectively provide the ROIC (or a portion thereof) of the image sensor assembly 200. In one aspect, the interface circuit can be considered to be part of the ROIC, or can be considered to be an interface between the detector and the ROIC. In some embodiments, the components of the image sensor assembly 200 can be implemented such that the unit cell array 205 and the ROIC can be part of a single die.

[0055] The column amplifier 225 can generally represent any column processing circuit suitable for a given application (analog and / or digital), and is not limited to amplifier circuits for analog signals. In this regard, the column amplifier 225 can be more generally referred to as a column processor in such a respect. The signals received by the column amplifier 225, such as analog signals on an analog bus and / or digital signals on a digital bus, can be processed according to the analog or digital nature of the signals. As an example, the column amplifier 225 may include circuits for processing digital signals. As another example, the column amplifier 225 can be a path that a digital signal from the unit cell array 205 passes through to reach the column multiplexer 215 (e.g., without processing). As another example, the column amplifier 225 may include an ADC for converting analog signals into digital signals (e.g., to obtain a digital count value). These digital signals can be provided to the column multiplexer 215.

[0056] Each unit cell can receive a bias signal (e.g., a bias voltage, a bias current) to bias the detector of the unit cell to compensate for different response characteristics of the unit cells that may be attributable to, for example, temperature variations, manufacturing variations, and / or other factors. For example, the control bias and timing circuit 235 can generate the bias signals and provide them to the unit cells. By providing appropriate bias signals to each unit cell, the unit cell array 205 can be effectively calibrated to provide accurate image data in response to light (e.g., visible light, IR light) incident on the detector of the unit cell. In one aspect, the control bias and timing circuit 235 can be, can include, or can be part of the logic circuit.

[0057] The control bias and timing circuit 235 can generate control signals for addressing the unit cell array 205 to allow access to and readout of image data from the addressed portion of the unit cell array 205. The unit cell array 205 can be addressed to access and readout image data from the unit cell array 205 row by row, but in other embodiments, the unit cell array 205 can be addressed column by column or in other ways.

[0058] The control bias and timing circuit 235 can generate a bias value and a timing control voltage. In some cases, the DAC 240 can convert a bias value received as a data input signal on the data input signal line 255 or as part thereof into a bias signal (e.g., an analog signal on the analog signal line 260), which can be provided to the individual unit cells through the operation of the column multiplexer 210, the column amplifier 220, and the row multiplexer 230. For example, the DAC 240 can drive a digital control signal (e.g., provided as a bit) to an appropriate analog signal level for the unit cell. In some technologies, a digital control signal of 0 or 1 can be driven to an appropriate logic low voltage level or an appropriate logic high voltage level, respectively. On the other hand, the control bias and timing circuit 235 can generate a bias signal (e.g., an analog signal) and provide the bias signal to the unit cell without using the DAC 240. In this regard, some embodiments do not include the DAC 240, the data input signal line 255, and / or the analog signal line 260. In an embodiment, the control bias and timing circuit 235 can be, can include, or can be Figure 1 The logic device 110 and / or a portion of the image capture component 120 may be otherwise coupled to Figure 1 logic device 110 and / or image capture component 120.

[0059] In one embodiment, the image sensor assembly 200 can be implemented as part of an imaging device (e.g., imaging device 105). In addition to the various components of the image sensor assembly 200, the imaging device can also include one or more processors, memory, logic devices, displays, interfaces, optical devices (e.g., lenses, mirrors, beam splitters), and / or other components that may be appropriate in various embodiments. In one aspect, the data output signal on the data output line 250 can be provided to a processor (not shown) for further processing. For example, the data output signal can be an image formed by pixel values ​​from unit cells of the image sensor assembly 200. The processor can perform operations such as non-uniformity correction (e.g., flat field correction or other calibration techniques), spatial and / or temporal filtering, and / or other operations. The image (e.g., processed image) can be stored in a memory (e.g., external to the imaging system or local to the imaging system) and / or displayed on a display device (e.g., external to the imaging system and / or integrated with the imaging system). Figure 2 The various components can be implemented on a single chip or multiple chips. In addition, although the various components are shown as a set of separate blocks, the various blocks can be combined together or Figure 2 The various blocks shown in can be separated into separate blocks.

[0060] Note that in Figure 2, the unit cell array 205 is depicted as 8×8 (e.g., 8 rows and 8 columns of unit cells). However, the unit cell array 205 can have other array sizes. As non-limiting examples, the unit cell array 205 can include 512×512 (e.g., 512 rows and 512 columns of unit cells), 1024×1024, 2048×2048, 4096×4096, 8192×8192, and / or other array sizes. In some cases, the array size can have a row size (e.g., the number of detectors in a row) that is different from the column size (e.g., the number of detectors in a column). Examples of frame rates can include 30 Hz, 60 Hz, and 120 Hz. In one aspect, each unit cell of the unit cell array 205 can represent a pixel.

[0061] Figure 3 A block diagram of an example ADC 300 and associated image sensor circuitry 380 is shown, in accordance with one or more embodiments of the present disclosure. However, not all depicted components are required, and one or more embodiments may include additional components not shown. Changes may be made to the arrangement and types of components without departing from the spirit or scope of the claims as described herein. Additional components, different components, and / or fewer components may be provided.

[0062] The image sensor circuit 380 includes a pixel array 385, a column decoder 390, and a row decoder 395. The pixel array 385 includes an array of detectors (e.g., photodetectors, microbolometers), each of which detects EM radiation and generates a pixel value based on the detected EM radiation. The pixel value of the detector can be or can be indicative of a detector signal (e.g., detector voltage, detector current) generated by the detector in response to the EM radiation. The pixel array data is multiplexed out using the column decoder 390 and the row decoder 395. In this regard, the column decoder 390 and the row decoder 395 can perform appropriate column addressing operations and row addressing operations to facilitate readout of the analog detector signals generated by the detectors of the pixel array 385. The analog detector signals can then be provided to the ADC 300 for conversion. As an example, Figure 3 300. In one embodiment, the pixel array 385 may be, or may include, a column-parallel output architecture in which data is read out from each column one row at a time in parallel. In this architecture, data may be sampled at the column level and held for conversion by the ADC 300. Figure 2 The unit cell array 205 may be or may be a part of it.

[0063] ADC 300 includes an integrator 305, a first comparator 310, a second comparator 315, a first pulse generator 320, a second pulse generator 325, a memory 330, a first counter circuit 335, a second counter circuit 340, a logic circuit 345, a first reference generator 350, a second reference generator 355, and an output circuit 360. Each of integrators 305 generates an integrator output signal based on an input signal provided to the integrator. Figure 3 In the example, each integrator 305 selectively receives a corresponding detector signal V in (e.g., generated by a corresponding detector of pixel array 385), selectively receives a reference current signal I1 from first reference generator 350, or selectively receives a reference current signal I2 from second reference generator 355. The signals are selectively provided to integrator 305 by switching using switches 365, 370, and 375 (respectively represented as S1, S2, and S3, and can be referred to as a first reference signal switch, a second reference signal switch, and a detector signal switch). As an example, I2 can be equal to I1 / 255.

[0064] When the corresponding detector switch 375 is closed, each integrator 305 can receive a detector signal from a detector of a column of the pixel array 385. The logic circuit 345 can be operated to control S3 to selectively couple the detector signal to the integrator 305. For a given integrator, when S3 is closed, the integrator begins integrating the detector signal and charging the integrator's capacitor. The integrator can integrate the detector signal until S3 is open and S1 is closed.

[0065] In S l When closed, the integrator receives the first reference signal I l , which causes the capacitor of the integrator to discharge. As the capacitor discharges, the integrator generates an integrator output signal that varies (e.g., increases, decreases) over time. The integrator continues to generate a varying output in response to receiving the first reference signal I1 until such time as S1 opens and S2 closes. In some cases, the time when S1 opens and S2 closes may be when the integrator output signal reaches the reference signal / level V th1 (e.g., also referred to as a threshold signal / level). When S2 is closed, the integrator receives the second reference signal I2, which causes the integrator to continue discharging and further generate a changing output signal until the integrator output signal reaches the reference signal / level V th2 (e.g., also called threshold signal / level). For example, in Figure 3 In, V th2It can be ground (e.g., 0V). In some cases, the integrator output signal can ramp up (e.g., nominally monotonically increasing over time) when the detector signal is provided to the integrator, ramp down (e.g., nominally monotonically decreasing over time) when the capacitor discharges when the integrator receives I1, and / or ramp down (e.g., nominally monotonically decreasing over time) when the capacitor discharges when the integrator receives I2. In some cases, the integrator output signal can ramp down when the detector signal is provided to the integrator, ramp up when the capacitor discharges when the integrator receives I1, and / or ramp up when the capacitor discharges when the integrator receives I2.

[0066] The first comparator 310 compares the integrator output signal (eg, voltage) from the integrator 305 with the threshold signal V thl A comparison is performed and a comparator output signal is generated based on the comparison. The threshold signal V th1 Can be generated by a reference generator. In some cases, the threshold signal V th1 The threshold voltages associated with the first comparator 310 and the second comparator 315 may be based on threshold voltages. For example, V th1 It can be between about 0.5V and 0.7V.

[0067] For a given comparator in the first comparator 310, the comparator receives an output signal from an integrator (e.g., a corresponding integrator in the integrator 305) at a first input of the comparator and receives a threshold signal V at a second input of the comparator. thl , and generates a comparator output signal based on the comparison of the signals. In one aspect, the comparator can be operated when the integrator signal exceeds V th1 generates a comparator output signal that is in or otherwise associated with a first state / level when the integrator signal does not exceed V th1 When the integrator signal exceeds V th1 The high level transition to the integrator when the signal does not exceed V th1 Low level when .

[0068] The second comparator 315 compares the integrator output signal (eg, voltage) from the integrator 305 with the threshold signal V th2 A comparison is performed and a comparator output signal is generated based on the comparison. For example, the threshold voltage V th2can be a ground reference level (e.g., 0V), wherein, for a given second comparator, the first input of the second comparator can be coupled to the integrator output signal and the second input of the second comparator can be grounded. In this regard, the second comparator can receive an output signal from an integrator (i.e., a corresponding integrator in the integrator 305 described above with respect to the first comparator 310), and compare the integrator output signal with respect to the threshold signal V th2 In one aspect, when the integrator signal is lower than the threshold signal V th2 The comparator may generate a comparator output signal that is in or otherwise associated with the first state / level when the integrator signal does not exceed (e.g., reach) the threshold signal V th2 When the comparator output signal is in or otherwise associated with a second state / level different from the first level, the comparator output signal is generated. The first state may be a logic low (e.g., a logic 0) and the second state may be a logic high (e.g., a logic 1), or vice versa. For example, when the first state is a logic low and the second state is a logic high, the comparator output signal is generated from the integrator signal exceeding the threshold signal V th2 The high level transition to integrator signal does not exceed the threshold signal V th2 low level (e.g., reaches ground voltage).

[0069] The first pulse generator 320 receives the comparator output signal from the first comparator 310. In one aspect, for a given pulse generator in the first pulse generator 320, the pulse generator can generate a pulse in response to a transition of the comparator output signal received by the pulse generator from a first state (e.g., a logic low) to a second state (e.g., a logic high). In this regard, an output transition from one of the first comparators 310 can cause the corresponding one of the first pulse generators 320 to transmit a pulse signal to a corresponding memory element of the memory 330. In some cases, the pulse signal duration can be between 1 ns and 2 ns. In one aspect, the pulse signal duration can be set to be less than a duration associated with a period of the first counter circuit 335.

[0070] Second pulse generator 325 receives the comparator output signal from second comparator 315. In one aspect, for a given pulse generator in second pulse generator 325, the pulse generator can generate a pulse in response to a transition of the comparator output signal received by the pulse generator from a first state (e.g., logic low) to a second state (e.g., logic high). In this regard, an output transition from one of second comparators 315 can cause a corresponding one of second pulse generators 325 to transmit a pulse signal to a corresponding memory element of memory 330. In some cases, the duration of the pulse signal can be between 1 ns and 2 ns. In one aspect, the pulse signal duration can be set to be less than a duration associated with a period of second counter circuit 340. In some cases, the period of first counter circuit 335 can be different from the period of second counter circuit 340.

[0071] The memory elements of memory 330 receive a first pulse signal from their corresponding first pulse generator 320 and a second pulse signal from their corresponding second pulse generator 325. In some cases, memory 330 may be a static memory (e.g., the memory elements may be static memory elements). The memory elements of memory 330 may include, for example, latches or flip-flop circuits for storing data (e.g., digital count values). In one aspect, the memory elements may include inverter devices or circuits that are not actively driven by counter circuits 335 and 340. The memory elements may include cross-coupled inverters.

[0072] The first counter circuit 335 adjusts the first digital count value according to time. The first digital count value can be incremented according to the first system clock, for example, by Figure 2 The control bias and timing circuit 235 is provided. In one embodiment, the counter circuit 335 provides control bits to operate (e.g., selectively close or open) switches S1 and S2. When S1 is closed, the first counter circuit 335 can adjust the first digital count value in conjunction with the adjustment of the integrator output signal by the integrator 305 based on the reference signal I1.

[0073] The second counter circuit 340 adjusts the second digital count value according to time. The second digital count value can be incremented according to the second system clock, for example, by Figure 2 The control bias and timing circuit 235 is provided. In one aspect, the second clock used by the second counter circuit 340 can be faster than the first clock used by the first counter circuit 335. In some cases, the first clock used by the first counter circuit 335 can be referred to as a synchronous clock. When S2 is closed, the second counter circuit 340 can adjust the second digital count value in conjunction with the adjustment of the integrator output signal by the integrator 305 based on the reference signal I2.

[0074] In response to the first pulse signal, the first memory element can capture a first digital count value from the first counter circuit 335. In response to the second pulse signal, the second memory element can capture a second digital count value from the second counter circuit 340. For a given detector signal V in , the first digital count value and the second digital count value may be combined to obtain an indicative detector signal V in In this regard, the first digital count value and the second digital count value together provide a detector signal V in The first digital count value may provide a first set of bits of the total digital count value, and the second digital count value may provide a second set of bits of the total digital count value. In one aspect, the first set of bits may be the most significant bits (MSBs) of the total digital count value, and the second set of bits may be the least significant bits (LSBs) of the total digital count value. In some cases, the first digital count value may contribute to the detector signal V in The second digital count value can contribute to the rough conversion of the detector signal V in Thus, in one embodiment, a first digital count value stored in memory 330 and its corresponding second digital count value stored in memory 330, when combined, provide a digital representation (e.g., an ADC conversion value) of a respective detector signal generated by a respective detector of pixel array 385.

[0075] Output circuit 360 can be coupled to memory 330 and can be configured to further process digital data stored in memory 330, such as digital count values. In some aspects, output circuit 360 can determine a scaling factor based on the count values ​​stored in memory 330 (e.g., as part of a calibration process). In some cases, such processing can include generating a data structure containing the digital count values ​​for processing, storage, and / or display by components downstream of output circuit 360 (e.g., logic devices, memory, display devices, etc.). In one embodiment, output circuit 360 can be considered or implemented as part of the ROIC. In one embodiment, output circuit 360 can be implemented by a logic device (e.g., logic device 110). Output circuit 360 can be implemented as part of ADC 300, such as Figure 3 as shown, or separately from ADC 300.

[0076] Note that in some embodiments, first pulse generator 320 and second pulse generator 325 are optional. In some cases, comparators 310 and 315 provide comparator output signals directly to memory 330 without an intervening pulse generator, allowing the memory element of memory 330 to store each counter value received from the counter circuit and thus consume power each time the counter circuit adjusts its counter value. For example, when the comparator output signal applied to the memory element remains at a logic high, the memory element can store each counter value received from the counter circuit. For some embodiments, the use of a pulse generator can allow for reduced power consumption compared to a scenario where the comparator is directly connected to the memory (e.g., without an intervening pulse generator). In this regard, for a pulse generator, the power consumption of the memory element may be primarily associated with the time at which the counter value generated by the counter circuit is captured (e.g., stored, latched) (e.g., the duration of the pulse signal used to capture the counter value). At other times, the memory element does not capture the counter value generated by the counter circuit. In some cases, the pulse generator can act as an output buffer to drive the memory element. When acting as an output buffer, the pulse generator can facilitate faster conversions, which can enable higher-speed ADC designs.

[0077] Figure 4 4 is a diagram illustrating the operation of the ADC 300 according to one or more embodiments of the present disclosure. Initially, to facilitate conversion of the detector signal from the pixel array 385, each of the integrator 305, the first counter circuit 335, and the second counter circuit 340 may be reset at time t=t0. For example, the reset may be performed such that the first counter circuit 335 and the second counter circuit 340 are at a zero digital count value and the integrator output is at a threshold voltage (e.g., a reference signal V th ). At t=t0, S1 and S2 may be open and S3 may be closed. For a given integrator (e.g., one of the integrators 305), at the moment S3 is closed, the integrator begins to generate the integrator output signal. In one embodiment, the integrator output signal may be a signal from V th1 On the one hand, the slope of the voltage ramp is proportional to the detector signal V supplied as input to the integrator when S3 is closed. in Proportional.

[0078] At time t = t0 + t l (For example, the duration t has elapsed since the start of the ramp-up of the integrator output voltage and the first digital count value l After that, S3 is turned on and S l Closed to allow the first reference signal I lThe input to the integrator is provided. In one aspect, t1 can be a predetermined amount of time. In some cases, t1 can be set by the user. In one aspect, the time from t0 to t0+t1 can be referred to as input integration or input sampling. At time t=t0+t1, when the integrator capacitor discharges, the first counter circuit 335 begins adjusting the first digital count value in conjunction with adjusting the downward ramp voltage of the integrator output signal.

[0079] At time t=t0+t2, the integrator output signal reaches (e.g., meets, crosses, is equal to) the threshold voltage V thl At this time, in response to the integrator output signal and the threshold voltage V th1 Compare and determine whether the integrator output signal has reached the threshold voltage V th1 , a comparator in the first comparator 310 generates a comparator output signal that transitions (e.g., from high to low or low to high, depending on the implementation). A corresponding one of the first pulse generators 320 determines the rising edge or falling edge of the comparator output transition and, in response, generates a first pulse signal. The first pulse signal may be received at a memory element of the memory 330, and in response to receiving the first pulse signal, the memory element may capture a first digital count value (represented as the MSB) from the first counter circuit 335. out In one aspect, the time from t0+t1 to t0+t2 can be referred to as a coarse integral, a first integral, a first phase, or variations thereof (eg, a first integration phase).

[0080] Furthermore, at time t=t0+t2, S1 opens and S2 closes to allow the second reference signal I2 to be provided to the integrator input. At time t=t0+t2, as the integrator capacitor continues to discharge, the second counter circuit 340 begins adjusting the second digital count value in conjunction with adjusting the downward ramp voltage of the integrator output signal. In one aspect, the discharge rate of the integrator when S2 is closed is lower than when S1 is closed (e.g., due to the difference between I1 and I2). As an example, I2 may be I1 / 255.

[0081] At time t=t0+t3, the integrator output signal reaches (e.g., meets, crosses, is equal to) the ground voltage. At this time, in response to comparing the integrator output signal with the ground voltage and determining that the integrator output signal has reached the ground voltage, the comparator in the second comparator 315 generates a comparator output signal that transitions (e.g., from high to low or from low to high, depending on the implementation). A corresponding one of the second pulse generators 315 determines the rising edge or falling edge of the comparator output transition and, in response, generates a second pulse signal. The second pulse signal can be received at a memory element of the memory 330, and in response to receiving the second pulse signal, the memory element can capture a second digital count value (expressed as LSB) from the second counter circuit 340. out ). In one aspect, the time from t0+t2 to t0+t3 can be referred to as a fine integration, a second integration, a second phase, or variations thereof (e.g., a second integration phase). In one embodiment, the first and second digital count values ​​stored in memory 330 together provide a digital representation (e.g., an ADC conversion value) of a detector signal generated by a detector of pixel array 385. In this regard, the first digital count value and its corresponding second digital count value can be combined to obtain a total digital count value. In one aspect, the total digital value is the detector signal V used to obtain the first and second digital count values. in digital representation.

[0082] although Figure 4 Graph 400 provides an example with a downward slope, but other ADC architectures may be associated with an upward slope. Figure 5 A diagram 500 is shown associated with the operation of an ADC according to one or more embodiments of the present disclosure. The ADC may have components arranged the same or similarly as the ADC 300. For t < t1, S1 and S2 may be open and S3 may be closed, so that the integrator (e.g., 305) generates an integrator output signal as the input signal to be digitized provided to the integrator. At t = t1, the integrator switches from receiving the input signal to receiving the reference signal I1 (e.g., a current signal). From t = t1 to t = t2, the integrator generates a ramping integrator output signal, and the first counter circuit increments its counter value. This ramp may be referred to as a first ramp. The comparator receives the integrator output signal and the reference signal V th1 , and generates a comparator output signal in a first state (e.g., logic low). At t=t2, the integrator output signal reaches the reference signal V th1 The comparator is tripped (eg, the comparator output signal transitions from a first state to a second state). The counter value at t=t2 may correspond to the first group of bits (eg, MSB). + At t=t2, the integrator switches from receiving the reference signal I1 to receiving the reference signal I2 (for example, the current signal).+ At t=t3, the integrator generates a ramping integrator output signal, and the second counter circuit increments its counter value. This ramp can be referred to as the second ramp. The comparator receives the integrator output signal and the reference signal V th2 (e.g., ground level) and generates a comparator output signal in the first state. At t=t3, the integrator output signal reaches the reference signal V th2 The comparator is tripped (eg, the comparator output signal transitions from the first state to the second state). The counter value at t=t3 may correspond to a second group of bits (eg, LSBs). In some cases, I2=I1 / 255.

[0083] Although diagrams 400 and 500 illustrate embodiments in which the end of a first conversion phase coincides with the start of the next conversion phase, in other cases, times may be allocated for the first and second conversion phases. In some cases, the time for the first conversion phase may be longer than the time for the second conversion phase. For a given conversion phase, conversions associated with input signals from columns of the pixel array may be performed in parallel, and the conversion phases may be allocated times to allow the comparators to transition for all columns for the range of input signal values ​​accommodated by the ADC. For example, the input voltage level for the first column may be lower and therefore associated with a shorter conversion time, while the input voltage level for the second column may be higher and therefore associated with a longer conversion time. The count value for the first column may be stored / latched earlier in the time allocated for the first ramp, while the count value for the second column may be stored / latched later in the time allocated for the first ramp.

[0084] Figure 6 1 shows signal waveforms associated with the operation of an ADC according to one or more embodiments of the present disclosure. An input signal to the ADC (denoted as Signal1) is captured, and then a ramp is applied to the input signal to adjust the input signal relative to a fixed reference voltage V REF Move the input signal. Figure 6 The resulting signal from applying the ramp to the input signal is denoted as SIG OUT The ADC can have Figure 3 ADC 300 may have the same or similar architecture (eg, with or without a pulse generator) and / or other dual-slope ADC architectures.

[0085] The amount of time it takes for a ramped signal to cross a reference level and thereby trip (e.g., also referred to as firing) a comparator (e.g., causing the comparator output signal to transition from one state to another) is a measure of the MSB associated with the input signal. Once the comparator trips, the ramping of the input signal will continue to increase until the start of the next clock cycle (e.g., the next synchronous clock cycle). The cessation of the ramp on the clocked input signal allows the stored level corresponding to the count value associated with the MSB to remain. In some cases, the conversion of the input signals from the columns can be performed in parallel, and respective times can be allocated to each of the first and second ramps to allow the comparator to trip for all columns for the range of input signal values ​​accommodated by the ADC. In one aspect, the count value associated with the MSB can be referred to as the MSB count value. Typically, for a multi-range ADC, this first ramp (e.g., corresponding to and / or referred to as the first conversion phase or first phase) is typically associated with more time than the second ramp and subsequent ramps (if any). Therefore, the clock used to synchronize the end of the first ramp, and thus the MSB count value, is typically not the fastest clock in the system.

[0086] After the MSB count value has been stored and the first ramp has stopped, the second ramp can be applied. The second ramp can have a lower range (e.g., scaled in integer increments based on the number of LSB bits and the time dedicated to the first ramp compared to the time dedicated to the second ramp) and can sweep across a finer range to enable digitization of the LSB count value to a small voltage level. When the input signal crosses the reference signal during the second ramp, the comparator can trip at that time and store (e.g., latch) the counter value indicating the LSB. In one aspect, the count value associated with the LSB can be referred to as the LSB count value. Such a clock is typically faster than the clock associated with the first ramp to allow for storage of a finer counter value associated with the LSB. Because such a clock is asynchronous with the clock used for the first ramp, the LSB counter value can be referred to as being asynchronously stored / latched. As an example, the full-scale range associated with coarse conversion can be approximately 2V, while the full-scale range associated with fine conversion can be approximately 125mV. After input signal Signal1 is converted, the ADC can subsequently capture the next input signal, denoted as Signal2.

[0087] The second ramp can be implemented in a variety of ways depending on the ADC architecture / implementation. As an example, the second ramp can continue in the same direction as the first ramp (e.g., Figure 4 and 5As shown in FIG, 1 , the reference level is shifted upward. As another example, the second ramp can be ramped in the opposite direction, as it will initially overshoot the target reference level, possibly with some offset to ensure that it will cross the reference level again. Before the second ramp begins, an offset can be applied to move the input signal to the opposite side of the reference level before the ramp continues again in the same direction. Other examples of ADCs and associated waveforms are described in U.S. patent application Ser. No. 17 / 362,876, filed on June 29, 2021, the entire contents of which are incorporated herein by reference.

[0088] In some embodiments, a multi-range ADC can facilitate fast conversion of analog input signals. The ADC's quality factors can include monotonicity and DNL (no missing or redundant codes). Appropriate calibration can be performed to allow for combining multiple ranges with accuracy, such that the final / combined ADC output is monotonic and free of any missing codes. Monotonic codes without missing codes can have a DNL between -1 and +1.

[0089] Although the embodiments herein are generally described with respect to an ADC architecture having a first ramp associated with a first group of bits (e.g., MSBs) of a digital representation of an analog signal (e.g., a detector signal) and a second ramp associated with a second group of bits (e.g., LSBs) of the digital representation, such an ADC architecture may generate a digital representation of the analog signal using more than two ramps, where each ramp is associated with a respective group of bits of the digital representation.

[0090] In a dual-slope ADC (e.g., also known as a dual-slope ADC), a first ramp can be swept across a signal range to determine a first set of bits (e.g., MSBs) of a digital representation of an analog signal, and then a second ramp can be swept across to determine a second set of bits (e.g., LSBs) of the digital representation. In some cases, the first ramp is steeper / faster than the second ramp. Note that each of the first and second ramps can be a linear ramp or a nonlinear ramp. If the slopes of the two ramps do not match (e.g., the first ramp and / or the second ramp are not at their respective predetermined values), non-monotonicity (or equivalently, missing codes) may occur.

[0091] In some embodiments, a dual-slope ADC can be calibrated to determine a scaling factor (e.g., also referred to as a calibration factor) to be applied to the count value (e.g., corresponding to the MSB) to correct for a mismatch (e.g., a gain mismatch) between the first slope and the second slope. Correcting such a mismatch can avoid redundant or missing codes. The calibration can be based on a relationship between the start of the first slope and the start of the first counter. The start of the first slope can be the time when the first slope begins to ramp up or ramp down. The start of the first counter can be the time when the first counter begins to increment or decrement.

[0092] Figure 7A FIG. 700 shows a diagram in accordance with one or more embodiments of the present disclosure, wherein a first ramp starts at different times relative to a counter to facilitate ADC calibration. The first ramp may be associated with a MSB count (e.g., also referred to as a coarse count) generated by a MSB counter circuit. In one aspect, the start of the MSB counter circuit, the start of the MSB counter signal, or the start of the MSB counter may be used interchangeably to refer to the time when the MSB counter circuit begins incrementing its count value according to a first clock. A second ramp (not shown) may be used after the first ramp to obtain an LSB count (e.g., also referred to as a fine count). As an example, the first ramp may be Figure 5 the ramp from t1 to t2 in FIG. 500 of Figure 5 and the second ramp may be

[0093] the ramp from t2 to t3 in FIG. 500 of OUT Signal INT OUT (e.g., a voltage signal) may be or may represent / simulate an integrator output voltage. The initial value of signal INT Figure 5 may be obtained from an integration associated with an input signal of the ADC (e.g., Figure 5 the integration during t < t1 in FIG. 500 of OUT Signal INT OUT may ramp up from the initial value. A comparator (e.g., one of the first comparators 310) may receive signal INT IN and a reference signal INT OUT and generate a comparator output signal based on signal INT IN and reference signal INT OUT When signal INT IN does not exceed reference signal INT OUT the comparator output signal may be in a first state (e.g., logic low), and when signal INT IN exceeds reference signal INT IN the comparator output signal may be in a second state (e.g., logic high). In some cases, the reference signal INT Figure 7A may be set to facilitate conversion of the value of an analog input signal within a certain value range (e.g., depending on the application, product requirements, etc.). As an example, in IN the reference signal INT IN is 2.8V. In one aspect, the reference signal INT Figure 5 corresponds to the reference signal V th1 in

[0094] The end of the first ramp can be associated with the MSB count. The value of the MSB count can be incremented according to the first clock (e.g., by an MSB counter circuit). OUT Exceeds the reference signal INT IN The comparator output signal changes from the first state to the second state. The first ramp continues to increase until it is consistent with the signal INT OUT Exceeds the reference signal INT IN For example, the first ramp reaches the reference signal INT between the start of a first clock cycle (e.g., associated with an MSB count of 1) and the start of a second clock cycle (e.g., associated with an MSB count of 2) that is adjacent in time to the first clock cycle and subsequent thereto. IN The MSB counts of the first clock cycle and the second clock cycle are consecutive integers (eg, MSB counts of 1 and 2, respectively). In some cases, the signal level (eg, voltage) at the end of the first ramp may be stored.

[0095] The first ramp can start at a different time based on a second clock that is faster than the first clock. Therefore, in some cases, the first clock can be referred to as a coarse clock, while the second clock can be referred to as a fine clock. In graph 700, the input signal provided to the ADC can have values ​​such that when the start of the first ramp coincides with the start of the MSB counter circuit, the first ramp results in an MSB count of 2. As shown in graph 700, the start of the first ramp can be adjusted to be earlier or later relative to the start of the MSB counter circuit. A ramp time offset (e.g., also referred to as a ramp offset) can provide a difference in the number of fine clock steps between the start of the first ramp and the start of the MSB counter circuit. The first clock (e.g., a synchronous clock) is used to facilitate storage (e.g., latching, capturing) of the voltage value at the end of the first ramp. The time increment used to adjust the start of the first ramp can be adjusted using the second clock. In some embodiments, rather than adjusting the start of the first ramp, the start of the first ramp can be fixed and the start of the counter can be adjusted using the second clock. Therefore, the start of the first ramp can be referred to as the first ramp starting at each of a plurality of time instances relative to the corresponding start time of the counter.

[0096] By adjusting when the first ramp begins, the value / level of the first ramp can be at different levels when the first clock causes the first ramp to stop. Different values ​​of the first ramp (e.g., associated with the MSB count value) are associated with different values ​​of the second ramp (e.g., associated with the LSB count value). In this regard, when the start of the first ramp changes, the level of the input signal sampled at the end of the first ramp is different, thereby generating a different LSB during the second ramp (not shown). In graph 700, there are 8 fine clock steps between each coarse clock, or equivalently, each first ramp offset adjusts the start of the first ramp by 1 / 8 of the MSB count.

[0097] Waveforms 705, 710, 715, and 720 are associated with ramps having ramp offsets of 0, -2 (e.g., advanced by two fine clock steps), +4 (e.g., delayed by four fine clock steps), and +8. Because the end of the first ramp of waveform 715 is at a lower level than the end of the first ramps of waveforms 705, 710, and 720, the LSB count value determined during the second ramp associated with waveform 715 is higher than the LSB count values ​​associated with waveforms 705, 710, and 720. For any input signal, adjusting the start of the first ramp by -8 fine clock steps or +8 fine clock steps will produce the same sample value at the end of the first ramp (and therefore the same LSB during the second ramp), but offset by one MSB count. For example, the end of the first ramp of waveforms 705 and 720 has a sample value and an MSB count of 2 for waveform 605, while the MSB count for waveform 620 is 3. As Figure 7B As shown, starting the ramp with different first ramp offsets can be viewed as, or can be simulated / implemented by using an appropriate clock to plot / sample the voltage values ​​of a single first ramp at different points in time.

[0098] The variation of the first ramp between -8 and +8 clock cycles ensures that seven different LSB count values ​​can be determined with the same MSB count for any fixed input level. When the first ramp is a linear ramp, either of the two LSB values ​​can be used to determine the slope of the first ramp compared to the slope of the second ramp. As an example, the start of the first ramp can be delayed in increments / steps of 2 ns (e.g., one cycle of a 500 MHz clock), and the clock rate that determines the rate of change of the LSB counter value is 1 count per ns. If the start of the ramp is delayed 2 ns (e.g., one cycle of a 500 MHz clock) relative to the MSB counter and the synchronous clock, the corresponding change in the voltage stored / saved at the end of the first ramp is (2 ns)(slope RAMP1 ), where slope RAMP1 is the slope of the first slope. Then, we can express it as slope RAMP2The slope of the second ramp and the clock rate that determines the rate at which the LSB counter value changes will cause the stored voltage level V stored Converted to LSB counter value. Each first ramp excursion count (e.g., each increment / step is 2ns) changes by V stored / slope RAMP2 The time to store the LSB counter value. Therefore, the total conversion factor of one step change from the start of the first slope is (2ns) × (slope RAMP1 / slope RAMP2 )×(1count / 1ns). Expressed as LSB cnt The LSB of the counter value is represented by R1O cnt The ratio of the first slope offset count can be provided as LSB cnt / R1O cnt =2(slope RAMP1 / slope RAMP2 ). Ideally / nominally (e.g., no mismatch, such as gain mismatch), slope RAMP1 / slope RAMP2 =32 and LSB cnt / R1O cnt =2(slope RAMP1 / slope RAMP2 )=64. As shown in this example, for a given first slope offset change, the change in LSB count is proportional to the slope RAMP1 / slope RAMP2 Proportional.

[0099] A calibration may be performed to generate a scaling / calibration factor that provides an actual weighting of the MSB counts to account for mismatches associated with the first ramp and / or the second ramp. In this regard, such a scaling / calibration factor provides an indication of how much the LSB counts are within the MSB counts. Figure 7A ) is equivalent to synchronizing the first ramp clock (e.g., 16 ns per step). In this regard, the clock ratio between the synchronized first ramp clock and the clock associated with the ramp offset is 8. In the example where the full MSB count is associated with eight first ramp offset counts (e.g., as shown in FIG. Figure 7A As shown), the scaling / calibration factor can be given by Scaling Factor = (ΔLSB cnt / ΔR1O cnt )(8) is provided. All eight first ramp offsets are associated with the same LSB count value, but are offset by one MSB count value. Changes in the first ramp offset that are less than eight clocks can be scaled to produce a full count.

[0100] To determine the MSB step size based on the LSB count, seven different LSB counts associated with the same MSB value can be used. Any two or more of these seven LSB counts can be used (e.g., in the linear case) and scaled to eight steps to determine the scaling factor. While any two of these LSB values ​​can be used, using more than two LSB values ​​(up to all seven) to determine the best fit curve (e.g., linear or nonlinear) can provide better calibration results. As the difference between the clock speed at which the first ramp is adjusted to begin and the synchronous clock speed associated with the incrementing MSB count increases, more samples can be acquired for the same MSB count to determine the best fit curve. If the first ramp is linear or substantially linear, the LSB points can be fitted to a line. If the first ramp is not linear, the LSB points can be fitted to a polynomial or other function and then scaled to the appropriate number of steps to estimate the MSB step size.

[0101] Figure 8 Graph 800 shows example calibration data for determining a calibration / scaling factor for a given MSB count, according to one or more embodiments of the present disclosure. For illustrative purposes, the clock ratio between the synchronized first ramp clock and the clock associated with the first ramp time offset (denoted as R10 and used to set the start time of the first ramp relative to the start time of the MSB counter) is 8. The first ramp time offset can sweep from -8 clock steps to +8 clock steps. For each clock step, multiple samples can be acquired at each clock step (e.g., to average out noise). A first ramp offset from -4 clock steps to +4 clock steps is shown in graph 800. The first ramp offset from -4 clocks to +1 clock in graph 800 is associated with samples having an MSB count of 1. Although not shown in graph 800, first ramp offsets below -4 clocks (e.g., -7, -6, and -5 clocks) can also be associated with an MSB count of 1 and can be associated with an average count value that is lower than the average count value between -4 clocks and +1 clock.

[0102] From the graph 800, the average LSB count value for R10 = -4 is 435.09, and the average LSB count value for R10 = +1 is 746.81. avg The difference in the mean LSB counts of is (746.81–435.09) and is expressed as ΔR1O The difference in the first ramp offset of is (1 - (-4)). From the results shown in graph 800, the calibration factor associated with the MSB count of 1 can be obtained by scaling factor = (ΔLSB avg / ΔR10)(clock ratio)=(746.81−435.09) / [1−(−4)](8)=498.75. In this example, the calibration factor of 498.75 is lower than the nominal weight of 512 LSB counts per 1 MSB count.

[0103] Despite Figure 8 The example provided in describes the average LSB counts associated with two first ramp offsets, but more than two average LSB counts can be used. Generally, a calibration factor determined using more average LSB counts can provide greater accuracy to compensate for noise and errors (e.g., mismatch) associated with the ADC being calibrated than a calibration factor determined using fewer average LSB counts. As another example, Figure 9 A chart 900 is shown according to one or more embodiments of the present disclosure, wherein a best linear fit (e.g., a best fit line) is determined using more than two average LSB counts. From the best linear fit, the slope of the best fit line, 62.327, is multiplied by the clock ratio, 8, to obtain a calibration factor, 498.62. Note that the offset (e.g., 186.12) shown in chart 900 generally does not provide information associated with the calibration factor. For a given MSB count, the LSB value swept at R10 can provide a check on the accuracy of the global offset applied between the two ramps. An accurate global offset can ensure that the LSB is not pulled high or low and is centered within the LSB range.

[0104] like Figure 9 As shown, the equation for the best fit line is y = 62.327x + 186.12, where x is the RIO setting and y is the average LSB count. To use this equation, the value y can be determined from the best fit line. MIN (R1O=4.0)=LSB MIN =62.327(4.0)+186.12=435.428 and value y MAX (R1O=9.0)=LSB MAX = 62.327(9.0) + 186.12 = 747.063. The scaling factor (eg, MSB weight) can be calculated by scaling factor = [y MAX (R1O=9.0)–y MIN (R1O=4.0)] / (9.0-4.0)(8)=498.616 by scaling y MAX (R1O=9.0)–y MIN (R1O=4.0) to the full 8 clocks to provide, because each MSB counts 8 clocks and the sampling point spans only 5 clocks (e.g., from R1O=9 to R1O=4).

[0105] As another example, Figure 10Graph 1000 is shown in accordance with one or more embodiments of the present disclosure, wherein more than two average LSB counts are used to determine a nonlinear curve (eg, a polynomial trend line). The equation for the best fit curve is y = -3.4132x 2 +101.36x+80.312, where x is the RIO setting and y is the average LSB count. For this nonlinear case, two R1O points 8 clocks apart (e.g., since each MSB counts 8 clocks) can be used to determine the scaling factor, since the LSB count cannot be directly scaled to the full 8 clocks provided in the linear case. As an example, the minimum and maximum R1Os with the same MSB counts seven R1Os apart can be used, and then each R1O can be offset by 0.5 counts. Assume that the sampled data spans from R1O=3.0 to R1O=11.0. The R1O endpoints of 3.5 and 11.5 can be used: y MIN (R1O=3.5)=LSB MIN =-3.4132(3.5) 2 +101.36(3.5)+80.312=393.2253 and y MAX (R1O=11.5)=LSB MAX =-3.4132(11.5) 2 +101.36(11.5)+80.312=794.4413. The scaling factor (e.g., MSB weight) can be obtained by MAX (R1O=11.5)-y MIN (R1O=3.5)=401.216 provides. Alternatively or additionally, R1O endpoints of 4.0 and 12.0 may be used to obtain y MAX (R1O=12.0)-y MIN (R10=4.0)=431.1008. In some cases, the scaling factor may be set to 401.216, 431.1008, and / or the average of these two values.

[0106] Typically, the nominally fixed input provided to an ADC is not fixed due to the presence of noise. Furthermore, the ADC itself may generate noise. Multiple samples can be used to reduce the effects of noise. In some cases, this noise can improve LSB resolution because various values ​​that would ideally be integers may actually become non-integer values. With multiple samples, the average value of a given setting may be a non-integer value, thus allowing the LSB average to be a non-integer value and the calibration factor to be a non-integer value. Using a non-integer value for the calibration factor allows for higher resolution than an integer-valued calibration factor.

[0107] In some aspects, each MSB count can be associated with a different calibration factor. During calibration, appropriate inputs can be provided to the ADC to allow determination of calibration factors for multiple MSB counts (e.g., 2 when the MSB comprises 5 bits). 5 In some aspects, due to variations in each column of the imaging device (e.g., column gain factor variations), calibration can be performed for each column of the imaging device. Thus, for an L-bit ADC (e.g., a 14-bit ADC) associated with N MSB bits (e.g., 5 MSB bits), M LSB bits (e.g., 9 LSB bits), and additional redundant LSB bits, where L=N+M, using a calibration factor appropriate for a given MSB count and / or a given column, calibration can be performed by S ADC =MSB cnt (scaling factor) + LSB cnt Provides a total value. Furthermore, although the calibration factor is described above as being applied to the MSB, the calibration factor may instead be appropriately determined and applied to the LSB. In this case, the total value may be obtained by S ADC =MSB cnt (2 M )+LSB cnt (scaling factor) / 2 M For example, when M=9, each MSB count ideally / nominal has a weight of 512 LSB counts.

[0108] Figure 11 A flow chart of an example process 1100 for facilitating ADC calibration according to one or more embodiments of the present disclosure is shown. Figure 4-10 Various charts and Figure 3 The process 1100 is described with respect to the ADC 300 of FIG. 1 , but the process 1100 can be performed with respect to other diagrams and / or associated ADC architectures. Note that Figure 11 One or more operations in may be combined, omitted, and / or performed in a different order as desired. In some cases, Figure 11 The operations shown in can be performed as part of factory calibration and / or field calibration.

[0109] At block 1105, an integrator (e.g., one of integrators 305) and a coarse counter circuit (e.g., first counter circuit 335) operate in conjunction so that a first ramp signal begins at a time instance relative to a start time of the coarse counter circuit. The ramp signal generated using the generator may be in response to receiving a reference signal (e.g., Figure 3The integrator output signal of the integrator is generated based on the reference current I1 of the reference generator 350 in the coarse counter circuit to discharge the integrator capacitor. In some cases, the start of the coarse counter circuit can be fixed, while the start of the first ramp signal can be adjusted (e.g., using a fine clock). In other cases, the start of the first ramp signal can be fixed and the start of the coarse counter circuit can be adjusted (e.g., using a fine clock). The start of the first ramp occurs when the first ramp begins to ramp up or down. The start of the counter can occur when the counter value begins to increment or decrement. As an example, in chart 400, the start of the first ramp occurs when the first ramp begins to ramp down at time t0+t1, and the start of the counter occurs when the counter value begins to increment at time t0+t1. Prior to time t0+t1, the integrator can be used to generate the integrator output signal based on the analog input signal to be digitized by the ADC. For block 1105, the start of the first ramp can, but need not, coincide with the start of the counter. In one aspect, the offset between the start of the first ramp and the start of the counter can be referred to as the first ramp offset.

[0110] At block 1110, a comparator (eg, one of the first comparators 310) generates a threshold signal based on a first ramp signal and a threshold signal (eg, a reference signal V th1 ) generates the comparator output signal. For example, refer to Figure 5 500, when the value (eg, voltage value) of the first ramp signal does not exceed the threshold signal V th1 , the comparator may generate a comparator output signal that is in or associated with a first state (eg, logic low), and when the value of the first ramp signal exceeds / reaches the threshold signal V th1 , the comparator may generate a comparator output signal that is in or associated with a second state (e.g., logic high). In this example, once the value of the first ramp signal increases above the threshold signal V th1 The comparator output signal changes from the first state to the second state.

[0111] At block 1115, a memory (eg, memory 330) captures the value of the first ramp signal in response to a transition of the comparator output signal (eg, from a first state to a second state). Figure 7A When the comparator output signal transitions in value during one clock cycle (e.g., associated with an MSB count), the first ramp signal may continue to increase until the start of the next clock cycle (e.g., associated with the next MSB count). In this regard, capturing the value of the first ramp signal occurs according to a clock that is slower than a clock associated with adjusting a start time of the first ramp signal and / or a start time of the counter.

[0112] At block 1120, the ADC determines a fine counter value associated with the first ramp signal started at block 1105 based on the value of the first ramp signal captured at block 1115. The fine counter value may be determined using the second ramp signal. The integrator may generate a second ramp signal based on the value of the first ramp captured at block 1115. A fine counter circuit (e.g., second counter circuit 340) associated with the fine counter value may operate in conjunction with the second ramp signal. A clock signal associated with the operation of the fine counter circuit may be faster than a clock signal associated with the operation of the coarse counter circuit. In some cases, a starting value of the second ramp signal may be based on the value of the first ramp captured at block 1115. A comparator (e.g., one of second comparators 315) may generate a second ramp signal based on the second ramp signal and a threshold signal (e.g., Figure 5 V in th2 ) generates the comparator output signal. Figure 5 500, when the value (eg, voltage value) of the second ramp signal does not exceed the threshold signal V th2 , the comparator output signal may be in or associated with a first state (eg, logic low), and when the value of the second ramp signal exceeds / reaches the threshold signal V th2 The comparator output signal may be in or associated with the second state (eg, logic high) when the comparator output signal transitions from the first state to the second state. The memory may capture the fine counter value currently output by the counter circuit in response to the comparator output signal transitioning from the first state to the second state.

[0113] At block 1125, a determination is made as to whether the first ramp signal has started at all predetermined time instances relative to the corresponding start times of the coarse counter circuit. If the determination is that the first ramp signal has not started at all predetermined time instances, process 1100 proceeds to block 1105 such that blocks 1105, 1110, 1115, 1120, and 1125 are performed in relation to the next time instance (e.g., the next ramp offset setting).

[0114] If the determination is that the first ramp signal has begun at all predetermined time instances, process 1100 proceeds to block 1130. For purposes of explanation, the fine counter value obtained from the iterations of blocks 1105, 1110, 1115, and 1120 is compared to the coarse counter value of the coarse counter signal (e.g., Figure 8 At block 1130, logic (e.g., implemented by output circuit 360) determines a scaling factor (e.g., also referred to as a calibration factor) associated with the coarse counter value based on the fine counter value and a plurality of time instances. The scaling factor may be determined by determining a relationship between the fine counter value and the first ramp offset, such as Figure 8-10 shown.

[0115] As described above, a calibration factor can be determined for each coarse count (e.g., MSB count) and each column (e.g., due to column gain factor variations) of an imaging device. Thus, in some embodiments, process 1100 can be performed to determine calibration factors for different columns and / or different coarse counts.

[0116] Figure 12 A flow chart of an example process 1200 for applying a scaling factor according to one or more embodiments of the present disclosure is shown. Figure 3 The process 1200 is described with respect to the ADC 300 of FIG. 1 , but the process 1100 may be performed with respect to other diagrams and / or associated ADC architectures. Note that Figure 12 One or more operations in may be combined, omitted, and / or performed in a different order as desired.

[0117] At block 1205, an integrator (e.g., one of the integrators 305) generates an integrated output signal based on the detector signal. At block 1210, the integrator generates a first ramp signal based on a first reference signal (e.g., the current signal I1), and a coarse counter circuit (e.g., the first counter circuit 335) generates a coarse counter signal in conjunction with the first ramp signal. At block 1215, a comparator (e.g., one of the first comparators 310) generates a coarse counter signal based on the first ramp signal and a reference signal (e.g., the current signal I1). Figure 3 V in th1 ) generates a comparator output signal. When the first ramp signal exceeds the first reference signal, the comparator output signal may be in a first state (e.g., logic low), and when the first ramp signal does not exceed the first reference signal, the comparator output signal may be in a second state. At block 1220, a memory (e.g., memory 330) captures a coarse counter value of the coarse counter signal in response to the transition of the comparator output signal from the first state to the second state.

[0118] At block 1225, the integrator generates a second ramp signal based on a second reference signal (e.g., current signal I2), and the fine counter circuit (e.g., second counter circuit 340) generates a fine counter signal in conjunction with the second ramp signal. At block 1230, the comparator (e.g., one of the second comparators 315) generates a fine counter signal based on the second ramp signal and the second reference signal (e.g., Figure 3 The comparator output signal is generated by the memory (e.g., memory 330) in response to the transition of the comparator output signal from the first state to the second state. When the second ramp signal exceeds the second reference signal, the comparator output signal may be in a first state (e.g., logic low), and when the second ramp signal does not exceed the second reference signal, the comparator output signal may be in a second state. At block 1235, a memory (e.g., memory 330) captures a fine counter value of the fine counter signal in response to the transition of the comparator output signal from the first state to the second state.

[0119] At block 1240, the logic device (e.g., output circuit 360) applies a scaling factor (e.g., stored in memory 330 and / or other memory) to obtain a totalized value associated with the detector signal. Depending on the implementation, the scaling factor may be applied to the coarse counter value stored at block 1220 or the fine counter value stored at block 1235. As described above, a different scaling factor may be determined for each coarse count (e.g., MSB count) and each column of the imaging device (e.g., due to variations in column gain factors). Thus, in some embodiments, process 1200 may be performed on a column-by-column basis and taking into account the coarse count.

[0120] Where applicable, the various embodiments provided by the present disclosure can be implemented using hardware, software, or a combination of hardware and software. Likewise, where applicable, the various hardware components and / or software components set forth herein can be combined into composite components comprising software, hardware, and / or both, without departing from the spirit of the present disclosure. Where applicable, the various hardware components and / or software components set forth herein can be divided into subcomponents comprising software, hardware, or both, without departing from the spirit of the present disclosure. In addition, where applicable, it is conceivable that software components can be implemented as hardware components, and vice versa.

[0121] Software according to the present disclosure, such as non-transitory instructions, program code, and / or data, can be stored on one or more non-transitory machine-readable media. It is also contemplated that the software identified herein can be implemented using one or more general-purpose or special-purpose computers and / or computer systems, networked and / or not. Where applicable, the order of the various steps described herein can be changed, combined into composite steps, and / or separated into sub-steps to provide the features described herein.

[0122] The foregoing description is not intended to limit the present disclosure to the precise forms disclosed or to the specific fields of use. The foregoing embodiments illustrate but do not limit the present invention. It is contemplated that various alternative embodiments and / or modifications of the present invention, whether explicitly described or implied herein, are possible in light of this disclosure. Accordingly, the scope of the present invention is limited solely by the appended claims.

Claims

1. A method for facilitating calibration of an analog-to-digital converter, the method comprising: For each of the multiple time instances: generating a first ramp signal that starts at the time instance relative to a corresponding start of the first counter signal; generating a corresponding first comparator output signal based on the first ramp signal and a first threshold signal, wherein the corresponding first comparator output signal is associated with a first state or a second state; capturing a respective first value of the first ramp signal in response to a transition of the respective first comparator output signal from a first state to a second state; and determining a corresponding second counter value of a second counter signal based on the corresponding first value; and A scaling factor is determined based on the second counter value and the plurality of time instances, wherein each of the first values ​​is associated with a same first counter value of the first counter signal.

2. The method of claim 1 , further comprising, for each of the plurality of time instances: generating a corresponding second ramp signal based on the corresponding first value; and Based on the corresponding second ramp signal and the second threshold signal, a corresponding second comparator output signal is generated, wherein, the corresponding second comparator output signal is associated with the third state or the fourth state, Wherein, for each time instance of the plurality of time instances, determining the corresponding second counter value comprises: capturing the corresponding second counter value in response to a transition of the corresponding second comparator output signal from a third state to a fourth state.

3. The method of claim 1 , further comprising determining a best fit curve based on the second counter value and the plurality of time instances, wherein The scaling factor is based on the best fit curve.

4. The method according to claim 1, wherein The first counter signal is associated with a first clock, and wherein the second counter signal is associated with a second clock having a faster clock speed than the first clock.

5. The method according to claim 4, wherein The scaling factor is also based on the first clock and the second clock.

6. The method according to claim 5, wherein: The scaling factor is based on a ratio of a clock speed of the first clock to a clock speed of the second clock.

7. The method according to claim 1, wherein For at least one time instance of the plurality of time instances: the first comparator output signal transitions from a first state to a second state between the start of a first clock cycle and the start of a second clock cycle that is adjacent in time to the first clock cycle, The corresponding first value indicates the value of the first ramp signal at the beginning of the second clock cycle, and The first counter value is associated with the second clock cycle.

8. The method according to claim 1, further comprising: receiving a detector signal; and A digital representation of the detector signal is determined based on the scaling factor.

9. The method according to claim 8, wherein The digital representation includes a coarse count value associated with the first counter signal and a fine count value associated with the second counter signal, the method further comprising: applying the scaling factor to the coarse count value to obtain a scaled coarse count value; and A total count value associated with the detector signal is generated based on a sum of the scaled coarse count value and the fine count value.

10. The method according to claim 8, further comprising: generating a third ramp signal and a third counter signal synchronized with the third ramp signal; generating a second comparator output signal based on the third ramp signal and the first threshold signal; capturing a third count value of the third counter signal in response to a transition of the second comparator output signal; generating a fourth ramp signal and a fourth counter signal synchronized with the fourth ramp signal; generating a third comparator output signal based on the fourth ramp signal and the second threshold signal; capturing a fourth count value of the fourth counter signal in response to a transition of the third comparator output signal; and A scaling factor is applied to one of the third count value or the fourth count value, wherein the digital representation is based on the third count value, the fourth count value, and the scaling factor.

11. A system for facilitating calibration of an analog-to-digital converter (ADC), the system comprising: an analog-to-digital converter, the analog-to-digital converter being configured to: For each of the multiple time instances: generating a first ramp signal that starts at the time instance relative to a corresponding start of the first counter signal; generating a corresponding first comparator output signal based on the first ramp signal and a first threshold signal, wherein the corresponding first comparator output signal is associated with a first state or a second state; capturing a respective first value of the first ramp signal in response to a transition of the respective first comparator output signal from a first state to a second state; and determining a corresponding second counter value of a second counter signal based on the corresponding first value; and A logic device is configured to determine a scaling factor based on the second counter value and the plurality of time instances, wherein each of the first values ​​is associated with a same first counter value of the first counter signal.

12. The system of claim 11, wherein: The analog-to-digital converter is further configured to: generating a corresponding second ramp signal based on the corresponding first value; and generating a corresponding second comparator output signal based on the corresponding second ramp signal and the second threshold signal, wherein the corresponding second comparator output signal is associated with the third state or the fourth state; and For each time instance of the plurality of time instances, the analog-to-digital converter is configured to determine the respective second counter value by capturing the respective second counter value in response to a transition of the respective second comparator output signal from a third state to a fourth state.

13. The system according to claim 11, wherein: The logic device is further configured to determine a best fit curve based on the second counter value and the plurality of time instances, and wherein the scaling factor is based on the best fit curve.

14. The system of claim 11, further comprising a clock generator circuit configured to generate the first clock and the second clock, wherein The second clock has a faster clock speed than the first clock, wherein the first counter signal is associated with the first clock, and wherein the second counter signal is associated with the second clock.

15. The system according to claim 14, wherein: The scaling factor is also based on the first clock and the second clock.

16. The system according to claim 11, wherein For at least one time instance of the plurality of time instances: the first comparator output signal transitions from a first state to a second state between the start of a first clock cycle and the start of a second clock cycle that is adjacent in time to the first clock cycle, The corresponding first value indicates the value of the first ramp signal at the beginning of the second clock cycle, and The first counter value is associated with the second clock cycle.

17. The system according to claim 16, wherein: A third counter value is associated with the first clock cycle, and wherein the first counter value and the third counter value are consecutive integers.

18. The system of claim 11, further comprising an image sensor device configured to receive electromagnetic radiation and generate a detector signal based on the electromagnetic radiation, wherein The logic device is further configured to determine a digital representation of the detector signal based on the scaling factor.

19. The system according to claim 18, wherein: The digital representation includes a coarse count value associated with the first counter signal and a fine count value associated with the second counter signal, and wherein the logic device is further configured to: applying the scaling factor to the coarse count value to obtain a scaled coarse count value; and A total count value associated with the detector signal is generated based on a sum of the scaled coarse count value and the fine count value.

20. The system of claim 18, wherein: The scaling factor is associated with a column of detectors of the image sensor device.

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