A logic truth table acquisition method and device, electronic equipment and storage medium

Abstract

The application relates to a logic truth table acquisition method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. The logic truth table acquisition method comprises the following steps: finding a register array from a netlist, wherein the register array comprises a plurality of registers; finding an enabling signal for controlling each register from the netlist; changing the value of an address control signal, and obtaining a logic truth table based on each enabling signal under different address control signals, wherein the logic truth table comprises the corresponding relationship between each enabling signal and the address control signal, and is used for determining the register corresponding to each enabling signal. The method can automatically find the enabling signal related to the register array from the netlist, change the value of the address control signal, obtain the logic truth table based on each enabling signal under different address control signals, and improve the problems of low efficiency and easy errors in manually acquiring the logic truth table of the register array.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuits, and particularly relates to a logic truth table acquisition method and device, electronic equipment and a storage medium. BACKGROUND

[0002] With the popularity and application of large-scale integrated circuits, the chip area should be reduced as much as possible, and the cost should be reduced. With the continuous reduction of process size, the cost increases exponentially, and the advantage of reducing the area is increasingly prominent. Today, the storage unit on the system on chip (SOC) accounts for 70% to 80% of the area, or even more, and reducing the area of the storage unit can greatly reduce the area of the chip and reduce the cost. The register matrix storage has the characteristics of fast speed, small area and the like compared with the memory storage, and is more and more widely used.

[0003] Currently, the logic truth table of the register array in the chip is mainly obtained by manual means. However, for high-performance chips (the depth of the register array (m*n) in the high-performance chip is very deep), although the manual method of obtaining the logic truth table is feasible, the workload is large and errors are easy to occur. SUMMARY

[0004] In view of this, the purpose of the present application is to provide a logic truth table acquisition method and device, electronic equipment and a storage medium to improve the problems of low efficiency and easy errors in manually obtaining the logic truth table of the register array.

[0005] Embodiments of the present application are implemented as follows:

[0006] In a first aspect, the embodiments of the present application provide a logic truth table acquisition method, comprising: finding a register array from a netlist, the register array comprising a plurality of registers; finding an enable signal for controlling each register from the netlist, the enable signal being controlled by an address control signal; changing the value of the address control signal, and obtaining a logic truth table based on each enable signal under different address control signals, the logic truth table containing the correspondence between each enable signal and the address control signal, and being used to determine the register corresponding to each enable signal.

[0007] In the embodiments of the present application, the register array is automatically found from the netlist, then the enable signals for controlling the registers in the register array are found, the values of the address control signals are automatically changed, and the logic truth table is obtained based on the enable signals under different address control signals, so that the logic truth table can be quickly obtained. Since the whole process is automatically performed by the machine according to the script without human intervention, the problems of low efficiency and easy error in manually obtaining the logic truth table of the register array are improved. Since the depth m of the register array (m*n) is very deep, although the manual method is feasible, the workload is large and errors are easy to occur.

[0008] In a possible implementation of the first aspect, the register array is found from the netlist, including: finding the register matrix from the netlist based on a register naming rule.

[0009] In the embodiments of the present application, the register matrix in the netlist can be quickly found based on the register naming rule.

[0010] In a possible implementation of the first aspect, the register array is connected with the ICG, and the enable signals for controlling the registers are found from the netlist, including: finding the clock pin PIN of each register in the register matrix; finding the ICG connected with each clock pin PIN from the netlist; and finding the enable signal of each ICG in the netlist.

[0011] In the embodiments of the present application, after the register array is found, the ICG can be found through the clock pin PIN of each register, so that the corresponding enable signal can be quickly and accurately obtained.

[0012] In a possible implementation of the first aspect, the register array is connected with the selector, and the enable signals for controlling the registers are found from the netlist, including: finding the data input pin PIN of each register in the register matrix; finding the selector connected with each data input pin PIN from the netlist; and finding the enable signal of each selector in the netlist.

[0013] In the embodiments of the present application, after the register array is found, the selector can be found through the data input pin PIN of each register, so that the corresponding enable signal can be quickly and accurately obtained.

[0014] In a possible implementation of the first aspect, the method for finding the enable signals for controlling the registers from the netlist comprises: finding a clock pin PIN of each register in the register matrix; determining whether an ICG connected to each clock pin PIN can be found from the netlist; and when an ICG connected to each clock pin PIN can be found from the netlist, finding an enable signal of each ICG in the netlist.

[0015] In a possible implementation of the first aspect, when an ICG connected to each clock pin PIN cannot be found from the netlist, the method further comprises: finding a selector connected to a data input pin PIN of each register from the netlist; and finding an enable signal of each selector in the netlist.

[0016] In a possible implementation of the first aspect, the address control signals are also used to control the logical addresses of the register array; and the logical truth table is obtained based on the enable signals under different address control signals, which comprises: obtaining the logical truth table based on a preset data write function, the enable signals under different address control signals, and the logical addresses.

[0017] In the embodiments of the present application, the preset data write function comprises a write condition and a write address. Since the data write function is determined by a function composed of the write condition (enable signal) and the write address (one of the logical addresses), the data can be written into the register only when the write condition and the write address both meet the requirements. In the case that the data is successfully written into the register, the address control signals meeting the requirements can be deduced based on the function, and then the logical truth table can be obtained.

[0018] In a possible implementation of the first aspect, the address control signals comprise k-bit binary signals, k is an integer greater than or equal to 1, and the k-bit binary signals correspond to 2 k k enable signals; the value of the address control signals is changed, and the logical truth table is obtained based on the enable signals under different address control signals, which comprises: increasing or decreasing the value of the k-bit binary signals one by one, and obtaining the logical truth table according to the change of the 2 k k enable signals.

[0019] In the embodiments of the present application, the value of the k-bit binary signals is increased or decreased one by one, and the enable signals in which the value changes are observed from the 2 k k enable signals, and then the logical truth table is obtained according to the 2 kThe change of the enable signals can quickly obtain the logic truth table. In a second aspect, the embodiments of the present application further provide a logic truth table acquisition device, comprising: an acquisition module and a processing module; the acquisition module is configured to find a register array from a netlist, the register array comprising a plurality of registers, and find an enable signal for controlling each register from the netlist, the enable signal being controlled by an address control signal; the processing module is configured to change the value of the address control signal, and obtain a logic truth table based on each enable signal under different address control signals, the logic truth table comprising the correspondence between each enable signal and the address control line.

[0020] In a third aspect, the embodiments of the present application further provide an electronic device, comprising: a memory and a processor, the processor being connected with the memory; the memory is configured to store a program; the processor is configured to invoke the program stored in the memory to execute the method provided in the first aspect and / or any possible implementation manner in combination with the first aspect.

[0021] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, having a computer program stored thereon, when the computer program is run by a processor, the method provided in the first aspect and / or any possible implementation manner in combination with the first aspect is executed. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor. Through the drawings shown, the above and other purposes, features and advantages of the present application will be more clear. The same reference signs in all the drawings indicate the same parts. The drawings are not necessarily drawn in proportion to the actual size, and the emphasis is on showing the main principles of the present application.

[0023] Figure 1 A flowchart of a logic truth table acquisition method provided by an embodiment of the present application is shown.

[0024] Figure 2 A principle diagram of a selector connected with a register provided by an embodiment of the present application is shown.

[0025] Figure 3 A principle diagram of an ICG connected with a register provided by an embodiment of the present application is shown.

[0026] Figure 4A principle diagram showing that an ICG is connected with a register array is shown.

[0027] Figure 5 A module block diagram of a logic truth table acquisition device is shown.

[0028] Figure 6 A structure diagram of an electronic device is shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0030] It should be noted that similar reference numerals and letters refer to similar items in the following drawings, and therefore, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the relationship terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0031] Furthermore, the term "and / or" in the present application is only used to describe the association relationship of the associated objects, and represents that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone.

[0032] In order to quickly obtain the logic truth table of the register array, the present application provides a logic truth table acquisition method, which will be described below with reference to the drawings. Figure 1 The logic truth table acquisition method provided by the present application will be described.

[0033] S1: Find the register array from the netlist.

[0034] In circuit design, the netlist is a text file used to describe the connection relationship between circuit elements, which is well known in the art and will not be introduced here.

[0035] When the register array is found from the netlist, in one embodiment, the register matrix can be found from the netlist based on the register naming rule (belonging to the regular expression), and the register array includes a plurality of registers. Taking a 128*32 register array as an example, the register naming rule corresponding to the register array can be shown in Table 1.

[0036] Table 1

[0037] Reg-0-0 Reg-0-1 Reg-0-2 …… Reg-0-31 Reg-1-0 Reg-1-1 Reg-1-2 …… Reg-1-31 …… …… …… …… …… Reg-127-0 Reg-127-1 Reg-127-2 …… Reg-127-31

[0038] The register array in the netlist can be found by finding the register whose naming rule conforms to the register naming rule shown in Table 1 from the netlist.

[0039] It can be understood that other ways can be used to find the register array in the netlist, and are not limited to the naming rule described above. Any way that can find the register array from the netlist can be used.

[0040] S2: Find the enable signal for controlling each register from the netlist, and the enable signal is controlled by the address control signal.

[0041] After the register array is found, the enable signal (Enable) for controlling each register needs to be further found from the netlist, and the enable signal is used to control or enable the corresponding register and is controlled by the address control signal. The address control signal includes a k-bit binary signal, and k is an integer greater than or equal to 1. The k-bit binary signal corresponds to 2kenable signals. k

[0042] There are mainly two ways to control or enable the register at present, one is based on ICG (Integrated Clock Gate), and the other is based on a selector.

[0043] If the register array is connected to the selector, the specific process of S2 can be: first, find the data input pin PIN (D end) of each register in the register matrix, then find the selector connected to each data input pin PIN from the netlist, and then find the enable signal (also called selection signal, used to control the output of the selector) of the selector connected to each data input pin PIN in the netlist. In one embodiment, each register in the register array corresponds to a selector, and different registers correspond to different selectors, and the schematic diagram is shown in FIG. 2. Figure 2 When Enable = 1, DoutN = DinN-1 (indicating that the output at the Nth moment is the same as the input at the N-1th moment); when Enable = 0, DoutN = DoutN-1 (indicating that the output at the Nth moment is the same as the output at the N-1th moment).

[0044] ​If the register array is known to be connected with ICG, the specific process of S2 can be: first finding the clock pin PIN of each register in the register matrix, then finding the ICG connected with each clock pin PIN in the netlist, and then finding the enable signal of the ICG connected with each clock pin PIN in the netlist (for controlling the opening or closing of the ICG). In this implementation, each register in the register array corresponds to an ICG, and registers in the same row correspond to the same ICG, as shown in the schematic diagram of FIG. 1. Figure 3 By adding the ICG before the clock input of the register, it is no longer the case that each register corresponds to a selector, but a row of registers corresponds to an ICG, so that the register has no clock when it does not need to flip, thereby reducing the power consumption of the chip and reducing the area of the chip.

[0045] In the case where the connection mode of the register array is unknown, the specific process of S2 can be: finding the clock pin PIN of each register in the register matrix, judging whether the ICG connected with each clock pin PIN can be found in the netlist; when the ICG connected with each clock pin PIN can be found in the netlist, finding the enable signal of each ICG in the netlist. When the ICG connected with each clock pin PIN cannot be found in the netlist, the method further includes finding the selector connected with the data input pin PIN of each register in the netlist, and finding the enable signal of each selector in the netlist.

[0046] S3: changing the value of the address control signal, and obtaining a logic truth table based on each enable signal under different address control signals.

[0047] After the enable signal (the enable signal of the ICG or the enable signal of the selector) for controlling each register is found in the netlist, the value of the address control signal can be changed, and a logic truth table can be obtained based on each enable signal under different address control signals, wherein the logic truth table contains the correspondence between each enable signal (Enable) and the address control signal. The address control signal can also be used to control the logical address (such as the write address) of the register in the register array, wherein the logical address corresponds to the enable signal of the register one by one.

[0048] In an implementation, the logic truth table is shown in Table 2. It can be understood that only k=7 is taken as an example here. The value of k is not limited to this.

[0049] Table 2

[0050] Add_6 Add_5 Add_4 Add_3 Add_2 Add_1 Add_0 WriteEnable Enable0 0 0 0 0 0 0 0 1 Enable1 0 0 0 0 0 0 1 1 Enable2 0 0 0 0 0 1 0 1 …… …… …… …… …… …… …… …… …… Enable127 1 1 1 1 1 1 1 1

[0051] The Add_6-Add_0 are binary 7-bit address control signals, which are used to generate a logical address (Addressi) of the register, and the logical address can be used as a write address or a read address. For example, the Add_6-Add_0 of 0000000 corresponds to the logical address 0, the Add_6-Add_0 of 0000001 corresponds to the logical address 1, and so on, and the Add_6-Add_0 of 1111111 corresponds to the logical address 127. At the same time, only one of the 128 enable signals has a value of 1.

[0052] In one embodiment, the implementation process of the S3 can be: sequentially increasing or decreasing the value of the k-bit binary signal, and determining the order of each bit in the k-bit binary signal according to the change of the 2 k k enable signals, and then obtaining the logical truth table. Taking the above 7-bit binary signal as an example, the value of at least one bit in the 7-bit binary address control signal is changed each time, and then it is observed which of the 128 enable signals has a value change, and the operation is repeated multiple times, so as to determine the order of each bit in the 7-bit address control signal from high to low, and thus obtain the logical truth table as shown in Table 1. Based on the logical truth table, it can be determined which bit in the address control signal is the high bit, which bit is the low bit, and which bits are the middle bits.

[0053] In another embodiment, when obtaining the logical truth table based on each enable signal under different address control signals, the logical truth table can be obtained based on a preset data write function, each enable signal under different address control signals, and a logical address. For example, when simulating the writing of data into the register, based on the preset data write function, the address control signal meeting the requirement can be deduced according to the condition of writing data into the register, so as to determine the order of each bit in the address control signal, and then obtain the logical truth table.

[0054] The preset data write function can be represented as RegArray(i, n) = Datai(conditioni, cmdi), wherein the conditioni corresponds to the write address Addressi, and the cmdi corresponds to the enable signal Enablei. Only when the conditioni and the cmdi both meet the data write requirement, the data Datai can be written into the register array RegArray(i, n), and the value of i is 0-m. For the register array, the data write function is determined by a function composed of a write condition and a write address, and the function is a function of the enable signal meeting the write condition. In the case of successfully writing data into the register, based on the function, the address control signal meeting the above requirement can be deduced, the order of each bit in the address control signal can be determined, and then the logical truth table can be obtained.

[0055] wherein m is the depth of the register array, and n is the data width of the register array. In order to write input data with width n into the register array RegArray(i, n), the input write address Address = i must be satisfied, and the ICG of the clock connected to RegArray(i, n) must satisfy Enablei = WriteEnable = 1'b1.

[0056] Taking a 128*32 register array as shown in Figure 4 , for example, 32(n) registers in each row are controlled by the same ICG, and a total of 128 ICGs (Enable0-Enable127) are included. It can be understood that if a selector is used for control, then each register corresponds to a selector. At this time, Figure 4 The correspondence between the ICGs in

[0057] ICG0->RegArray(0, n)->Address = 0;

[0058] ICG1->RegArray(1, n)->Address = 1;

[0059] ICG2->RegArray(2, n)->Address = 2;

[0060] ...

[0061] ICGi->RegArray(i, n)->Address = i;

[0062] ...

[0063] ICG127->RegArray(127, n)->Address = 127.

[0064] wherein the n registers in the same row have the same logical address, and through the above method, the logical truth table of the register matrix can be quickly found.

[0065] Based on the same inventive concept, an embodiment of the present application also provides a logic truth table acquisition device 100, as shown in Figure 5 . The logic truth table acquisition device 100 comprises an acquisition module 110 and a processing module 120.

[0066] The acquisition module 110 is configured to find a register array from a netlist, wherein the register array comprises a plurality of registers; and find an enable signal for controlling each register from the netlist, wherein the enable signal is controlled by an address control signal.

[0067] The processing module 120 is configured to change the value of the address control signal, and obtain a logic truth table based on each enable signal under different address control signals, wherein the logic truth table comprises a corresponding relationship between each enable signal and the address control line.

[0068] Optionally, the acquisition module 110 is configured to find the register matrix from the netlist based on a register naming rule.

[0069] If the register array is connected with the ICG, the acquisition module 110 is configured to find a clock pin PIN of each register in the register matrix, find an ICG connected with each clock pin PIN from the netlist, and find an enable signal of each ICG in the netlist.

[0070] If the register array is connected with the selector, the acquisition module 110 is configured to find a data input pin PIN of each register in the register matrix, find a selector connected with each data input pin PIN from the netlist, and find an enable signal of each selector in the netlist.

[0071] Optionally, the acquisition module 110 is configured to find a clock pin PIN of each register in the register matrix, determine whether an ICG connected with each clock pin PIN can be found from the netlist, find an enable signal of each ICG in the netlist when the ICG connected with each clock pin PIN can be found from the netlist, find a selector connected with a data input pin PIN of each register from the netlist when the ICG connected with each clock pin PIN cannot be found from the netlist, and find an enable signal of each selector in the netlist.

[0072] The address control signal is also used to control a logic address of the register array, and the processing module 120 is configured to obtain a logic truth table based on a preset data write function function, each enable signal under different address control signals, and the logic address.

[0073] The address control signal comprises a k-bit binary signal, k is an integer greater than or equal to 1, and the k-bit binary signal corresponds to two k enable signals; the processing module 120 is configured to sequentially increase or decrease the value of the k-bit binary signal, and obtain the logic truth table according to the change of the two k enable signals.

[0074] The logic truth table acquisition device 100 provided in the embodiments of the present application has the same implementation principle and technical effects as the foregoing method embodiments, and for brevity of description, the part not mentioned in the device embodiment can be referred to the corresponding content in the foregoing method embodiments.

[0075] AsFigure 6 As shown, Figure 6 This diagram illustrates a structural block diagram of an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0076] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, such as... Figure 5 The software functional module shown is the logic truth table acquisition device 100. The logic truth table acquisition device 100 includes at least one software functional module that can be stored as software or firmware in the memory 220 or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute executable modules stored in the memory 220, such as the software functional module or computer program included in the logic truth table acquisition device 100. For example, the processor 240 is used to find a register array from a netlist, the register array including multiple registers; find enable signals from the netlist for controlling each register, the enable signals being controlled by address control signals; change the value of the address control signals, and based on each enable signal under different address control signals, obtain a logic truth table, the logic truth table containing the correspondence between each enable signal and the address control signal, used to determine the register corresponding to each enable signal.

[0077] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0078] The processor 240 can be an integrated circuit chip with processing capability. The above processor can be a general purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; also can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The methods, steps and logical block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general purpose processor can be a microprocessor or the processor 240 can also be any conventional processor or the like.

[0079] The electronic device 200 described above includes but is not limited to a mobile phone, a tablet, a computer, a server, etc.

[0080] The embodiments of the present application also provide a non-volatile computer readable storage medium (hereinafter referred to as storage medium) having a computer program stored thereon, wherein the computer program is run by a computer such as the electronic device 200 described above, and executes the logical truth table acquisition method shown above.

[0081] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the embodiments can be referred to each other.

[0082] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and block diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementation manners, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0083] In addition, the function modules in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0084] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a computer readable storage medium, includes several instructions for causing a computer device (which can be a personal computer, a notebook computer, a server, or an electronic device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned computer readable storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0085] The above is merely a specific implementation manner of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for obtaining a logical truth table, characterized in that, include: Locate the register array, which comprises multiple registers, from the netlist; The enable signals used to control each register are located in the netlist. These enable signals are controlled by address control signals, which consist of k-bit binary signals, where k is an integer greater than or equal to 1, corresponding to 2^k bits. k Two enable signals, at the same time 2 k Only one enable signal is valid. The value of the address control signal is changed, and a logical truth table is obtained based on each enable signal under different address control signals; the logical truth table contains the correspondence between each enable signal and the address control signal, and is used to determine the register corresponding to each enable signal.

2. The method according to claim 1, characterized in that, Locate the register array from the netlist, including: The register array is located from the netlist based on the register naming rules.

3. The method according to claim 1, characterized in that, The register array is connected to the ICG; the enable signals for controlling each register are found from the netlist, including: Locate the clock pin PIN of each register in the register array; Locate the ICG connected to each clock pin from the netlist; Locate the enable signal for each ICG in the netlist.

4. The method according to claim 1, characterized in that, The register array is connected to the selector; the enable signals for controlling each register are found from the netlist, including: Locate the data input pin (PIN) of each register in the register array; Locate the selector connected to each data input pin from the netlist; Locate the enable signal for each selector in the netlist.

5. The method according to claim 1, characterized in that, Locate the enable signals used to control each register from the netlist, including: Locate the clock pin PIN of each register in the register array; Determine if the ICG connected to each clock pin can be found in the netlist; When an ICG connected to each clock pin PIN can be found in the netlist, locate the enable signal for each ICG in the netlist.

6. The method according to claim 5, characterized in that, When the ICG connected to each clock pin cannot be found in the netlist, the method further includes: Locate the selector connected to the data input pin of each register from the netlist; Locate the enable signal for each selector in the netlist.

7. The method according to any one of claims 1-6, characterized in that, The address control signal is also used to control the logical address of the register array; a logical truth table is obtained based on each enable signal under different address control signals, including: Based on the preset data write function and the various enable signals and logical addresses under different address control signals, a logical truth table is obtained.

8. The method according to any one of claims 1-6, characterized in that, By changing the value of the address control signal and obtaining a logical truth table based on each enable signal under different address control signals, including: The value of the k-bit binary signal is increased or decreased sequentially, and according to the 2 k The logic truth table is obtained by analyzing the changes in each enable signal.

9. A logic truth table acquisition device, characterized in that, include: The acquisition module is used to find a register array from the netlist, the register array including multiple registers, and to find enable signals from the netlist for controlling each register. The enable signals are controlled by address control signals, which include k-bit binary signals, where k is an integer greater than or equal to 1, corresponding to 2^k bits. k Two enable signals, at the same time 2 k Only one enable signal is valid. The processing module is used to change the value of the address control signal and obtain a logic truth table based on each enable signal under different address control signals. The logic truth table contains the correspondence between each enable signal and the address control line, and is used to determine the register corresponding to each enable signal.

10. An electronic device, characterized in that, include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-8.

11. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, performs the method as described in any one of claims 1-8.

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