Pixel circuit and pixel circuit driving method

Abstract

The present application provides a pixel circuit and a driving method thereof, comprising: a signal write control subcircuit, a reset subcircuit, a voltage compensation subcircuit, a driving subcircuit, and a light-emitting device; the signal write control subcircuit is connected to the reset subcircuit and the voltage compensation subcircuit, respectively; the reset subcircuit and the voltage compensation subcircuit are connected to the driving subcircuit, respectively; the driving subcircuit is connected to the light-emitting device; the reset subcircuit is configured to reset the control terminal of the driving subcircuit when a reset signal is input to the signal write control subcircuit; the voltage compensation subcircuit is configured to perform voltage compensation on the data signal at the control terminal of the driving subcircuit when a data signal is input to the signal write control subcircuit. By performing voltage compensation on the data signal at the control terminal of the driving subcircuit by the voltage compensation subcircuit, the afterimage phenomenon of the displayed image can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a driving method for the pixel circuit. Background Art

[0002] In existing display technology, regardless of the type of transistor, the threshold voltage is unstable. Under long-term pressure and high temperature, the threshold voltage will drift. Due to different display images, the threshold drift of transistors in different parts of the display panel is different, which will cause differences in display brightness, often appearing as ghosting, which is commonly known as afterimage. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a pixel circuit and a driving method for the pixel circuit to reduce the afterimage phenomenon of the display screen. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a pixel circuit, the circuit comprising:

[0005] Signal writing control subcircuit, reset subcircuit, voltage compensation subcircuit, driving subcircuit and light emitting device;

[0006] The signal writing control subcircuit is connected to the reset subcircuit and the voltage compensation subcircuit respectively, the reset subcircuit and the voltage compensation subcircuit are connected to the driving subcircuit respectively, and the driving subcircuit is connected to the light-emitting device;

[0007] The reset sub-circuit is configured to reset the control terminal of the driving sub-circuit when the signal writing control sub-circuit inputs a reset signal;

[0008] The voltage compensation sub-circuit is used to perform voltage compensation on the data signal at the control end of the driving sub-circuit when the signal writing control sub-circuit inputs a data signal.

[0009] In one possible implementation, the signal writing control subcircuit includes a first transistor, the reset subcircuit includes a third transistor, the voltage compensation subcircuit includes a second transistor, and the driving subcircuit includes a fourth transistor and a first storage capacitor;

[0010] The gate of the first transistor is connected to the first gate control signal terminal, the first terminal of the first transistor is connected to the signal voltage input terminal, and the second terminal of the first transistor is connected to the second terminal of the second transistor and the first terminal of the third transistor respectively;

[0011] The gate of the second transistor is connected to the first end of the second transistor, and the first end of the second transistor is respectively connected to the gate of the fourth transistor, the first end of the first storage capacitor, and the second end of the third transistor;

[0012] The gate of the third transistor is connected to the first end of the third transistor;

[0013] The first terminal of the fourth transistor is connected to the cathode of the light emitting device, and the anode of the light emitting device is connected to the power supply voltage terminal;

[0014] The second end of the fourth transistor is connected to the second end of the first storage capacitor and the negative end of the power supply respectively.

[0015] In a possible implementation manner, a threshold voltage of the second transistor is equal to a threshold voltage of the fourth transistor.

[0016] In one possible embodiment, the circuit includes at least two driving sub-circuits, and the circuit also includes at least two gate control sub-circuits; the gate control sub-circuits correspond one-to-one to the driving sub-circuits; for each driving sub-circuit, the driving sub-circuit is respectively connected to the reset sub-circuit and the voltage compensation sub-circuit through the gate control sub-circuit corresponding to the driving sub-circuit.

[0017] In one possible implementation, the first gate control subcircuit includes a fifth transistor, the first driver subcircuit includes a fourth transistor and a first storage capacitor; the second gate control subcircuit includes a sixth transistor, the second driver subcircuit includes a seventh transistor and a second storage capacitor; the signal write control subcircuit includes a first transistor, the reset subcircuit includes a third transistor, and the voltage compensation subcircuit includes a second transistor;

[0018] The gate of the first transistor is connected to the scan signal terminal, the first terminal of the first transistor is connected to the signal voltage input terminal, and the second terminal of the first transistor is connected to the second terminal of the second transistor and the first terminal of the third transistor respectively;

[0019] The gate of the second transistor is connected to the first end of the second transistor, and the first end of the second transistor is connected to the first end of the fifth transistor and the first end of the sixth transistor respectively;

[0020] The gate of the third transistor is connected to the first end of the third transistor, and the second end of the third transistor is connected to the first end of the fifth transistor and the first end of the sixth transistor respectively;

[0021] The gate of the fifth transistor is connected to the first gate control signal terminal, and the second terminal of the fifth transistor is connected to the gate of the fourth transistor and the first terminal of the first storage capacitor respectively;

[0022] The gate of the sixth transistor is connected to the second gate control signal terminal, and the second terminal of the sixth transistor is connected to the gate of the seventh transistor and the first terminal of the second storage capacitor respectively.

[0023] In a possible implementation, the threshold voltage of the second transistor is equal to the threshold voltage of the fourth transistor, and the threshold voltage of the second transistor is equal to the threshold voltage of the seventh transistor.

[0024] In a second aspect, an embodiment of the present application provides a method for driving a pixel circuit, for driving the pixel circuit described in any one of the first aspects above, the method comprising:

[0025] In the reset phase, the control terminal of the signal writing control subcircuit inputs a first valid enable signal, and the data terminal of the signal writing control subcircuit inputs a reset signal;

[0026] In the data writing phase, the control terminal of the signal writing control subcircuit inputs a first valid enable signal, and the data terminal of the signal writing control subcircuit inputs a data signal;

[0027] The first valid enable signal, the reset signal, and the data signal have the same positive and negative polarities, and an absolute value of a voltage of the reset signal is greater than an absolute value of a voltage of the data signal.

[0028] In a possible implementation, for each gate control sub-circuit, during the reset phase and the data writing phase of the pixel row to which the gate control sub-circuit belongs, the control terminal of the gate control sub-circuit inputs the second valid enable signal;

[0029] The first valid enable signal, the second valid enable signal, the reset signal and the data signal have the same positive and negative polarities.

[0030] In a third aspect, an embodiment of the present application provides a display substrate, comprising:

[0031] A pixel circuit as described in any one of the first aspects above.

[0032] In a fourth aspect, an embodiment of the present application provides a display device, comprising:

[0033] The display substrate as described in the third aspect above.

[0034] Beneficial effects of the embodiments of the present application:

[0035] An embodiment of the present application provides a pixel circuit and a driving method for the pixel circuit, comprising: a signal write control subcircuit, a reset subcircuit, a voltage compensation subcircuit, a driving subcircuit, and a light-emitting device; the signal write control subcircuit is respectively connected to the reset subcircuit and the voltage compensation subcircuit, the reset subcircuit and the voltage compensation subcircuit are respectively connected to the driving subcircuit, and the driving subcircuit is connected to the light-emitting device; the reset subcircuit is configured to reset the control terminal of the driving subcircuit when a reset signal is input to the signal write control subcircuit; the voltage compensation subcircuit is configured to perform voltage compensation on the data signal at the control terminal of the driving subcircuit when a data signal is input to the signal write control subcircuit. By performing voltage compensation on the data signal at the control terminal of the driving subcircuit by the voltage compensation subcircuit, the afterimage phenomenon of the displayed image can be reduced.

[0036] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0038] Figure 1 Schematic diagram of an OLED pixel circuit in related art;

[0039] Figure 2 A schematic diagram of an external compensation pixel circuit in the related art;

[0040] Figure 3 A schematic diagram of a first structure of a pixel circuit provided in an embodiment of the present application;

[0041] Figure 4 A second structural diagram of a pixel circuit provided in an embodiment of the present application;

[0042] Figure 5a A third structural schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0043] Figure 5b A fourth structural schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0044] Figure 6 for Figure 4 The timing diagram corresponding to the pixel circuit shown;

[0045] Figure 7a for Figure 4 Schematic diagram of the pixel circuit in the reset phase;

[0046] Figure 7b for Figure 4 Schematic diagram of the pixel circuit in the data writing stage;

[0047] Figure 8 for Figure 5b The timing diagram corresponding to the pixel circuit shown. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0049] First, a brief description of the OLED (Organic Light-Emitting Diode) pixel circuit in the related art is given. Figure 1 Figure 1 shows an OLED pixel circuit in related art. The power supply voltage VDD continuously provides operating voltage to the OLED. The current flowing through the OLED is controlled by the gate voltage of transistor T1, which is written by the data signal Vdata and stored in capacitor C1, ensuring continuous light emission during a scanning cycle. The current flowing through the OLED is controlled by T1 and satisfies the following formula: Ids = 1 / 2*W / L*μ*Cox*(Vgs-|Vth|). 2 .

[0050] Where Ids is the current flowing through the OLED, W and L are the width and length of the T1 channel, μ is the effective carrier mobility, Cox is the capacitance per unit area of the gate oxide layer, Vth is the threshold voltage of T1, and Vgs is the gate-source voltage of T1.

[0051] Under current process conditions, all transistors experience unstable threshold voltages. Under prolonged pressure and high temperatures, the threshold voltage will drift. Due to varying display screens, the threshold drift of transistors in different parts of the display panel can cause variations in display brightness, often manifesting as image sticking, commonly known as afterimages. Therefore, compensation technology is needed in pixel circuit design to address this issue.

[0052] like Figure 2As shown in the figure, it is an external compensation pixel circuit in the related art, which consists of 3 transistors and 1 storage capacitor, so it is referred to as a 3T1C structure. In addition to the traditional data line (Data line), the 3T1C external compensation pixel circuit also has a sensing line (Sense line) that can extract the current of the transistor T1 or OLED into the driver chip. There are two ways to extract electrical signals: one is to extract the current of the transistor T1, which is called TFT sensing (Thin Film Transistorsensing, thin film field effect transistor sensing method), and the other is to extract the current of the OLED, which is called OLED sensing (organic light-emitting diode sensing method). The basic principle is to give a driving voltage to the transistor T1 or OLED, and extract the current into the driver chip through the sensing line.

[0053] After reading the current signal, external compensation uses an external integrated circuit chip to compensate for non-uniformities in transistor threshold voltage and mobility, as well as OLED aging. The technical difficulty of external compensation lies in the need for high-precision and high-speed reading of electrical parameters. Parasitic effects on the sensing lines can affect reading speed and cause signal attenuation. Errors in the sensing circuit can cause output distortion. Noise from adjacent sensing lines or the external environment can interfere with the accuracy of the sensing signal. Furthermore, external compensation is costly, which in turn leads to higher costs for the display panel.

[0054] In order to reduce the afterimage phenomenon of the display screen without increasing the cost of the display panel, the embodiments of the present application provide a pixel circuit and a driving method of the pixel circuit.

[0055] Next, a pixel circuit 1 provided in an embodiment of the present application is described in detail. Figure 3 , the circuit includes: a signal writing control subcircuit 11, a reset subcircuit 12, a voltage compensation subcircuit 13, a driving subcircuit 14 and a light emitting device 15;

[0056] The signal writing control subcircuit 11 is connected to the reset subcircuit 12 and the voltage compensation subcircuit 13 respectively. The reset subcircuit 12 and the voltage compensation subcircuit 13 are connected to the driving subcircuit 14 respectively. The driving subcircuit 14 is connected to the light emitting device 15.

[0057] The reset sub-circuit 12 is used to reset the control terminal of the driving sub-circuit 14 when the signal writing control sub-circuit 11 inputs the reset signal Vref;

[0058] The voltage compensation sub-circuit 13 is configured to perform voltage compensation on the data signal at the control end of the driving sub-circuit 14 when the signal writing control sub-circuit 11 inputs the data signal Vdata.

[0059] The type of the light-emitting device can be customized according to actual conditions. In one possible implementation, the light-emitting device is an OLED.

[0060] In the embodiment of the present application, the voltage compensation sub-circuit performs voltage compensation on the data signal of the control terminal of the driving sub-circuit, thereby reducing the ghosting phenomenon of the display screen.

[0061] In one possible implementation, see Figure 4 , the signal writing control sub-circuit 11 includes a first transistor T1, the reset sub-circuit 12 includes a third transistor T3, the voltage compensation sub-circuit 13 includes a second transistor T2, and the driving sub-circuit 14 includes a fourth transistor T4 and a first storage capacitor C1;

[0062] The gate of the first transistor T1 is connected to the first gate control signal terminal Gate(n), the first terminal of the first transistor T1 is connected to the signal voltage input terminal Data, and the second terminal of the first transistor T1 is connected to the second terminal of the second transistor T2 and the first terminal of the third transistor T3 respectively;

[0063] The gate of the second transistor T2 is connected to the first end of the second transistor T2, and the first end of the second transistor T2 is respectively connected to the gate of the fourth transistor T4, the first end of the first storage capacitor C1, and the second end of the third transistor T3;

[0064] The gate of the third transistor T3 is connected to the first end of the third transistor T3;

[0065] The first end of the fourth transistor T4 is connected to the cathode of the light emitting device OLED, and the anode of the light emitting device OLED is connected to the power supply voltage terminal VDD;

[0066] The second end of the fourth transistor T4 is connected to the second end of the first storage capacitor C1 and the negative power supply terminal VSS respectively.

[0067] In a possible implementation manner, the threshold voltage of the second transistor T2 is equal to the threshold voltage of the fourth transistor T4.

[0068] The signal voltage input terminal Data can output a reset signal Vref or a data signal Vdata. When the reset signal Vref is input to the first transistor T1, the third transistor T3 is turned on, resetting the gate of the fourth transistor T4. When the data signal Vdata is input to the first transistor T1, the second transistor T2 is turned on, performing voltage compensation on the data signal Vdata written to the gate of the fourth transistor T4. That is, by making the threshold voltage of the second transistor T2 equal to the threshold voltage of the fourth transistor T4, the threshold voltage is offset, eliminating the impact of the threshold voltage on the display image.

[0069] It should be noted that the "equal" in the threshold voltage of the second transistor T2 being equal to the threshold voltage of the fourth transistor T4 does not mean completely equal in the conventional sense. Instead, it means that in the process flow, the size of T2 is designed to be consistent with the size of T4, and T2 is as close to T4 as possible in the backplane layout, so that the threshold voltage of T2 is basically equal to the threshold voltage of T4, and the temperature influence and drift are also relatively close. Therefore, the threshold voltages cannot be completely offset, but the threshold voltage deviation needs to be limited to a range, which can be ΔVth < 0.5V. That is, when the threshold voltage deviation exceeds a certain range (ΔVth ≥ 0.5V), the current consistency cannot be guaranteed.

[0070] In the embodiment of the present application, the threshold voltage of the second transistor T2 is equal to the threshold voltage of the fourth transistor T4 to perform threshold voltage offset, thereby eliminating the influence of the threshold voltage on the display image, and reducing the afterimage phenomenon of the display image.

[0071] In one possible embodiment, the circuit includes at least two driving sub-circuits, and the circuit also includes at least two gate control sub-circuits; the gate control sub-circuits correspond one-to-one to the driving sub-circuits; for each driving sub-circuit, the driving sub-circuit is respectively connected to the reset sub-circuit and the voltage compensation sub-circuit through the gate control sub-circuit corresponding to the driving sub-circuit.

[0072] In one possible implementation, see Figure 5a , a pixel circuit 1 including two driving sub-circuits and two gate control sub-circuits is used as an example for schematic description.

[0073] In one possible implementation, see Figure 5bThe first gate control subcircuit 16 includes a fifth transistor T5, the first driver subcircuit 14 includes a fourth transistor T4 and a first storage capacitor C1; the second gate control subcircuit 16' includes a sixth transistor T6, the second driver subcircuit 14' includes a seventh transistor T7 and a second storage capacitor C2; the signal write control subcircuit 11 includes a first transistor T1, the reset subcircuit 12 includes a third transistor T3, and the voltage compensation subcircuit 13 includes a second transistor T2;

[0074] The gate of the first transistor T1 is connected to the scan signal terminal Scan(n), the first terminal of the first transistor T1 is connected to the signal voltage input terminal Data, and the second terminal of the first transistor T1 is connected to the second terminal of the second transistor T2 and the first terminal of the third transistor T3 respectively;

[0075] The gate of the second transistor T2 is connected to the first end of the second transistor T2, and the first end of the second transistor T2 is connected to the first end of the fifth transistor T5 and the first end of the sixth transistor T6 respectively;

[0076] The gate of the third transistor T3 is connected to the first end of the third transistor T3, and the second end of the third transistor T3 is connected to the first end of the fifth transistor T5 and the first end of the sixth transistor T6 respectively;

[0077] The gate of the fifth transistor T5 is connected to the first gate control signal terminal Gate(n), and the second terminal of the fifth transistor T5 is connected to the gate of the fourth transistor T4 and the first terminal of the first storage capacitor C1 respectively;

[0078] The gate of the sixth transistor T6 is connected to the second gate control signal terminal Gate(n+1), and the second terminal of the sixth transistor T6 is connected to the gate of the seventh transistor T7 and the first terminal of the second storage capacitor C2 respectively.

[0079] In a possible implementation, the threshold voltage of the second transistor T2 is equal to the threshold voltage of the fourth transistor T4 , and the threshold voltage of the second transistor T2 is equal to the threshold voltage of the seventh transistor T7 .

[0080] The analysis of equal threshold voltages is described above and will not be repeated here.

[0081] It is understandable that it is possible to design two rows of pixels to share the compensation unit (signal writing control subcircuit 11, reset subcircuit 12, voltage compensation subcircuit 13), or it is possible to design three rows of pixels to share the compensation unit (signal writing control subcircuit 11, reset subcircuit 12, voltage compensation subcircuit 13). It is also possible to design multiple rows of pixels to share the compensation unit (signal writing control subcircuit 11, reset subcircuit 12, voltage compensation subcircuit 13) according to actual needs. Figure 5b In the figure, two rows of pixels are used as an example. By controlling the fifth transistor T5 to be turned on and the sixth transistor T6 to be turned off, the gate of the fourth transistor T4 is reset and data is written. By controlling the fifth transistor T5 to be turned off and the sixth transistor T6 to be turned on, the gate of the seventh transistor T7 is reset and data is written.

[0082] In the embodiments of the present application, firstly, by designing a shared compensation unit, multiple rows of pixels can share the same compensation unit, reducing the pixel circuit layout space. Secondly, by setting the threshold voltage of the second transistor T2 equal to the threshold voltage of the transistor in each driver sub-circuit, threshold voltage offset is achieved, eliminating the impact of threshold voltage on the display image and reducing the image sticking phenomenon on the display image.

[0083] An embodiment of the present application further provides a method for driving a pixel circuit, for driving the pixel circuit 1 described in any one of the above embodiments, the method comprising:

[0084] In the reset phase, the control terminal of the signal writing control subcircuit inputs a first valid enable signal, and the data terminal of the signal writing control subcircuit inputs a reset signal;

[0085] In the data writing phase, the control terminal of the signal writing control subcircuit inputs a first valid enable signal, and the data terminal of the signal writing control subcircuit inputs a data signal;

[0086] The first valid enable signal, the reset signal, and the data signal have the same positive and negative polarities, and an absolute value of a voltage of the reset signal is greater than an absolute value of a voltage of the data signal.

[0087] In a possible implementation, for each gate control sub-circuit, during the reset phase and the data writing phase of the pixel row to which the gate control sub-circuit belongs, the control terminal of the gate control sub-circuit inputs the second valid enable signal;

[0088] The first valid enable signal, the second valid enable signal, the reset signal and the data signal have the same positive and negative polarities.

[0089] In the embodiment of the present application, the working state of the pixel circuit at different stages is controlled by inputting different voltage signals at different stages.

[0090] In a possible implementation manner, each transistor is an N-type transistor; the first valid enable signal, the second valid enable signal, the reset signal, and the data signal are all at a high level.

[0091] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all N-type transistors;

[0092] The first end of the first transistor T1 is the drain of the N-type transistor, and the second end of the first transistor T1 is the source of the N-type transistor;

[0093] The first end of the second transistor T2 is the drain of the N-type transistor, and the second end of the second transistor T2 is the source of the N-type transistor;

[0094] The first end of the third transistor T3 is the drain of the N-type transistor, and the second end of the third transistor T3 is the source of the N-type transistor;

[0095] The first end of the fourth transistor T4 is the drain of the N-type transistor, and the second end of the fourth transistor T4 is the source of the N-type transistor;

[0096] The first end of the fifth transistor T5 is the drain of the N-type transistor, and the second end of the fifth transistor T5 is the source of the N-type transistor;

[0097] The first end of the sixth transistor T6 is the drain of the N-type transistor, and the second end of the sixth transistor T6 is the source of the N-type transistor;

[0098] The first end of the seventh transistor T7 is the drain of the N-type transistor, and the second end of the seventh transistor T7 is the source of the N-type transistor;

[0099] It is understood that for any transistor in the circuit of this application, the transistor can be an N-type transistor or a P-type transistor, and the specific selection can be made according to the actual situation; the first end of the transistor is the source or drain, and the second end of the transistor is the drain or source corresponding to the first end. It is understood that the transistor can be a P-type transistor or an N-type transistor, and the specific selection can be made according to the actual situation, but the device connection method of the circuit needs to be adjusted accordingly. Such replacement schemes are still within the scope of protection of this application.

[0100] It can be understood that the transistors used in the circuit of the present application can be MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistors), or TFT tubes (Thin Film Transistors) or other types of transistors. The specific selection can be made according to the actual situation. The replacement scheme is still within the scope of protection of the present application. The connection method of the MOS tube or other types of transistors can refer to the connection method of the TFT tube, which will not be repeated here.

[0101] In the embodiment of the present application, different voltage signals are used to control the switching of each N-type transistor to control different working states of the pixel circuit.

[0102] The driving method of the pixel driving circuit 1 is described in detail below:

[0103] See also Figure 6 ,for Figure 4 The timing diagram corresponding to the pixel circuit shown. In the reset phase, the first gate control signal terminal Gate(n) is at a high level, the first transistor T1 is turned on, the signal voltage input terminal Data inputs the reset signal Vref (high level), the third transistor T3 (Vgs3-Vth3>0) is turned on, the second transistor T2 (Vgs2-Vth2<0) is turned off, and the gate of the fourth transistor T4 is reset through the third transistor T3. Wherein, Vgs3 represents the gate-source voltage of the third transistor T3, Vth3 represents the threshold voltage of the third transistor T3, Vgs2 represents the gate-source voltage of the second transistor T2, and Vth2 represents the threshold voltage of the second transistor T2. Figure 4 The schematic diagram of the pixel circuit in the reset phase is shown as Figure 7a As shown, the potential at point a is Vref-Vth3.

[0104] In the data writing (writing Vdata) stage, the first gate control signal terminal Gate(n) is at a high level, the first transistor T1 is turned on, the signal voltage input terminal Data inputs the data signal Vdata (high level), Vdata<Vref, the third transistor T3 (Vgs3-Vth3<0) is turned off, the second transistor T2 (Vgs2-Vth2>0) is turned on, and the data signal Vdata value is written to the gate of the fourth transistor T4 through the second transistor T2. Figure 4 The schematic diagram of the pixel circuit in the data writing stage is shown as follows Figure 7b As shown, when the potential at point a is Vdata+Vth2, the second transistor T2 is turned off.

[0105] During the light-emitting phase, the current flowing through the OLED is: Ids = 1 / 2*W / L*μ*Cox*(Vgs-Vth4) 2 =1 / 2*W / L*μ*Cox*(Vdata+Vth2-VDD-Vth4) 2 When Vth2 is equal to Vth4, the influence of the threshold voltage on the display image can be eliminated, and the afterimage phenomenon of the display image can be reduced.

[0106] See also Figure 8 ,for Figure 5b The timing diagram corresponding to the pixel circuit shown. During the reset phase of the pixel row to which the fifth transistor T5 belongs, the scan signal terminal Scan(n) is high, the first transistor T1 is turned on, the first gate control signal terminal Gate(n) is high, the fifth transistor T5 is turned on, the second gate control signal terminal Gate(n+1) is low, and the sixth transistor T6 is turned off. The signal voltage input terminal Data inputs the reset signal Vref (high), the third transistor T3 (Vgs3-Vth3>0) is turned on, the second transistor T2 (Vgs2-Vth2<0) is turned off, and the gate of the fourth transistor T4 is reset through the third transistor T3.

[0107] During the data writing phase for the pixel row to which the fifth transistor T5 belongs, the scan signal terminal Scan(n) is high, the first transistor T1 is turned on, the first gate control signal terminal Gate(n) is high, the fifth transistor T5 is turned on, the second gate control signal terminal Gate(n+1) is low, and the sixth transistor T6 is turned off. The signal voltage input terminal Data inputs the data signal Vdata (high), Vdata < Vref, the third transistor T3 (Vgs3 - Vth3 < 0) is turned off, the second transistor T2 (Vgs2 - Vth2 > 0), and the data signal Vdata value is written to the gate of the fourth transistor T4 via the second transistor T2.

[0108] During the reset phase of the pixel row to which the sixth transistor T6 belongs, the scan signal terminal Scan(n) is high, the first transistor T1 is turned on, the first gate control signal terminal Gate(n) is low, the fifth transistor T5 is turned off, the second gate control signal terminal Gate(n+1) is high, and the sixth transistor T6 is turned on. The signal voltage input terminal Data inputs a reset signal Vref (high), the third transistor T3 (Vgs3-Vth3>0) is turned on, the second transistor T2 (Vgs2-Vth2<0) is turned off, and the gate of the seventh transistor T7 is reset via the third transistor T3.

[0109] During the data writing phase for the pixel row to which the sixth transistor T6 belongs, the scan signal terminal Scan(n) is high, the first transistor T1 is turned on, the first gate control signal terminal Gate(n) is low, the fifth transistor T5 is turned off, the second gate control signal terminal Gate(n+1) is high, and the sixth transistor T6 is turned on. The signal voltage input terminal Data inputs the data signal Vdata (high), Vdata < Vref, the third transistor T3 (Vgs3 - Vth3 < 0) is turned off, the second transistor T2 (Vgs2 - Vth2 > 0), and the data signal Vdata value is written to the gate of the seventh transistor T7 via the second transistor T2.

[0110] An embodiment of the present application further provides a display substrate, comprising:

[0111] A pixel circuit as described in any of the above embodiments.

[0112] An embodiment of the present application further provides a display device, comprising:

[0113] The display substrate as described in the above embodiment.

[0114] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0115] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0116] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A pixel circuit, characterized in that: The circuit comprises: Signal writing control subcircuit, reset subcircuit, voltage compensation subcircuit, driving subcircuit and light emitting device; The signal writing control subcircuit is connected to the reset subcircuit and the voltage compensation subcircuit respectively, the reset subcircuit and the voltage compensation subcircuit are connected to the driving subcircuit respectively, and the driving subcircuit is connected to the light-emitting device; The reset sub-circuit is configured to reset the control terminal of the driving sub-circuit when the signal writing control sub-circuit inputs a reset signal; The voltage compensation sub-circuit is used to perform voltage compensation on the data signal at the control end of the driving sub-circuit when the signal writing control sub-circuit inputs a data signal; The signal writing control subcircuit includes a first transistor, the reset subcircuit includes a third transistor, the voltage compensation subcircuit includes a second transistor, and the driving subcircuit includes a fourth transistor and a first storage capacitor; The gate of the first transistor is connected to the first gate control signal terminal, the first terminal of the first transistor is connected to the signal voltage input terminal, and the second terminal of the first transistor is connected to the second terminal of the second transistor and the first terminal of the third transistor respectively; The gate of the second transistor is connected to the first end of the second transistor, and the first end of the second transistor is respectively connected to the gate of the fourth transistor, the first end of the first storage capacitor, and the second end of the third transistor; The gate of the third transistor is connected to the first end of the third transistor; The first terminal of the fourth transistor is connected to the cathode of the light emitting device, and the anode of the light emitting device is connected to the power supply voltage terminal; The second end of the fourth transistor is connected to the second end of the first storage capacitor and the negative end of the power supply respectively.

2. The circuit according to claim 1, wherein: A threshold voltage of the second transistor is equal to a threshold voltage of the fourth transistor.

3. The circuit according to claim 1, wherein: The circuit includes at least two driving sub-circuits, and the circuit also includes at least two gate control sub-circuits; the gate control sub-circuits correspond to the driving sub-circuits one-to-one; for each driving sub-circuit, the driving sub-circuit is respectively connected to the reset sub-circuit and the voltage compensation sub-circuit through the gate control sub-circuit corresponding to the driving sub-circuit.

4. The circuit according to claim 3, characterized in that The first gate control subcircuit includes a fifth transistor, the first driver subcircuit includes a fourth transistor and a first storage capacitor; the second gate control subcircuit includes a sixth transistor, the second driver subcircuit includes a seventh transistor and a second storage capacitor; the signal write control subcircuit includes a first transistor, the reset subcircuit includes a third transistor, and the voltage compensation subcircuit includes a second transistor; The gate of the first transistor is connected to the scan signal terminal, the first terminal of the first transistor is connected to the signal voltage input terminal, and the second terminal of the first transistor is connected to the second terminal of the second transistor and the first terminal of the third transistor respectively; The gate of the second transistor is connected to the first end of the second transistor, and the first end of the second transistor is connected to the first end of the fifth transistor and the first end of the sixth transistor respectively; The gate of the third transistor is connected to the first end of the third transistor, and the second end of the third transistor is connected to the first end of the fifth transistor and the first end of the sixth transistor respectively; The gate of the fifth transistor is connected to the first gate control signal terminal, and the second terminal of the fifth transistor is connected to the gate of the fourth transistor and the first terminal of the first storage capacitor respectively; The gate of the sixth transistor is connected to the second gate control signal terminal, and the second terminal of the sixth transistor is connected to the gate of the seventh transistor and the first terminal of the second storage capacitor respectively.

5. The circuit according to claim 4, characterized in that A threshold voltage of the second transistor is equal to a threshold voltage of the fourth transistor, and a threshold voltage of the second transistor is equal to a threshold voltage of the seventh transistor.

6. A method for driving a pixel circuit, characterized in that: For driving the pixel circuit according to any one of claims 1 to 5, the method comprising: In the reset phase, the control terminal of the signal writing control subcircuit inputs a first valid enable signal, and the data terminal of the signal writing control subcircuit inputs a reset signal; In the data writing phase, the control terminal of the signal writing control subcircuit inputs a first valid enable signal, and the data terminal of the signal writing control subcircuit inputs a data signal; The first valid enable signal, the reset signal, and the data signal have the same positive and negative polarities, and an absolute value of a voltage of the reset signal is greater than an absolute value of a voltage of the data signal.

7. The driving method according to claim 6, wherein: The driving method is used to drive the pixel circuit according to any one of claims 3 to 5, and the method includes: For each gate control sub-circuit, during the reset phase and data writing phase of the pixel row to which the gate control sub-circuit belongs, the control terminal of the gate control sub-circuit inputs the second valid enable signal; The first valid enable signal, the second valid enable signal, the reset signal and the data signal have the same positive and negative polarities.

8. A display substrate, characterized in that: The display substrate comprises: A pixel circuit as claimed in any one of claims 1 to 5.

9. A display device, characterized in that: The display device includes: A display substrate as claimed in claim 8.

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