Gate driving circuit, display panel and display device

Abstract

Embodiments of the present application provide a gate drive circuit, a display panel, and a display device, wherein the gate drive circuit includes: a plurality of cascaded rows of shift register units, wherein the first input terminal of the shift register unit in the N+1th row is connected to the output terminal of the shift register unit in the Nth row, and the second input terminal of the shift register unit in the N+1th row is connected to the output terminal of the shift register unit in the N+2th row, and the shift register unit includes: a first input circuit connected to a first high-level signal terminal, a first control signal terminal, and a first input terminal; a second input circuit connected to a second high-level signal terminal, a second control signal terminal, a first node, and a second input terminal; a first control circuit connected to a first clock signal terminal, a first node, and the output terminal of the shift register; and a second control circuit connected to a third high-level signal terminal, a second clock signal terminal, and a second node. The technical solution of the embodiments of the present application can avoid the occurrence of multiple outputs of the shift register unit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Art

[0002] Currently, gate drive circuits are typically formed on the array substrate of a liquid crystal display (LCD) using a gate driver on array (GOA) process. Gate drive circuits typically include multiple cascaded GOA units. Currently, abnormal GOA unit outputs are typically caused by multiple GOA unit outputs, impacting the stability of the display device. Summary of the Invention

[0003] Embodiments of the present application provide a gate driving circuit, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of an embodiment of the present application, an embodiment of the present application provides a gate drive circuit, comprising a plurality of cascaded rows of shift register units, wherein the first input terminal of the shift register unit in the N+1th row is connected to the output terminal of the shift register unit in the Nth row, and the second input terminal of the shift register unit in the N+1th row is connected to the output terminal of the shift register unit in the N+2th row, and the shift register unit comprises: a first input circuit connected to a first high-level signal terminal, a first control signal terminal, a first node, and the first input terminal of the shift register unit, the first input circuit being configured to: output a signal at the first control signal terminal to the first node under the control of a signal at the first high-level signal terminal and a signal at the first input terminal; a second input circuit, The second input circuit is connected to the second high-level signal terminal, the second control signal terminal, the first node and the second input terminal of the shift register unit, and is configured to: output the signal of the second control signal terminal to the first node under the control of the signal of the second high-level signal terminal and the signal of the second input terminal; the first control circuit is connected to the first clock signal terminal, the first node and the output terminal of the shift register unit, and is configured to: output the output signal from the output terminal under the level control of the first node; the second control circuit is connected to the third high-level signal terminal, the second clock signal terminal and the second node, and is configured to: output the second clock signal to the second node under the control of the second clock signal of the second clock signal terminal.

[0005] In one embodiment, the first input circuit includes: a first transistor, the gate of the first transistor is used to connect to the first high-level signal terminal, and the first electrode of the first transistor is used to connect to the first input terminal; a second transistor, the gate of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the first control signal terminal, and the second electrode of the second transistor is connected to the first node.

[0006] In one embodiment, the first control circuit includes: a third transistor, the gate of the third transistor is connected to the first node, and the first electrode of the third transistor is used to connect to the first clock signal end; a first capacitor, one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the second electrode of the third transistor.

[0007] In one embodiment, the second control circuit includes: a fourth transistor, the gate and the first electrode of the fourth transistor are used to connect to the second clock signal terminal; a fifth transistor, the gate of the fifth transistor is connected to the second electrode of the fourth transistor, the first electrode of the fifth transistor is used to connect to the third high-level signal terminal, and the second electrode of the fifth transistor is connected to the second node.

[0008] In one embodiment, the second input circuit includes: a sixth transistor, the gate of the sixth transistor is used to connect to the second high-level signal terminal, and the first electrode of the sixth transistor is used to connect to the second input terminal; a seventh transistor, the gate of the seventh transistor is connected to the second electrode of the sixth transistor, the first electrode of the seventh transistor is used to connect to the second control signal terminal, and the second electrode of the seventh transistor is connected to the first node.

[0009] In one embodiment, the shift register unit further includes: an eighth transistor, a gate of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is used to connect to the low-level signal terminal, and a second electrode of the eighth transistor is connected to the first node.

[0010] In one embodiment, the shift register unit further includes: a ninth transistor, the gate of the ninth transistor being connected to the second node, the first electrode of the ninth transistor being used to connect to the low-level signal terminal, and the second electrode of the ninth transistor being used to connect to the output terminal; a tenth transistor, the gate of the tenth transistor being used to connect to the output terminal, the first electrode of the tenth transistor being used to connect to the low-level signal terminal, and the second electrode of the tenth transistor being connected to the second node; an eleventh transistor, the gate of the eleventh transistor being connected to the first node, the first electrode of the eleventh transistor being connected to the second node, and the second electrode of the eleventh transistor being used to connect to the low-level signal terminal; and a twelfth transistor, the gate and the first electrode of the twelfth transistor being used to connect to the reset signal terminal, and the second electrode of the twelfth transistor being connected to the second node.

[0011] In one embodiment, the shift register unit further includes: a second capacitor, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is used to connect to the low-level signal end.

[0012] As another aspect of an embodiment of the present application, an embodiment of the present application provides a display panel, comprising a gate driving circuit according to any implementation of the first aspect of the present application.

[0013] As another aspect of the embodiments of the present application, the embodiments of the present application provide a display device, including a gate driving circuit according to any embodiment of the first aspect of the present application, or including a gate driving circuit according to any embodiment of the second aspect of the present application.

[0014] The embodiments of the present application adopt the above technical solution to improve the stability of the gate driving circuit, avoid the occurrence of multiple outputs of the shift register unit, and thus improve the stability of the display device.

[0015] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0017] Figure 1 is a circuit diagram of a shift register unit in the related art;

[0018] Figure 2 A cascade relationship diagram of multiple shift register units in the related art;

[0019] Figure 3 is a timing diagram of a shift register unit in the related art;

[0020] Figure 4 The output abnormality timing diagram of multiple shift register units in the related art;

[0021] Figure 5 1 is a circuit diagram of a shift register unit of a gate driving circuit according to an embodiment of the present application;

[0022] Figure 6 is a cascade relationship diagram of multiple shift register units in a gate driving circuit according to an embodiment of the present application;

[0023] Figure 7 1 is a positive scan timing diagram of a gate driving circuit according to an embodiment of the present application;

[0024] Figure 8 1 is a reverse scan timing diagram of a gate drive circuit according to an embodiment of the present application;

[0025] Figure 9 is a timing diagram of a gate driving circuit according to an embodiment of the present application;

[0026] Figure 10 1 is a timing comparison diagram of a shift register unit according to an embodiment of the present application and a shift register unit in related art;

[0027] Figure 11 1 is a timing comparison diagram of a first node of a shift register unit according to an embodiment of the present application and a first node of a shift register unit in the related art;

[0028] Figure 12 1 is a timing comparison diagram of the second node of the shift register unit according to the embodiment of the present application and the second node of the shift register unit in the related art.

[0029] Description of reference numerals:

[0030] 10: Gate drive circuit;

[0031] 100: shift register unit; 110: first input circuit; 111: first transistor; 112: second transistor; 120: second input circuit; 121: sixth transistor; 122: seventh transistor; 130: first control circuit; 131: third transistor; 132: first capacitor; 140: second control circuit; 141: fourth transistor; 142: fifth transistor; 151: eighth transistor; 152: ninth transistor; 153: tenth transistor; 154: eleventh transistor; 155: twelfth transistor; 156: second capacitor. DETAILED DESCRIPTION

[0032] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0033] Figure 1 FIG. 1 is a circuit diagram of a shift register unit in the related art. Figure 1As shown, in the related art, the shift register unit includes 10 transistors and 2 capacitors. Among them, the 10 transistors are respectively the first transistor T1 to the tenth transistor T10. When the control node PU_CN is at a high level and the second clock signal terminal CKB is at a high level, the sixth transistor T6 and the seventh transistor T7 are turned on, so that the sixth transistor T6 and the seventh transistor T7 form a DC path. At this time, it is necessary to set the conduction parameters of the sixth transistor T6 and the seventh transistor T7, for example, setting a voltage divider with different aspect ratios so that the resistance of the sixth transistor T6 is greater than the resistance of the seventh transistor T7, so that the level of the second node PD can be pulled down.

[0034] Figure 2 FIG is a cascade relationship diagram of multiple shift register units in the related art. Figure 2 As shown, the shift register units of odd-numbered stages control the shift register units of odd-numbered stages, and the shift register units of even-numbered stages control the shift register units of even-numbered stages. Specifically, the output of the shift register units in the Nth row is the input of the shift register units in the N+2th row, and at the same time, the output of the shift register units in the N+2th row is fed back to the gate of the second transistor T2 of the shift register units in the Nth row. When the output of the shift register units in the N+2th row is high, the second transistor T2 of the shift register units in the Nth row is turned on, resetting the first node PU and the second node PD, and the output terminal OUTPUT of the shift register units in the Nth row outputs a low level.

[0035] Figure 3 is a timing diagram of a shift register unit in the related art; Figure 4 FIG. 1 is a timing diagram of output abnormality of multiple shift register units in the related art. Figure 3 As shown, in the related art, there is a voltage drop at the voltage of the first node PU of the shift register unit (see part A), and there is a voltage drop at the voltage of the second node PD (see part B). Figure 4 When the output of the shift register unit in the N+2th row is abnormal, the first node PU and the second node PD of the shift register unit in the Nth row cannot be reset, resulting in abnormal outputs of multiple rows of shift register units (such as OUT1-OUT5).

[0036] The following combination Figure 5-Figure 12 The gate driving circuit 10 according to the first embodiment of the present application is described.

[0037] Figure 5 1 is a circuit diagram of a shift register unit 100 of a gate driving circuit 10 according to an embodiment of the present application; Figure 6 FIG. 1 is a cascade diagram of a plurality of shift register units 100 in a gate drive circuit 10 according to an embodiment of the present application. Figure 5 and Figure 6As shown, the gate driving circuit 10 includes a plurality of cascaded rows of shift register units 100, wherein the first input end of the N+1th row of shift register units 100 is connected to the output end of the Nth row of shift register units 100, and the second input end of the N+1th row of shift register units 100 is connected to the output end of the N+2th row of shift register units 100.

[0038] For example, in Figure 5 and Figure 6 In the example, the first input terminal OUT of the first row shift register unit GOA1 N-1 It can be used to connect the frame start signal terminal STV, and the output terminal OUT1 of the first row shift register GOA1 can be connected to the first input terminal OUT of the second row shift register GOA2. N-1 The output terminal OUT2 of the second row shift register GOA2 can be connected to the second input terminal OUT of the first row shift register GOA1. N+1 and the first input terminal OUT of the third row shift register GOA3 N-1 The output terminal OUT3 of the third row shift register GOA3 can be connected to the second input terminal OUT of the second row shift register GOA2. N+1 and the first input terminal OUT of the fourth row shift register GOA4 N-1 The cascade relationship of the multiple rows of shift register units 100 in the embodiment of the present application effectively replaces the solution in the related art in which odd-numbered shift register units control odd-numbered shift register units and even-numbered shift register units control even-numbered shift register units.

[0039] The shift register unit 100 includes a first input circuit 110, a second input circuit 120, a first control circuit 130, and a second control circuit 140. The first input circuit 110 is connected to the first high level signal terminal VGH1, the first control signal terminal CN, the first node PU, and the first input terminal OUT of the shift register unit 100. N-1 The second input circuit 120 is connected to the second high level signal terminal VGH2, the second control signal terminal CNB, the first node PU and the second input terminal OUT of the shift register unit 100. N+1 The first control circuit 130 is connected to the first clock signal terminal CK, the first node PU and the output terminal OUT of the shift register. N The second control circuit 140 is connected to the third high level signal terminal VGH3 , the second clock signal terminal CKB and the second node PD.

[0040] The first input circuit 110 is configured to: connect the signal at the first high level signal terminal VGH1 to the first input terminal OUT N-1Under the control of the signal of the first control signal terminal CN, the signal is output to the first node PU; the second input circuit 120 is configured as: the signal at the second high level signal terminal VGH2 and the second input terminal OUT N+1 Under the control of the signal of the second control signal terminal CNB, the signal is output to the first node PU; the first control circuit 130 is configured to: under the level control of the first node PU, output the output signal to the output terminal OUT N The second control circuit 140 is configured to output the second clock signal to the second node PD under the control of the second clock signal at the second clock signal terminal CKB.

[0041] For example, the first input terminal OUT of the first row shift register GOA1 N-1 It can be used to connect to the frame start signal terminal STV. Figure 7 1 is a positive scan timing diagram of the gate driving circuit 10 according to an embodiment of the present application; Figure 8 FIG. 1 is a timing diagram of the reverse sweep of the gate drive circuit 10 according to an embodiment of the present application. Figure 7 and Figure 8 The shift register supports forward scanning and reverse scanning. For example, when the first control signal terminal CN is high and the second control signal terminal CNB is low, forward scanning is performed; when the first control signal terminal CN is low and the second control signal terminal CNB is high, reverse scanning is performed.

[0042] According to the gate drive circuit 10 of the embodiment of the present application, by adopting the above-mentioned cascaded multi-row shift register unit 100, when the second clock signal terminal CKB is at a high level, the second clock signal can charge the second node PD without a voltage drop, thereby avoiding threshold loss, and playing a role in improving the driving capability and waveform shaping of the level signal of the second node PD, thereby achieving the reset of the first node PU and the second node PD by the second clock signal of this stage, improving the stability of the gate drive circuit 10, avoiding the occurrence of multiple outputs of the shift register unit 100, and thus improving the stability of the display device.

[0043] In one embodiment, combined Figure 5 The first input circuit 110 includes a first transistor 111 and a second transistor 112. The gate of the first transistor 111 is connected to the first high level signal terminal VGH1, and the first electrode of the first transistor 111 is connected to the first input terminal OUT N-1 The gate of the second transistor 112 is connected to the second electrode of the first transistor 111 , the first electrode of the second transistor 112 is connected to the first control signal terminal CN, and the second electrode of the second transistor 112 is connected to the first node PU.

[0044] One of the first electrode and the second electrode is a source electrode, and the other of the first electrode and the second electrode is a drain electrode. The first transistor 111 and the second transistor 112 can be N-type transistors or P-type transistors, which is not limited in the present embodiment.

[0045] For example, in combination Figure 5 and Figure 6 The gate drive circuit 10 may include a frame start signal terminal STV, a first clock signal line CKL, a second clock signal line CKBL, a third clock signal line CKR, and a fourth clock signal line CKBR. For example, the same signal CKBL is connected to different ports in different rows. The first row on the odd side is connected to the CK port, the second row on the odd side is connected to the CKB port, and so on.

[0046] For odd-numbered rows of shift register units 100, the first control circuit 130 may be connected to the first clock signal terminal CK of the first clock signal line CKL, and the second control circuit 140 may be connected to the second clock signal terminal CKB of the second clock signal line CKBL. For even-numbered rows of shift register units 100, the first control circuit 130 may be connected to the first clock signal terminal CK of the third clock signal line CKR, and the second control circuit 140 may be connected to the second clock signal terminal CKB of the fourth clock signal line CKBR.

[0047] Among them, the first input terminal OUT of the first row shift register GOA1 N-1 It can be used to connect the frame start signal terminal STV. Take the first control signal terminal CN as a high level 8V and the second control signal terminal CNB as a low level -8V as an example for explanation. Figure 9 FIG. 1 is a timing diagram of the gate drive circuit 10 according to an embodiment of the present application. Figure 9 In the first stage T1, the frame start signal terminal STV is at a high level. Due to the capacitance effect of the transistor, the first transistor 111 is bootstrapped and outputs 16V. The second transistor 112 can be fully turned on, the first node PU is charged with a full 8V level, and the second node PD remains at a low level. At this time, the output terminal OUT N Output low level.

[0048] In one embodiment, Figure 5 and Figure 6 As shown, the first control circuit 130 includes a third transistor 131 and a first capacitor 132. The gate of the third transistor 131 is connected to the first node PU, and the first electrode of the third transistor 131 is used to connect to the first clock signal terminal CK. One end of the first capacitor 132 (for example, Figure 5 The left end of the first capacitor 132 is connected to the first node PU, and the other end of the first capacitor 132 (for example, Figure 5The right end of the transistor 130 is connected to the second electrode of the third transistor 131.

[0049] For example, in combination Figure 9 , when the first control signal terminal CN is at a high level of 8V and the second control signal terminal CNB is at a low level of -8V, in the first stage T1, the frame start signal terminal STV is at a high level, the first transistor 111 is bootstrapped, and the first transistor 111 outputs 16V. The second transistor 112 can be fully turned on, and the first node PU is charged with a full 8V level. The second node PD remains at a low level, the third transistor 131 is turned on, and the output terminal OUT N Output low level. In the second stage T2, the first clock signal terminal CK of the first clock signal line CKL is high level, the first capacitor 132 has a bootstrap effect, at this time the voltage of the first node PU is 24V, the second node PD remains low level, the third transistor 131 is turned on, and the output terminal OUT N Output high level. In the third phase T3, the first clock signal terminal CK of the third clock signal line CKR is high level, the first node PU and the second node PD are both low level, and the output terminal OUT N Output low level.

[0050] In one embodiment, Figure 5 As shown, the second control circuit 140 includes a fourth transistor 141 and a fifth transistor 142. The gate and first electrode of the fourth transistor 141 are connected to the second clock signal terminal CKB. The gate of the fifth transistor 142 is connected to the second electrode of the fourth transistor 141, the first electrode of the fifth transistor 142 is connected to the third high-level signal terminal VGH3, and the second electrode of the fifth transistor 142 is connected to the second node PD.

[0051] Illustratively, in the fourth stage T4, the second clock signal terminal CKB of the second clock signal line CKBL is at a high level. At this time, the fourth transistor 141 and the fifth transistor 142 cooperate to cause the fifth transistor 142 to bootstrap, and the second clock signal of the second clock signal terminal CKB charges the second node PD through the fifth transistor 142 without a voltage drop.

[0052] In this embodiment, based on the above-mentioned cascade relationship of multiple shift register units 100, by setting the above-mentioned fourth transistor 141 and fifth transistor 142, the second clock signal of the second clock signal terminal CKB can charge the second node PD through the fifth transistor 142 without voltage drop, avoiding threshold loss and effectively improving the stability of the gate drive circuit 10.

[0053] In one embodiment, Figure 5As shown, the second input circuit 120 includes a sixth transistor 121 and a seventh transistor 122. The gate of the sixth transistor 121 is used to connect to the second high level signal terminal VGH2, and the first electrode of the sixth transistor 121 is used to connect to the second input terminal OUT N+1 The gate of the seventh transistor 122 is connected to the second electrode of the sixth transistor 121 , the first electrode of the seventh transistor 122 is connected to the second control signal terminal CNB, and the second electrode of the seventh transistor 122 is connected to the first node PU.

[0054] For example, in combination Figure 6 When the first control signal terminal CN is at a high level of 8V and the second control signal terminal CNB is at a low level of -8V, the first transistor 111 and the sixth transistor 121 are normally open, and the output terminal OUT of the next row of shift register units 100 is switched on. N The output signal is fed back to the second input terminal OUT of the shift register unit 100 in this row. N+1 .

[0055] In one embodiment, reference Figure 5 The shift register unit 100 may further include an eighth transistor 151 , a ninth transistor 152 , a tenth transistor 153 , an eleventh transistor 154 , a twelfth transistor 155 and a second capacitor 156 .

[0056] Specifically, the gate of the eighth transistor 151 is connected to the second node PD, the first electrode of the eighth transistor 151 is connected to the low-level signal terminal VGL, and the second electrode of the eighth transistor 151 is connected to the first node PU. The gate of the ninth transistor 152 is connected to the second node PD, the first electrode of the ninth transistor 152 is connected to the low-level signal terminal VGL, and the second electrode of the ninth transistor 152 is connected to the output terminal OUT N The gate of the tenth transistor 153 is connected to the output terminal OUT N The first electrode of the tenth transistor 153 is connected to the low-level signal terminal VGL, and the second electrode of the tenth transistor 153 is connected to the second node PD. The gate of the eleventh transistor 154 is connected to the first node PU, the first electrode of the eleventh transistor 154 is connected to the second node PD, and the second electrode of the eleventh transistor 154 is connected to the low-level signal terminal VGL. The gate and the first electrode of the twelfth transistor 155 are connected to the reset signal terminal RESET, and the second electrode of the twelfth transistor 155 is connected to the second node PD. One end of the second capacitor 156 (for example, Figure 5 The upper end of the second capacitor 156 is connected to the second node PD, and the other end of the second capacitor 156 (for example, Figure 5 The lower end in the middle) is used to connect the low-level signal end VGL.

[0057] In this embodiment, the fourth transistor 141, the fifth transistor 142 and the eleventh transistor 154 can be prevented from being turned on at the same time, thereby avoiding a DC path (i.e., a short circuit) from the second clock signal terminal CKB to the low-level signal terminal VGL, thereby avoiding the problem of competition between the potentials of the first node PU and the second node PD due to the DC path. Therefore, the power consumption of the gate drive circuit 10 can be reduced and the stability of the gate drive circuit 10 can be improved.

[0058] Figure 10 1 is a timing comparison diagram of the shift register unit 100 according to the embodiment of the present application and the shift register unit in the related art; Figure 11 1 is a timing comparison diagram of the first node PU of the shift register unit 100 according to the embodiment of the present application and the first node of the shift register unit in the related art; Figure 12 1 is a timing comparison diagram of the second node PD of the shift register unit 100 according to the embodiment of the present application and the second node of the shift register unit in the related art.

[0059] According to the gate driving circuit 10 of the embodiment of the present application, Figures 9-12 As shown, from Figure 11 As can be seen from the figure, the circuit structure and cascade relationship of the shift register unit 100 according to the embodiment of the present application can make the reset voltage of the second node PD have no voltage drop, improve the voltage and response speed of the second node PD, and make the circuit output more stable when the row is closed; Figure 12 It can be seen that the circuit structure and cascade relationship of the shift register unit 100 of the embodiment of the present application can make the bootstrap voltage of the first node PU higher, realize the waveform shaping of the first node PU, improve the voltage and response speed of the first node PU, and make the circuit output more stable when the row is opened.

[0060] The display panel according to the second aspect of the present application includes the gate driving circuit 10 according to any embodiment of the first aspect of the present application.

[0061] The display device according to the embodiment of the third aspect of the present application includes the gate driving circuit 10 according to any embodiment of the first aspect of the present application, or includes the display panel according to any embodiment of the second aspect of the present application.

[0062] For example, the display panel may include an array of multiple sub-pixel units. The display device may further include a data driver circuit. The data driver circuit is used to provide data signals to the pixel array. The gate driver circuit 10 is used to provide drive signals to the pixel array. For example, the drive signals can drive scanning transistors and sensing transistors in the sub-pixel units. The data driver circuit is electrically connected to the sub-pixel units via data lines, and the gate driver circuit 10 is electrically connected to the sub-pixel units via gate lines.

[0063] For example, the display device may be a liquid crystal display device or an organic light emitting diode display device. For example, the display device may be a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or any other product or component with a display function.

[0064] The gate driving circuit 10, the display panel and other components of the display device in the above embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0065] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0067] In this application, unless otherwise expressly specified or limited, terms such as "installed," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0068] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0069] The disclosure above provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0070] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A gate drive circuit, characterized in that: A plurality of cascaded shift register units are provided, wherein the first input end of the shift register unit in the N+1th row is connected to the output end of the shift register unit in the Nth row, and the second input end of the shift register unit in the N+1th row is connected to the output end of the shift register unit in the N+2th row, and the shift register unit comprises: a first input circuit connected to a first high-level signal terminal, a first control signal terminal, a first node, and a first input terminal of the shift register unit, wherein the first input circuit is configured to output a signal from the first control signal terminal to the first node under control of a signal from the first high-level signal terminal and a signal from the first input terminal; a second input circuit connected to a second high-level signal terminal, a second control signal terminal, the first node, and a second input terminal of the shift register unit, the second input circuit being configured to: output a signal from the second control signal terminal to the first node under the control of a signal from the second high-level signal terminal and a signal from the second input terminal; a first control circuit connected to a first clock signal terminal, the first node, and an output terminal of the shift register unit, the first control circuit being configured to: output an output signal from the output terminal under the level control of the first node; The second control circuit is connected to the third high-level signal terminal, the second clock signal terminal and the second node. The second control circuit is configured to output the second clock signal to the second node under the control of the second clock signal at the second clock signal terminal.

2. The gate drive circuit according to claim 1, wherein: The first input circuit comprises: a first transistor, wherein a gate of the first transistor is connected to the first high-level signal terminal, and a first electrode of the first transistor is connected to the first input terminal; A second transistor, wherein the gate of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is used to connect to the first control signal terminal, and the second electrode of the second transistor is connected to the first node.

3. The gate drive circuit according to claim 1, wherein: The first control circuit includes: a third transistor, wherein a gate of the third transistor is connected to the first node, and a first electrode of the third transistor is used to be connected to the first clock signal terminal; A first capacitor, one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the second electrode of the third transistor.

4. The gate drive circuit according to claim 1, wherein: The second control circuit includes: a fourth transistor, wherein the gate and the first electrode of the fourth transistor are used to be connected to the second clock signal terminal; A fifth transistor, wherein the gate of the fifth transistor is connected to the second electrode of the fourth transistor, the first electrode of the fifth transistor is used to connect to the third high-level signal terminal, and the second electrode of the fifth transistor is connected to the second node.

5. The gate driving circuit according to claim 1, wherein: The second input circuit includes: a sixth transistor, wherein a gate of the sixth transistor is connected to the second high-level signal terminal, and a first electrode of the sixth transistor is connected to the second input terminal; A seventh transistor, wherein the gate of the seventh transistor is connected to the second electrode of the sixth transistor, the first electrode of the seventh transistor is used to connect to the second control signal terminal, and the second electrode of the seventh transistor is connected to the first node.

6. The gate driving circuit according to claim 1, wherein: The shift register unit further includes: An eighth transistor, wherein the gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is used to connect to the low-level signal terminal, and the second electrode of the eighth transistor is connected to the first node.

7. The gate driving circuit according to claim 6, wherein: The shift register unit further includes: a ninth transistor, wherein a gate of the ninth transistor is connected to the second node, a first electrode of the ninth transistor is connected to the low-level signal terminal, and a second electrode of the ninth transistor is connected to the output terminal; a tenth transistor, wherein a gate of the tenth transistor is connected to the output terminal, a first electrode of the tenth transistor is connected to the low-level signal terminal, and a second electrode of the tenth transistor is connected to the second node; an eleventh transistor, wherein a gate of the eleventh transistor is connected to the first node, a first electrode of the eleventh transistor is connected to the second node, and a second electrode of the eleventh transistor is used to be connected to the low-level signal terminal; A twelfth transistor, wherein the gate and the first electrode of the twelfth transistor are used to connect to the reset signal terminal, and the second electrode of the twelfth transistor is connected to the second node.

8. The gate driving circuit according to claim 1, wherein: The shift register unit further includes: A second capacitor, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is used to connect to the low-level signal end.

9. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 8.

10. A display device, characterized in that: The method comprises the gate driving circuit according to any one of claims 1 to 8; or comprises the display panel according to claim 9.

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