Sot-mram memory cells, memory arrays, memory with polymorphic storage

Abstract

The application provides a kind of SOT-MRAM storage unit of polymorphic storage, storage array, memory, and relates to magnetic memory technical field.The SOT-MRAM storage unit of polymorphic storage of the application, bottom electrode, magnetic tunnel junction and top electrode;When the voltage between bottom electrode and top electrode is different, the potential difference between the top and bottom of magnetic tunnel junction is formed, and by inputting different write voltage, the different resistance state of magnetic tunnel junction is controlled.The application can realize multi-resistance state storage by the method of applying voltage to the top and bottom of magnetic tunnel junction without changing the existing process, and solves the technical problem of small storage density of the existing SOT-MRAM single storage unit.At the same time, the application does not need complex process, and the cost is low.

Description

Technical Field

[0001] This invention relates to the field of magnetic memory technology, and specifically to a polymorphic SOT-MRAM memory cell, memory array, memory, and a method for implementing SOT-MRAM polymorphic memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM), as an emerging non-volatile memory, features high read / write speeds, long battery life, long storage time, and low power consumption. In recent years, major semiconductor manufacturers such as TSMC, Samsung, and GlobalFoundries have actively invested in the MRAM field. On one hand, traditional embedded flash memory (e-flash) is based on an erase-then-write method, with a limited number of erase cycles per cell. Excessive erase cycles lead to wear and tear, affecting the entire e-flash lifespan. Furthermore, e-flash is too expensive below the 28nm CMOS technology node. In contrast, MRAM offers the advantage of unlimited write cycles at a lower cost, making it a crucial alternative to e-flash. On the other hand, MRAM can also replace SRAM to address potential leakage issues in advanced CMOS nodes. However, currently mature technologies like Toggle-MRAM and STT-MRAM are difficult to replace L1 or L2 SRAM caches due to write speed limitations and reliability issues. To address the above issues, Liu et al. proposed a spin-orbit moment MRAM (SOT-MRAM) with separate read and write paths in a three-terminal device, which fundamentally solves the read errors and tunnel junction aging problems caused by high write current.

[0003] Magnetic tunnel junctions (MTJs) are the basic memory cells of SOT-MRAMs. They typically consist of two ferromagnetic layers separated by an oxide semiconductor layer, forming a sandwich-like structure. When the magnetic moments of the two ferromagnetic layers are in the same direction, the device is in a low-resistivity state; when the magnetic moments are in opposite directions, the device is in a high-resistivity state. However, a single memory cell in a conventional SOT-MRAM can only store 1 bit. To improve the storage density of the device, one main approach is to reduce the size of the MTJ, which poses a challenge to micro- and nano-fabrication processes. Another approach is to achieve multi-bit storage in a single device to increase the storage density. Currently, most solutions for multi-bit storage are achieved by stacking or cascading MTJs. However, this method does not truly achieve multi-bit storage in a single device.

[0004] As can be seen from the above description, the storage density of a single memory cell in existing SOT-MRAM is low. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the shortcomings of existing technologies, this invention provides a polymorphic SOT-MRAM storage cell, storage array, and memory, which solves the technical problem of low storage density in a single SOT-MRAM storage cell.

[0007] (II) Technical Solution

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] In a first aspect, the present invention provides a multi-state storage SOT-MRAM memory cell, comprising: a magnetic tunnel junction, a bottom electrode and a top electrode, wherein the bottom electrode is disposed in the lowest structural layer of the magnetic tunnel junction and the top electrode is disposed in the highest structural layer of the magnetic tunnel junction;

[0010] When the voltages between the bottom and top electrodes are different, a potential difference is formed between the top and bottom of the magnetic tunnel junction. At the same time, by inputting different write voltages, the magnetic tunnel junction is controlled to exhibit different resistance states.

[0011] Preferably, the bottom electrode includes a first bottom electrode and a second bottom electrode, which are symmetrically disposed in the lowest structural layer of the magnetic tunnel junction.

[0012] Different voltages are applied to the first bottom electrode and the second bottom electrode. The voltage at the midpoint between the first bottom electrode and the second bottom electrode is the voltage at the bottom of the magnetic tunnel junction.

[0013] Preferably, the voltage of the top electrode is set to 0, and different voltages are applied to the first bottom electrode and the second bottom electrode. The voltage of the top electrode is different from the voltage at the bottom of the magnetic tunnel junction, and a potential difference is formed between the top and bottom of the magnetic tunnel junction.

[0014] Preferably, the write voltage margin is increased by increasing the potential difference.

[0015] Preferably, when the potential difference is 0, the positive and negative directions of the write voltage control the direction of the free layer magnetic moment in the magnetic tunnel junction to be parallel or antiparallel to the direction of the reference layer magnetic moment, and the magnetic tunnel junction exhibits a low magnetoresistance state R3 or a high magnetoresistance state R1.

[0016] When a potential difference exists, applying a write voltage changes the direction of the free layer magnetic moment in the magnetic tunnel junction. When the write voltage increases to V1, the magnetic tunnel junction exhibits a biased resistance state R2. Continuing to increase the write voltage, when it reaches V2, the direction of the free layer magnetic moment flips relative to its original state, and the magnetic tunnel junction exhibits a high magnetoresistance state R1 or a low magnetoresistance state R3. Continuing to increase the write voltage, the direction of the free layer magnetic moment remains unchanged, and the resistance state of the magnetic tunnel junction remains unchanged.

[0017] Wherein, |V1| < |V2|.

[0018] Preferably, the first bottom electrode and the second bottom electrode are respectively connected to two channels of the pulse power supply;

[0019] And / or, the top electrode is grounded.

[0020] Preferably, the magnetic tunnel junction comprises, from bottom to top, a heavy metal layer, a free layer, an isolation layer, a reference layer, a pinning layer, and a capping layer.

[0021] Secondly, the present invention provides a polymorphic SOT-MRAM storage array, characterized in that it includes a plurality of polymorphic SOT-MRAM storage cells as described above.

[0022] Thirdly, the present invention provides a polymorphic SOT-MRAM memory, characterized in that it includes at least one SOT-MRAM memory array as described above.

[0023] Fourthly, the present invention provides a method for realizing SOT-MRAM multi-state storage, characterized in that the method includes: applying voltage to the top and bottom ends of a magnetic tunnel junction and simultaneously inputting different write voltages to realize multi-resistance state storage of a single magnetic tunnel junction.

[0024] (III) Beneficial Effects

[0025] This invention provides a polymorphic SOT-MRAM memory cell, memory array, and memory. Compared with the prior art, it has the following advantages:

[0026] This invention discloses a multi-state SOT-MRAM memory cell comprising a bottom electrode, a magnetic tunnel junction, and a top electrode. When the voltages between the bottom and top electrodes are different, a potential difference is formed between the top and bottom of the magnetic tunnel junction. By inputting different write voltages, the magnetic tunnel junction is controlled to exhibit different resistance states. This invention achieves multi-resistivity storage without altering existing processes by applying voltages across the top and bottom of the magnetic tunnel junction, solving the technical problem of low storage density in existing SOT-MRAM single memory cells. Furthermore, this invention requires no complex processes and is low in cost. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a structural diagram of an SOT-MRAM device;

[0029] Figure 2 Existing methods for implementing multi-resistive-state storage using SOT-MRAM;

[0030] Figure 3 Test method schematic diagram;

[0031] Figure 4 A schematic diagram of the multi-resistance curve obtained by applying a positive voltage between the top and bottom of the SOT-MRAM memory cell in the embodiment of the present invention;

[0032] Figure 5 In this embodiment of the invention, a large positive voltage is applied between the top and bottom of the SOT-MRAM memory cell to obtain a multi-resistance curve, which increases the write voltage margin.

[0033] Figure 6 A schematic diagram of the multi-resistance curve obtained by applying a negative voltage between the top and bottom of the SOT-MRAM memory cell in the embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] This application provides a polymorphic SOT-MRAM memory cell, memory array, and memory, which solves the technical problem of low storage density of a single SOT-MRAM memory cell and enables multi-bit storage in a single device.

[0036] The technical solution in this application is to solve the above-mentioned technical problems, and the general idea is as follows:

[0037] The main structure of SOT-MRAM devices is as follows: Figure 1 As shown, the structure consists of a heavy metal layer, a free layer, an isolation layer, a reference layer, a pinning layer, and a capping layer. The thickness of each layer is on the nanometer and angstrom scale. The magnetoresistance of the MTJ is mainly related to the direction of the magnetic moment of the free layer. When the direction of the magnetic moment of the free layer is parallel to the direction of the magnetic moment of the reference layer, the MTJ exhibits a low magnetoresistance state (R3). When the direction of the magnetic moment of the free layer is antiparallel to the direction of the magnetic moment of the reference layer, the MTJ exhibits a high magnetoresistance state (R1). The reversal of the direction of the magnetic moment of the free layer is related to the magnitude of the write voltage in the heavy metal layer. Conventional SOT-MRAMs only exhibit two resistive states, R1 and R3, during voltage writing. To achieve multi-resistance state storage in a single device, more complex device structure designs or multiple devices connected in series are usually required. Figure 2 To achieve multi-resistivity storage in existing devices, two multi-mode junction boxes (MTJs) are connected in series or stacked in the circuit. This method typically requires complex layout design and fabrication processes, and increases the planar area occupied by the MTJ, thus not truly achieving multi-resistivity storage with a single device. Against this backdrop, this invention develops a method to achieve multi-bit storage in a single device by applying bias voltages to the top and bottom terminals of the MTJ without changing the MTJ area or existing process flow.

[0038] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0039] This invention provides a multi-state SOT-MRAM memory cell, comprising: a magnetic tunnel junction, a bottom electrode, and a top electrode. The bottom electrode is disposed in the lowest structural layer of the magnetic tunnel junction, and the top electrode is disposed in the highest structural layer of the magnetic tunnel junction. When the voltage between the bottom electrode and the top electrode is different, a potential difference is formed between the top and bottom of the magnetic tunnel junction. By inputting different write voltages, the magnetic tunnel junction is controlled to exhibit different resistance states.

[0040] like Figure 3 As shown, in a specific implementation, the bottom electrode includes a first bottom electrode and a second bottom electrode, which are symmetrically arranged in the lowest structural layer of the magnetic tunnel junction. The voltage at the midpoint between the first and second bottom electrodes is the voltage of the bottom electrode, i.e., the voltage at the bottom of the magnetic tunnel junction. Furthermore, the magnetic tunnel junction MTJ of this embodiment has the same structure as existing SOT-MRAM devices, comprising, from bottom to top, a heavy metal layer, a free layer, an isolation layer, a reference layer, a pinning layer, and a capping layer. The first and second bottom electrodes are connected to the heavy metal layer, and the top electrode is connected to the capping layer.

[0041] In the specific implementation process, the voltage of the top electrode is set to 0, and different voltages are applied to the first bottom electrode and the second bottom electrode. The voltage of the top electrode is different from that of the bottom electrode, and a potential difference is formed between the top and bottom of the magnetic tunnel junction.

[0042] like Figure 4 and Figure 5 As shown, by increasing the potential difference, the write voltage margin is increased.

[0043] like Figure 4 and Figure 5 As shown, when the potential difference is 0, the positive and negative directions of the write voltage control the direction of the free layer magnetic moment in the magnetic tunnel junction to be parallel or antiparallel to the direction of the reference layer magnetic moment, and the magnetic tunnel junction exhibits a low magnetoresistance state R3 or a high magnetoresistance state R1.

[0044] When a potential difference exists, a write voltage is applied, and the direction of the free layer magnetic moment in the magnetic tunnel junction changes. When the write voltage increases to V1, the magnetic tunnel junction exhibits a biased resistance state R2. If the write voltage is further increased, when it increases to V2, the direction of the free layer magnetic moment is reversed relative to the original state, and the magnetic tunnel junction exhibits a high magnetoresistance state R1 or a low magnetoresistance state R3. If the write voltage is further increased, the direction of the free layer magnetic moment remains unchanged, and the resistance state of the magnetic tunnel junction remains unchanged.

[0045] Wherein, |V1| < |V2|. The absolute values ​​of V1 and V2 are positively correlated with the voltage difference between the top and bottom of the MTJ junction.

[0046] like Figure 6 As shown, by changing the direction of the potential difference, i.e. setting the voltage at the midpoint between the first and second bottom electrodes to a negative voltage, the resistance state of R2 changes to a symmetrical position.

[0047] In the specific implementation process, the first bottom electrode and the second bottom electrode are respectively connected to the two channels of the pulse power supply, and the top electrode is grounded.

[0048] This invention also provides a polymorphic SOT-MRAM storage array, including a plurality of polymorphic SOT-MRAM storage cells as described above.

[0049] This invention also provides a polymorphic SOT-MRAM memory, including at least one SOT-MRAM memory array as described above.

[0050] This invention also provides a method for implementing SOT-MRAM multi-state storage, the method comprising: applying voltage to the top and bottom ends of a magnetic tunnel junction to achieve multi-resistive state storage of a single magnetic tunnel junction.

[0051] In summary, compared with existing technologies, it has the following beneficial effects:

[0052] This invention, without altering existing processes, achieves multi-resistive state storage by applying voltages to the top and bottom of a magnetic tunnel junction, thus solving the technical problem of low storage density in a single memory cell of existing SOT-MRAM. Furthermore, this invention requires no complex processes, resulting in low cost.

[0053] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A polymorphic SOT-MRAM memory cell, characterized in that, include: A magnetic tunnel junction, a bottom electrode, and a top electrode, wherein the bottom electrode is disposed in the lowest structural layer of the magnetic tunnel junction, and the top electrode is disposed in the highest structural layer of the magnetic tunnel junction; Specifically, when the voltages between the bottom and top electrodes are different, a potential difference is formed between the top and bottom of the magnetic tunnel junction. Simultaneously, by inputting different write voltages to the bottom electrode, the magnetic tunnel junction is controlled to exhibit different resistance states. The direction of the write voltage can be either positive or negative. When a potential difference exists, applying a write voltage changes the direction of the free layer magnetic moment in the magnetic tunnel junction. When the write voltage increases to V1, the magnetic tunnel junction exhibits a biased resistance state R2. Continuing to increase the write voltage, when it reaches V2, the direction of the free layer magnetic moment flips relative to its original state, and the magnetic tunnel junction exhibits a high magnetoresistance state R1 or a low magnetoresistance state R3. Continuing to increase the write voltage, the direction of the free layer magnetic moment remains unchanged, and the resistance state of the magnetic tunnel junction remains unchanged. Where |V1| < |V2|.

2. The SOT-MRAM memory cell with polymorphic storage as described in claim 1, characterized in that, The bottom electrode includes a first bottom electrode and a second bottom electrode, which are symmetrically disposed in the lowest structural layer of the magnetic tunnel junction. Different voltages are applied to the first bottom electrode and the second bottom electrode. The voltage at the midpoint between the first bottom electrode and the second bottom electrode is the voltage at the bottom of the magnetic tunnel junction.

3. The SOT-MRAM memory cell with polymorphic storage as described in claim 2, characterized in that, The voltage of the top electrode is set to 0. Different voltages are applied to the first bottom electrode and the second bottom electrode. The voltage of the top electrode is different from the voltage at the bottom of the magnetic tunnel junction, and a potential difference is formed between the top and bottom of the magnetic tunnel junction.

4. The SOT-MRAM memory cell with polymorphic storage as described in claim 2, characterized in that, By increasing the potential difference, the write voltage margin is increased.

5. The SOT-MRAM memory cell with polymorphic storage as described in claim 2, characterized in that, When the potential difference is 0, the positive and negative directions of the write voltage control the direction of the free layer magnetic moment in the magnetic tunnel junction to be parallel or antiparallel to the direction of the reference layer magnetic moment. The magnetic tunnel junction exhibits a low magnetoresistance state R3 or a high magnetoresistance state R1.

6. The SOT-MRAM memory cell with polymorphic storage as described in any one of claims 2 to 5, characterized in that, The first bottom electrode and the second bottom electrode are respectively connected to two channels of the pulse power supply; And / or, the top electrode is grounded.

7. The SOT-MRAM memory cell with polymorphic storage as described in any one of claims 1 to 5, characterized in that, The magnetic tunnel junction comprises, from bottom to top, a heavy metal layer, a free layer, an isolation layer, a reference layer, a pinning layer, and a capping layer.

8. A polymorphic SOT-MRAM memory array, characterized in that, It includes multiple SOT-MRAM memory cells with polymorphic storage as described in any one of claims 1 to 7.

9. A polymorphic SOT-MRAM memory, characterized in that, It includes at least one SOT-MRAM storage array as described in claim 8.

10. A method for implementing SOT-MRAM polymorphic storage, characterized in that, The method includes: achieving multi-resistivity storage of a single magnetic tunnel junction by applying voltages to both the top and bottom terminals of the magnetic tunnel junction, and simultaneously inputting different write voltages to the top and bottom electrodes, wherein the direction of the write voltages is either positive or negative. When a potential difference exists, applying a write voltage changes the direction of the free layer magnetic moment in the magnetic tunnel junction. When the write voltage increases to V1, the magnetic tunnel junction exhibits a biased resistance state R2. Continuing to increase the write voltage, when it reaches V2, the direction of the free layer magnetic moment flips relative to its original state, and the magnetic tunnel junction exhibits a high magnetoresistance state R1 or a low magnetoresistance state R3. Continuing to increase the write voltage, the direction of the free layer magnetic moment remains unchanged, and the resistance state of the magnetic tunnel junction remains unchanged. Where |V1| < |V2|.

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