A method of forming a semiconductor structure and a semiconductor structure

Abstract

Embodiments of the present application disclose a semiconductor structure forming method and a semiconductor structure, wherein the method comprises the following steps: providing a substrate, wherein a gate structure is formed on the substrate; forming a first sidewall covering sidewalls of the gate structure; the first sidewall has a first preset thickness in a direction parallel to a plane of the substrate; performing a first ion implantation on the substrate exposed to both sides of the gate structure; removing part of the first sidewall to form a second sidewall; the second sidewall has a second preset thickness in the direction parallel to the plane of the substrate; and performing a second ion implantation on the substrate on both sides of the gate structure, wherein a doping type of the first ion implantation is opposite to that of the second ion implantation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of manufacturing semiconductor devices, and in particular to a method for forming a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] With the continuous reduction of the size of MOSFET devices, especially into 65 nanometers and below nodes, MOSFET devices highlight various adverse physical effects due to extremely short channels, such as short channel effect (SCE) or gate induced drain leakage (GIDL), etc., which seriously restrict the improvement of device performance. Among them, the short channel effect determines the device channel length, threshold voltage, etc. that can be used, which degrades the device performance and reliability, and limits the further reduction of feature size. SUMMARY

[0003] Therefore, the embodiments of the present application provide a method for forming a semiconductor structure and the semiconductor structure.

[0004] According to a first aspect of the embodiments of the present application, a method for forming a semiconductor structure is provided, which comprises:

[0005] providing a substrate, wherein a gate structure is formed on the substrate;

[0006] forming a first sidewall covering the sidewall of the gate structure; the first sidewall has a first preset thickness in a direction parallel to the substrate plane;

[0007] performing a first ion implantation on the substrate exposed to both sides of the gate structure of the first sidewall;

[0008] removing part of the first sidewall to form a second sidewall; the second sidewall has a second preset thickness in a direction parallel to the substrate plane;

[0009] performing a second ion implantation on the substrate on both sides of the gate structure, wherein the doping type of the first ion implantation is opposite to that of the second ion implantation.

[0010] In some embodiments, the first preset thickness ranges from 5 to 10 μm; and the second preset thickness ranges from 1 to 5 μm.

[0011] In some embodiments, the first ion implantation is LDD ion implantation; and the second ion implantation is Halo ion implantation.

[0012] In some embodiments, the performing a first ion implantation on the substrate on both sides of the gate structure comprises:

[0013] The first preset angle is less than the second preset angle.

[0014] The second ion implantation to the substrate on both sides of the gate structure comprises:

[0015] The second preset angle is less than the first preset angle.

[0016] The first preset angle is less than the second preset angle.

[0017] In some embodiments, the first ion implantation to the substrate on both sides of the gate structure comprises:

[0018] The first preset dose is greater than the second preset dose.

[0019] The second ion implantation to the substrate on both sides of the gate structure comprises:

[0020] The first preset dose is greater than the second preset dose.

[0021] The first preset dose is greater than the second preset dose.

[0022] In some embodiments, the method further comprises:

[0023] After the second ion implantation, performing thermal diffusion to the substrate on both sides of the gate structure to form an LDD region and a Halo region in the substrate; wherein, in a projection along a direction perpendicular to the substrate plane, a projection of the LDD region does not overlap with a projection of the gate structure.

[0024] In some embodiments, after the LDD region and the Halo region are formed, the method further comprises:

[0025] forming a source region and a drain region by performing source-drain ion implantation to the substrate on both sides of the gate structure with the second side wall as a mask.

[0026] According to a second aspect of the embodiments of the present application, a method for forming a semiconductor structure is provided, which comprises:

[0027] providing a substrate, wherein a gate structure is formed on the substrate;

[0028] forming a third side wall covering the sidewall of the gate structure; the third side wall has a third preset thickness in a direction parallel to the substrate plane;

[0029] forming a fourth sidewall covering sidewalls of the third sidewall; the fourth sidewall has a fourth preset thickness in a direction parallel to the substrate plane; the third sidewall and the fourth sidewall have a high etching selectivity;

[0030] performing a first ion implantation on the substrate exposed to both sides of the gate structure by the third sidewall and the fourth sidewall;

[0031] removing the fourth sidewall;

[0032] performing a second ion implantation on the substrate exposed to both sides of the gate structure; wherein the first ion implantation and the second ion implantation are of opposite doping types.

[0033] In some embodiments, the third preset thickness ranges from 1-5 μm; the fourth preset thickness ranges from 4-5 μm.

[0034] In some embodiments, the first ion implantation is an LDD ion implantation; the second ion implantation is a Halo ion implantation.

[0035] In some embodiments, the performing a first ion implantation on the substrate exposed to both sides of the gate structure; comprises:

[0036] the first ion implantation has a first preset angle with a direction perpendicular to the substrate plane;

[0037] the performing a second ion implantation on the substrate exposed to both sides of the gate structure; comprises:

[0038] the second ion implantation has a second preset angle with a direction perpendicular to the substrate plane;

[0039] wherein the first preset angle is smaller than the second preset angle.

[0040] In some embodiments, the performing a first ion implantation on the substrate exposed to both sides of the gate structure; comprises:

[0041] the first ion implantation has a first preset dosage;

[0042] the performing a second ion implantation on the substrate exposed to both sides of the gate structure; comprises:

[0043] the second ion implantation has a second preset dosage;

[0044] wherein the first preset dosage is greater than the second preset dosage.

[0045] In some embodiments, further comprising:

[0046] After the second ion implantation, the substrate on both sides of the gate structure is subjected to thermal diffusion to form an LDD region and a Halo region in the substrate; wherein, in a projection along a direction perpendicular to a plane of the substrate, a projection of the LDD region does not overlap with a projection of the gate structure.

[0047] In some embodiments, after the LDD region and the Halo region are formed, the method further comprises:

[0048] The substrate on both sides of the gate structure is subjected to source-drain ion implantation to form a source region and a drain region, with the third sidewall as a mask.

[0049] According to a first aspect of the embodiments of the present application, a semiconductor structure is provided, comprising:

[0050] a substrate,

[0051] a gate structure on the substrate; a sidewall of the gate structure is formed with a sidewall;

[0052] an LDD region and a Halo region in the substrate; wherein,

[0053] in a projection along a direction perpendicular to a plane of the substrate, a projection of the LDD region does not overlap with a projection of the gate structure, and a projection of the Halo region has an overlapping part with the projection of the gate structure.

[0054] In some embodiments, the Halo region is subjected to ion implantation with a dose of 1×1013atoms / cm2. 13 2 .

[0055] In the embodiments of the present application, by first forming a first sidewall with a larger thickness, and performing a first ion implantation, i.e. LDD ion implantation, with the first sidewall as a mask, diffusion of the implanted ions to the channel can be effectively reduced, and generation of GIDL current is reduced. Then, part of the first sidewall is etched to form a second sidewall with a smaller thickness, and a second ion implantation, i.e. Halo ion implantation, is performed, and the Halo ions under the channel are increased, which can reduce SCE. Moreover, when the Halo ion implantation is performed, the second sidewall as a mask has a smaller thickness, and the Halo ions entering the channel are increased, so that the ion dose for reaching the same threshold voltage is correspondingly reduced, thereby reducing the generation of junction leakage. BRIEF DESCRIPTION OF DRAWINGS

[0056] Figure 1 a flowchart of a forming method of a semiconductor structure provided by the embodiments of the present application;

[0057] Figures 2a to 2g a structural schematic diagram of a semiconductor structure in a forming process provided by the embodiments of the present application;​

[0058] Figure 3 A flow chart of a method for forming a semiconductor structure according to another embodiment of the present application is provided;

[0059] Figures 4a to 4h A structure diagram of a semiconductor structure in a forming process according to an embodiment of the present application is provided;

[0060] Figure 5 A structure diagram of a semiconductor structure according to an embodiment of the present application is provided.

[0061] Explanation of reference numerals:

[0062] 10 - substrate;

[0063] 20 - gate structure; 21 - gate oxide layer; 22 - first gate conductive layer; 23 - second gate conductive layer; 24 - gate insulating layer;

[0064] 30 - side wall; 31 - first side wall; 32 - second side wall; 33 - third side wall; 34 - fourth side wall;

[0065] 410 - LDD ion implantation region; 41 - LDD region; 42 - Halo region;

[0066] 51 - source region; 52 - drain region. DETAILED DESCRIPTION

[0067] The exemplary embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the application but there can be many variations to the embodiments and they should not be treated as limiting the application as they merely present some of the ways to implement the application. Rather, the application should only be limited by the scope of the claims.

[0068] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known structures are not shown in detail in order not to obscure the application. As such, it will be understood that the application can be practiced with modification and alteration, and that the

[0069] In the drawings, the size of layers, regions, elements and the like can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0070] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0071] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0073] For a thorough understanding of the application, detailed steps and detailed structures will be presented in the following description, in order to explain the technical solutions of the application. The preferred embodiments of the application are described in detail as follows, however, in addition to these detailed descriptions, the application can also have other implementation manners.

[0074] In the MOS device, after the polysilicon gate etching is formed, a side wall is formed on the gate side wall as a barrier layer for LDD and Halo ion implantation. The LDD ion implantation is generally zero degree or small angle implantation, and the Halo ion implantation needs to be implanted into the MOS channel below at a larger angle.

[0075] The LDD and Halo implanted ions diffuse by heat, the LDD ions diffuse to the channel, increase the area covered by the drain and the gate, and cause the generation of GIDL current. The Halo implanted ions greatly affect the performance of the short channel device, by adjusting the Halo ion implantation angle and ion dose, the threshold voltage, channel current and off current of the device can be adjusted, and the change of junction leakage will also be affected. The Halo ion dose is related to the threshold voltage of the MOS device, but the Halo ion implantation angle is affected by the shadow effect, to achieve the predetermined threshold voltage, more ion dose needs to be implanted, and the increase of ion dose will also cause the generation of junction leakage.

[0076] Based on this, the embodiment of the application provides a semiconductor structure forming method, please refer to the accompanying drawings Figure 1 As shown in the figure, the method comprises the following steps:

[0077] Step 101: providing a substrate, a gate structure is formed on the substrate;

[0078] Step 102: forming a first side wall covering the side wall of the gate structure; the first side wall has a first preset thickness in the direction parallel to the substrate plane;

[0079] Step 103: performing first ion implantation on the substrate exposed to both sides of the gate structure of the first side wall;

[0080] Step 104: removing part of the first side wall to form a second side wall; the second side wall has a second preset thickness in the direction parallel to the substrate plane;

[0081] Step 105: performing second ion implantation on the substrate on both sides of the gate structure, wherein the doping type of the first ion implantation is opposite to that of the second ion implantation.

[0082] The forming method of the semiconductor structure provided by the embodiments of the present application will be further described in detail below with specific embodiments.

[0083] Figures 2a to 2g The structure schematic diagram of the semiconductor structure provided by the embodiments of the present application in the forming process.

[0084] Firstly, referring to Figure 2a , a step 101 is performed to provide a substrate 10, wherein the substrate 10 is formed with a gate structure 20.

[0085] The substrate 10 can be a single-element semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (for example, a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0086] The gate structure 20 comprises, from bottom to top, a gate oxide layer 21, a first gate conductive layer 22, a second gate conductive layer 23 and a gate insulating layer 24.

[0087] The material of the gate oxide layer 21 includes but is not limited to silicon oxide; the material of the first gate conductive layer 22 includes but is not limited to titanium nitride; the material of the second gate conductive layer 23 includes but is not limited to metal tungsten; and the material of the gate insulating layer 24 includes but is not limited to silicon nitride.

[0088] Next, referring to Figure 2b , a step 102 is performed to form a first side wall 31 covering the sidewall of the gate structure 20; the first side wall 31 has a first preset thickness in the direction parallel to the plane of the substrate 10.

[0089] The first side wall 31 can be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluorine-doped silicon glass, low-k dielectric material and combinations thereof, and / or other suitable materials.

[0090] The first preset thickness is h1 shown in Figure 2b . In an embodiment, the first preset thickness ranges from 5 to 10 μm.

[0091] Next, referring to Figure 2c , a step 103 is performed to perform a first ion implantation on the substrate 10 exposed to both sides of the gate structure 20.

[0092] In an embodiment, the first ion implantation is LDD ion implantation.

[0093] After the first ion implantation, an LDD ion implantation region 410 is formed in the substrate 10 on both sides of the gate structure 20.

[0094] Next, referring to Figure 2d , a step 104 is performed to remove part of the first side wall 31 to form a second side wall 32; the second side wall 32 has a second preset thickness in a direction parallel to the plane of the substrate 10.

[0095] The second preset thickness is h2 as shown in Figure 2d In an embodiment, the second preset thickness ranges from 1 to 5 μm.

[0096] Next, referring to Figure 2e , a step 105 is performed to perform a second ion implantation on the substrate 10 on both sides of the gate structure 20, wherein the doping type of the first ion implantation is opposite to that of the second ion implantation.

[0097] In an embodiment, the second ion implantation is a Halo ion implantation.

[0098] The doping type of the first ion implantation is opposite to that of the second ion implantation, i.e. the doping type of the LDD ion implantation is opposite to that of the Halo ion implantation. Specifically, taking NMOS as an example, the doping type of the LDD ion implantation is N type, and the doping type of the Halo ion implantation is P type.

[0099] In an embodiment, the step of performing the first ion implantation on the substrate 10 on both sides of the gate structure 20 comprises: the angle between the direction of the first ion implantation and the direction perpendicular to the plane of the substrate 10 is a first preset angle; the step of performing the second ion implantation on the substrate 10 on both sides of the gate structure 20 comprises: the angle between the direction of the second ion implantation and the direction perpendicular to the plane of the substrate 10 is a second preset angle; wherein the first preset angle is smaller than the second preset angle.

[0100] When performing the first ion implantation, i.e. LDD ion implantation, vertical implantation or small-angle implantation is generally used. The first preset angle ranges from 0° to 3°.

[0101] When performing the second ion implantation, i.e. Halo ion implantation, large-angle implantation is generally used. The second preset angle ranges from 21° to 30°.

[0102] Vertical implantation or small-angle implantation of LDD ions can make the LDD ions more dispersed in the substrate on both sides of the gate structure, reduce the diffusion of LDD ions to the substrate below the gate structure, and thus reduce the generation of GIDL current. Large-angle implantation of Halo ions can increase the Halo ions entering the substrate below the gate structure, so as to reduce the diffusion of LDD ions and also reduce SCE.

[0103] In one embodiment, the first ion implantation of the substrates 10 on both sides of the gate structure 20 includes: the dose of the first ion implantation is a first preset dose; the second ion implantation of the substrates 10 on both sides of the gate structure 20 includes: the dose of the second ion implantation is a second preset dose; wherein the first preset dose is greater than the second preset dose.

[0104] The first preset dose is 1×10 14 atoms / cm 2 The second preset dose is 1×10 13 atoms / cm 2 .

[0105] Next, see Figure 2f After the second ion implantation, thermal diffusion is performed on the substrate 10 on both sides of the gate structure 20 to form LDD region 41 and Halo region 42 in the substrate; wherein, in the projection along the direction perpendicular to the plane of the substrate 10, the projection of the LDD region 41 does not overlap with the projection of the gate structure 20.

[0106] In some embodiments, the projection of the LDD region 41 does not overlap with the projection of the gate structure 20, including: the sidewall of the LDD region 41 is flush with the sidewall of the gate structure 20.

[0107] In this embodiment, because the first sidewall has a large preset thickness, when LDD ion implantation is performed using the first sidewall as a mask, the diffusion of implanted ions into the channel can be effectively reduced. Therefore, the projection of the LDD region does not overlap with the projection of the gate structure.

[0108] After thermal diffusion, the LDD ion implantation region 410 forms the LDD region 41.

[0109] Next, see Figure 2g After forming LDD region 41 and Halo region 42, the method further includes:

[0110] Using the second sidewall 32 as a mask, source and drain ion implantation is performed on the substrate 10 on both sides of the gate structure 20 to form source region 51 and drain region 52.

[0111] The doping type of the source / drain ion implantation is the same as that of the LDD ion implantation, and opposite to that of the Halo ion implantation. Specifically, if the doping type of the LDD ion implantation is P-type, then the doping type of the Halo ion implantation is N-type, and the doping type of the source / drain ion implantation is P-type.

[0112] In the embodiment of the present application, the first side wall with a large thickness is formed first, and the first side wall is used as a mask to perform the first ion implantation, i.e. LDD ion implantation, so as to effectively reduce the diffusion of the implanted ions to the channel and reduce the generation of GIDL current. Then, part of the first side wall is etched to form the second side wall with a small thickness, and the second ion implantation, i.e. Halo ion implantation, is performed to increase the Halo ions under the channel, so as to reduce SCE.

[0113] In the embodiment of the present application, when the Halo ion implantation is performed, the second side wall used as a mask has a small thickness, and the Halo ions entering the channel are increased, so that the ion dosage for reaching the same threshold voltage is correspondingly reduced, thereby reducing the generation of junction leakage.

[0114] The embodiment of the present application also provides a forming method of a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Figure 3 As shown in the drawings, the method comprises the following steps:

[0115] Step 301: providing a substrate, wherein a gate structure is formed on the substrate;

[0116] Step 302: forming a third side wall covering the sidewall of the gate structure; the third side wall has a third preset thickness in a direction parallel to the substrate plane;

[0117] Step 303: forming a fourth side wall covering the sidewall of the third side wall; the fourth side wall has a fourth preset thickness in a direction parallel to the substrate plane; the third side wall and the fourth side wall have a high etching selectivity;

[0118] Step 304: performing the first ion implantation on the substrate exposed to both sides of the gate structure through the third side wall and the fourth side wall;

[0119] Step 305: removing the fourth side wall;

[0120] Step 306: performing the second ion implantation on the substrate on both sides of the gate structure; wherein the doping type of the first ion implantation is opposite to that of the second ion implantation.

[0121] The forming method of the semiconductor structure provided by the embodiment of the present application will be described in further detail below in combination with specific embodiments.

[0122] Figures 4a to 4h The structure schematic diagram of the semiconductor structure provided by the embodiment of the present application in the forming process is shown in the following figure.

[0123] Firstly, referring to Figure 4a , step 301 is performed to provide a substrate 10, wherein a gate structure 20 is formed on the substrate 10.

[0124] The substrate 10 can be a single-element semiconductor material substrate (for example, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (for example, a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0125] The gate structure 20 includes, from bottom to top, a gate oxide layer 21, a first gate conductive layer 22, a second gate conductive layer 23, and a gate insulating layer 24.

[0126] The material of the gate oxide layer 21 includes, but is not limited to, silicon oxide; the material of the first gate conductive layer 22 includes, but is not limited to, titanium nitride; the material of the second gate conductive layer 23 includes, but is not limited to, metallic tungsten; and the material of the gate insulating layer 24 includes, but is not limited to, silicon nitride.

[0127] Next, referring to Figure 4b , a step 302 is performed to form a third sidewall 33 covering the sidewall of the gate structure 20; the third sidewall 33 has a third preset thickness in a direction parallel to the plane of the substrate 10.

[0128] The third sidewall 33 can be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluorine-doped silicon glass, low-k dielectric material, combinations thereof, and / or other suitable materials.

[0129] The third preset thickness is h3 as shown in Figure 4b In an embodiment, the third preset thickness ranges from 1 to 5 μm.

[0130] Next, referring to Figure 4c , a step 303 is performed to form a fourth sidewall 34 covering the sidewall of the third sidewall 33; the fourth sidewall 34 has a fourth preset thickness in a direction parallel to the plane of the substrate 10; the third sidewall 33 and the fourth sidewall 34 have a high etching selectivity.

[0131] The fourth sidewall 34 can be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluorine-doped silicon glass, low-k dielectric material, combinations thereof, and / or other suitable materials.

[0132] The fourth preset thickness is h4 as shown in Figure 4c In an embodiment, the fourth preset thickness ranges from 4 to 5 μm.

[0133] In the embodiments of the present application, by setting the third sidewall 33 and the fourth sidewall 34 to have a high etching selectivity, the fourth sidewall located at the outer layer can be selectively etched away, and compared with using the same material, this scheme is easier to control the etching degree and reduce the process difficulty.

[0134] Next, referring to Figure 4d , a first ion implantation is performed on the substrate 10 on both sides of the gate structure 20 exposed to the third side wall 33 and the fourth side wall 34.

[0135] In an embodiment, the first ion implantation is an LDD ion implantation.

[0136] After the first ion implantation, an LDD ion implantation region 410 is formed in the substrate 10 on both sides of the gate structure 20.

[0137] Next, referring to Figure 4e , a step 305 is performed to remove the fourth side wall 34.

[0138] Next, referring to Figure 4f , a step 306 is performed to perform a second ion implantation on the substrate 10 on both sides of the gate structure 20; wherein the doping type of the first ion implantation is opposite to that of the second ion implantation.

[0139] In an embodiment, the second ion implantation is a Halo ion implantation.

[0140] The doping type of the first ion implantation is opposite to that of the second ion implantation, that is, the doping type of the LDD ion implantation is opposite to that of the Halo ion implantation. Specifically, taking NMOS as an example, the doping type of the LDD ion implantation is N type, and the doping type of the Halo ion implantation is P type.

[0141] In an embodiment, the first ion implantation on the substrate 10 on both sides of the gate structure 20 comprises: the angle between the direction of the first ion implantation and the direction perpendicular to the plane of the substrate 10 is a first preset angle; and the second ion implantation on the substrate 10 on both sides of the gate structure 20 comprises: the angle between the direction of the second ion implantation and the direction perpendicular to the plane of the substrate 10 is a second preset angle; wherein the first preset angle is smaller than the second preset angle.

[0142] When performing the first ion implantation, that is, the LDD ion implantation, it is generally perpendicular or small-angle implantation. The range of the first preset angle is 0°-3°.

[0143] When performing the second ion implantation, that is, the Halo ion implantation, it is generally large-angle implantation. The range of the second preset angle is 21°-30°.

[0144] The vertical injection or low-angle injection of LDD ions can make the LDD ions more dispersed in the substrate on both sides of the gate structure, reduce the diffusion of the LDD ions to the substrate under the gate structure, and further reduce the generation of GIDL current. The high-angle injection of Halo ions can increase the Halo ions entering the substrate under the gate structure, reduce the diffusion of the LDD ions, and also reduce SCE.

[0145] In an embodiment, the first ion injection to the substrate 10 on both sides of the gate structure 20 comprises: the dose of the first ion injection is a first preset dose; and the second ion injection to the substrate 10 on both sides of the gate structure 20 comprises: the dose of the second ion injection is a second preset dose; wherein the first preset dose is greater than the second preset dose.

[0146] The first preset dose is 1×1013 atoms / cm2. 14 The second preset dose is 1×1012 atoms / cm2. 2 . 13 The second preset dose is 1×1012 atoms / cm2. 2 .

[0147] Next, referring to Figure 4g After the second ion injection, the substrate 10 on both sides of the gate structure 20 is subjected to thermal diffusion to form an LDD region 41 and a Halo region 42 in the substrate; wherein the projection of the LDD region 41 does not overlap with the projection of the gate structure 20 in the projection along the direction perpendicular to the plane of the substrate 10.

[0148] In some embodiments, the projection of the LDD region 41 does not overlap with the projection of the gate structure 20, comprising: the sidewall of the LDD region 41 is flush with the sidewall of the gate structure 20.

[0149] In this embodiment, because the third sidewall and the fourth sidewall have a large preset thickness, when LDD ion injection is performed with the third sidewall and the fourth sidewall as a mask, the diffusion of the injected ions to the channel can be effectively reduced, and therefore the projection of the LDD region does not overlap with the projection of the gate structure.

[0150] After the LDD ion injection region 410 is subjected to thermal diffusion, the LDD region 41 is formed.

[0151] Next, referring to Figure 4h After the LDD region 41 and the Halo region 42 are formed, the method further comprises:

[0152] The source / drain ion injection to the substrate 10 on both sides of the gate structure 20 is performed with the third sidewall 33 as a mask to form a source region 51 and a drain region 52.

[0153] The doping type of the source / drain ion implantation is the same as that of the LDD ion implantation, and opposite to that of the Halo ion implantation. Specifically, if the doping type of the LDD ion implantation is P-type, then the doping type of the Halo ion implantation is N-type, and the doping type of the source / drain ion implantation is P-type.

[0154] This application also provides a semiconductor structure. Figure 5 This is a schematic diagram of the semiconductor structure provided in an embodiment of this application.

[0155] like Figure 5 As shown, the semiconductor structure includes: a substrate 10, a gate structure 20 located on the substrate 10; a sidewall 30 formed on the sidewall of the gate structure 20; an LDD region 41 and a Halo region 42 located within the substrate 10; wherein, in a projection along a direction perpendicular to the plane of the substrate 10, the projection of the LDD region 41 does not overlap with the projection of the gate structure 20, and the projection of the Halo region 42 overlaps with the projection of the gate structure 20.

[0156] The substrate 10 can be a single-element semiconductor material substrate (e.g., silicon (Si) substrate, germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

[0157] The gate structure 20 includes, from bottom to top, a gate oxide layer 21, a first gate conductive layer 22, a second gate conductive layer 23, and a gate insulating layer 24.

[0158] The material of the gate oxide layer 21 includes, but is not limited to, silicon oxide; the material of the first gate conductive layer 22 includes, but is not limited to, titanium nitride; the material of the second gate conductive layer 23 includes, but is not limited to, tungsten metal; and the material of the gate insulating layer 24 includes, but is not limited to, silicon nitride.

[0159] The sidewall 30 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric materials and combinations thereof, and / or other suitable materials.

[0160] The preset thickness of the sidewall 30 is in the range of 1-5 μm.

[0161] In some embodiments, the projection of the LDD region 41 does not overlap with the projection of the gate structure 20, including: the sidewall of the LDD region 41 is flush with the sidewall of the gate structure 20.

[0162] In one embodiment, the doping types of the LDD region 41 and the Halo region 42 are opposite. Specifically, taking NMOS as an example, if the doping type of the LDD region is N-type, then the doping type of the Halo region is P-type.

[0163] The ion implantation dose in the LDD region 41 is 1×10⁻⁶. 14 atoms / cm 2 The ion implantation dose in the Halo region 42 is 1×10⁻⁶. 13 atoms / cm 2 .

[0164] In one embodiment, the semiconductor structure further includes a source region 51 and a drain region 52, wherein the source region 51 and the drain region 52 are respectively located within the substrate 10 on both sides of the gate structure 20.

[0165] The doping type of the source region 51 and the drain region 52 is the same as that of the LDD region and the opposite of that of the Halo region. Specifically, if the doping type of the LDD region is P-type, then the doping type of the Halo region is N-type, and the doping type of the source region 51 and the drain region 52 is P-type.

[0166] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate with a gate structure formed thereon; forming a first sidewall covering sidewalls of the gate structure; the first sidewall has a first preset thickness in a direction parallel to a substrate plane; performing a first ion implantation on the substrate exposed to both sides of the gate structure; removing part of the first sidewall to form a second sidewall; the second sidewall has a second preset thickness in a direction parallel to the substrate plane; performing a second ion implantation on the substrate exposed to both sides of the gate structure, wherein the first ion implantation and the second ion implantation are of opposite doping types, the first ion implantation is an LDD ion implantation, and the second ion implantation is a Halo ion implantation; after the second ion implantation, performing thermal diffusion on the substrate exposed to both sides of the gate structure to form an LDD region and a Halo region in the substrate; in a projection along a direction perpendicular to the substrate plane, a projection of the LDD region does not overlap with a projection of the gate structure.

2. The method of claim 1, wherein: the first preset thickness ranges from 5 to 10 μm, and the second preset thickness ranges from 1 to 5 μm.

3. The method of claim 1, wherein: the first ion implantation on the substrate exposed to both sides of the gate structure comprises: an angle between a direction of the first ion implantation and a direction perpendicular to the substrate plane is a first preset angle; the second ion implantation on the substrate exposed to both sides of the gate structure comprises: an angle between a direction of the second ion implantation and a direction perpendicular to the substrate plane is a second preset angle; and the first preset angle is smaller than the second preset angle.

4. The method of claim 1, wherein: the first ion implantation on the substrate exposed to both sides of the gate structure comprises: a dose of the first ion implantation is a first preset dose; the second ion implantation on the substrate exposed to both sides of the gate structure comprises: a dose of the second ion implantation is a second preset dose; and the first preset dose is greater than the second preset dose.

5. The method of claim 1, wherein, After the LDD region and the Halo region are formed, the method further comprises: performing a source-drain ion implantation on the substrate exposed to both sides of the gate structure with the second sidewall as a mask to form a source region and a drain region.

6. A method of forming a semiconductor structure, comprising: The method comprises: providing a substrate with a gate structure formed thereon; forming a third sidewall covering sidewalls of the gate structure; the third sidewall has a third preset thickness in a direction parallel to a substrate plane; forming a fourth sidewall covering sidewalls of the third sidewall; the fourth sidewall has a fourth preset thickness in a direction parallel to the substrate plane; the third sidewall and the fourth sidewall have a high etching selectivity; performing a first ion implantation on the substrate exposed to both sides of the gate structure; removing the fourth sidewall; and performing a second ion implantation on the substrate exposed to both sides of the gate structure. The substrate on both sides of the gate structure is subjected to a second ion implantation; wherein the doping type of the first ion implantation is opposite to that of the second ion implantation.

7. The method of claim 6, wherein, The third preset thickness ranges from 1 to 5 μm; and the fourth preset thickness ranges from 4 to 5 μm.

8. The method of claim 7, wherein, The first ion implantation is LDD ion implantation; and the second ion implantation is Halo ion implantation.

9. The method of claim 8, wherein, The first ion implantation on both sides of the gate structure includes: The angle between the direction of the first ion implantation and the direction perpendicular to the substrate plane is a first preset angle; The second ion implantation on both sides of the gate structure includes: The angle between the direction of the second ion implantation and the direction perpendicular to the substrate plane is a second preset angle; The first preset angle is smaller than the second preset angle.

10. The method of claim 8, wherein, The first ion implantation on both sides of the gate structure includes: The dose of the first ion implantation is a first preset dose; The second ion implantation on both sides of the gate structure includes: The dose of the second ion implantation is a second preset dose; The first preset dose is greater than the second preset dose.

11. The method of claim 8, wherein, Further comprising: After the second ion implantation, the substrate on both sides of the gate structure is subjected to thermal diffusion to form an LDD region and a Halo region in the substrate; wherein, in the projection along the direction perpendicular to the substrate plane, the projection of the LDD region does not overlap with the projection of the gate structure.

12. The method of claim 11, wherein, After the LDD region and the Halo region are formed, the method further comprises: With the third side wall as a mask, source-drain ion implantation is performed on the substrate on both sides of the gate structure to form a source region and a drain region.

13. A semiconductor structure formed according to the method of any one of claims 1-5. Comprise: a substrate, a gate structure on the substrate; a side wall of the gate structure is formed with a side wall; an LDD region and a Halo region in the substrate; wherein, in the projection along the direction perpendicular to the substrate plane, the projection of the LDD region does not overlap with the projection of the gate structure, and the projection of the Halo region has an overlapping part with the projection of the gate structure.

14. The semiconductor structure of claim 13, wherein, The dose of ion implantation of the Halo region is 1 x 10 13 atoms / cm 2 .

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