Bipolar transistor device and method of making the same

Abstract

The application provides a bipolar transistor device and a manufacturing method thereof, which comprises the following steps: providing a substrate, wherein an outer collector region is formed in the substrate, and a first isolation layer is formed on the substrate surface of the outer collector region; sequentially forming an outer base region layer and a second isolation layer on the substrate surface, and forming an opening in the outer base region layer and the second isolation layer, wherein the opening exposes the first isolation layer; forming a first side wall on the sidewall of the opening; forming a second side wall, wherein the second side wall covers the sidewall of the lower part of the first side wall, and the first isolation layer is exposed by wet etching; and forming an emitter. After the first side wall is formed, the second side wall is formed before wet etching, the second side wall acts as a barrier layer in the wet etching process, the second side wall is consumed in the wet etching process, the first isolation layer below the second side wall is protected, and the first isolation layer is prevented from being side etched in the wet etching process. The sidewall of the first isolation layer is regular, which is beneficial to the filling of the subsequent emitter.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a bipolar transistor device and a manufacturing method thereof. BACKGROUND

[0002] BiCMOS integrated circuit devices integrating bipolar transistors (BJT) and metal oxide semiconductor field effect transistors (MOSFET), which have both the technical advantages of bipolar transistors and MOSFETs and high integration, have been manufactured and applied in the semiconductor industry for decades.

[0003] A bipolar transistor is a semiconductor device composed of two p-n junctions in close proximity to each other. A typical bipolar transistor includes three device regions and terminals: the emitter, the base, and the collector. If the emitter and collector are N-type doped and the base is P-type doped, the device is an "NPN" transistor. Alternatively, if an opposite doping structure is used, the device is a "PNP" transistor.

[0004] In the process of manufacturing a bipolar transistor, in the process of wet etching the oxide layer on the surface of the substrate in the emitter window, the wet etching liquid not only exposes the substrate by etching downward on the oxide layer, but also damages the side of the oxide layer, i.e., the oxide layer is drilled and etched on both sides to form a recess. The existence of the recess is not conducive to the subsequent filling of the emitter in the wet etched emitter window. SUMMARY

[0005] The purpose of the present application is to provide a bipolar transistor device and a manufacturing method thereof. By forming a second side wall as a barrier layer, the second side wall is sacrificed in the wet etching process, and the first isolation layer below the second side wall is protected, avoiding the side etching of the first isolation layer in the wet etching process. The side wall of the first isolation layer is regular, which is conducive to the subsequent filling of the emitter.

[0006] The present application provides a manufacturing method of a bipolar transistor device, comprising:

[0007] A substrate is provided, and an outer collector region is formed in the substrate. A first isolation layer is formed on the surface of the substrate of the outer collector region. An outer base region layer and a second isolation layer are sequentially formed on the surface of the substrate. An opening is formed in the outer base region layer and the second isolation layer, and the opening exposes the first isolation layer. A first side wall is formed on the side wall of the opening.

[0008] A second side wall is formed, which covers the side wall of the lower part of the first side wall, and the bottom of the second side wall is located on the first isolation layer.

[0009] The first isolation layer is wet etched to expose the substrate.

[0010] forming an emitter, the emitter filling an emitter window surrounded by the first spacer and the first isolation layer after wet etching.

[0011] Further, forming the second spacer, specifically comprising:

[0012] forming a spacer material layer, the spacer material layer covering at least sidewalls of the first spacer and the exposed first isolation layer;

[0013] dry etching the spacer material layer to expose part of the first isolation layer, and etching the remaining spacer material layer as the second spacer.

[0014] Further, the process of dry etching the spacer material layer to form the second spacer comprises: the etching gas is a mixed gas of a multi-fluorine fluorine-based gas, a chlorine-based gas and an auxiliary gas.

[0015] Further, the multi-fluorine fluorine-based gas is a combination of one or more of SiF4, NF3, SF6, CF4, CF3I, CHF3, CH3F, CH2F2, C2F6, C2F6, C3F8 and C4F8.

[0016] Further, the sidewall of the first isolation layer exposed after wet etching is perpendicular to the surface of the substrate.

[0017] Further, the material of the outer base region layer and the emitter is polysilicon.

[0018] Further, the material of the first isolation layer comprises silicon oxide or silicon oxynitride.

[0019] Further, the substrate located on both sides of the outer collector region is formed with a collector lead-out region, and the substrate between the outer collector region and the collector lead-out region is formed with an isolation region.

[0020] Further, after forming the emitter, the method further comprises:

[0021] etching the second isolation layer and the outer base region layer to form an outer base region, the outer base region covering part of the outer collector region and part of the isolation region, and exposing the collector lead-out region.

[0022] The application further provides a bipolar transistor device, comprising:

[0023] A substrate has an outer collector region formed therein; the substrate surface successively has an outer base region layer and a second isolation layer formed thereon, the outer base region layer and the second isolation layer have an opening formed therein, the side wall on both sides of the opening is formed with a stacked first isolation layer and a first side wall; the first isolation layer and the first side wall enclose an emitter window, and the emitter window is filled with an emitter, and the emitter is located on the substrate surface of the outer collector region.

[0024] Compared with the prior art, the present application has the following beneficial effects:

[0025] The present application provides a bipolar transistor device and a manufacturing method thereof, comprising: providing a substrate, the substrate has an outer collector region formed therein, and the substrate surface of the outer collector region has a first isolation layer formed thereon; the substrate surface successively has an outer base region layer and a second isolation layer formed thereon, the outer base region layer and the second isolation layer have an opening formed therein, and the opening exposes the first isolation layer; the side wall of the opening has a first side wall formed thereon; a second side wall is formed, the second side wall covers the side wall of the lower part of the first side wall, and the first isolation layer is exposed by wet etching; and an emitter is formed. After the first side wall is formed, the second side wall is formed before wet etching, the second side wall acts as a barrier layer during the wet etching process, the second side wall is sacrificed during the wet etching process, the first isolation layer below the second side wall is protected, and the first isolation layer is prevented from being side-pitted during the wet etching process. The side wall of the first isolation layer is regular, which is beneficial to the subsequent filling of the emitter. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A manufacturing method flow chart of a bipolar transistor device of an embodiment of the present application.

[0027] Figures 2 to 7 A manufacturing method flow chart of a bipolar transistor device of an embodiment of the present application.

[0028] Wherein, the reference signs are as follows:

[0029] 10-substrate; 11-buried layer; 12-outer collector region; 13-isolation region; 14-collector lead-out region; 21-outer base region layer; 210-outer base region; 22-second isolation layer; 23-first isolation layer; a-recess; 24-first side wall; 25-side wall material layer; 250-second side wall; 26-emitter; K-opening; C-emitter window. DETAILED DESCRIPTION

[0030] The present application will be further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and features of the present application will be more apparent. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0031] For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "rear", "front", "vertical", "horizontal", and derivatives thereof shall relate to the application as oriented in use. There can be other structures or components described and / or shown herein which have not been described in detail herein in the interest of clarity and / or brevity. However, it should be understood by those skilled in the art that those structures or components can be added to or otherwise included in the described embodiments without departing from the scope of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will be understood that the terms "first", "second", etc. are used herein only to distinguish one element from another, and do not otherwise limit the elements. These terms are not necessarily used consistently in all instances.

[0032] The present application provides a method for manufacturing a bipolar transistor device, as shown in Figure 1 The present application provides a method for manufacturing a bipolar transistor device, as shown in

[0033] In step S1, a substrate is provided, in which an outer collector region is formed, and a first isolation layer is formed on the substrate surface of the outer collector region; an outer base region layer and a second isolation layer are sequentially formed on the substrate surface, an opening is formed in the outer base region layer and the second isolation layer, the opening exposes the first isolation layer; a first side wall is formed on the sidewall of the opening;

[0034] In step S2, a second side wall is formed, which covers the sidewall of the lower part of the first side wall, and the bottom of the second side wall is located on the first isolation layer;

[0035] In step S3, the first isolation layer is etched by wet etching to expose the substrate;

[0036] In step S4, an emitter is formed, which fills the emitter window formed by the first side wall and the first isolation layer after wet etching.

[0037] The steps of the method for manufacturing a bipolar transistor device according to the embodiments of the present application will be described below. Figures 2 to 7 The steps of the method for manufacturing a bipolar transistor device according to the embodiments of the present application will be described below.

[0038] As shown in Figure 2As shown, a substrate 10 is provided, and a buried layer 11 is formed in the substrate 10 by ion implantation or thermal oxidation. An external collector region 12, an isolation region 13, and a collector lead-out region 14 are formed on the substrate 10 and the buried layer 11. A first isolation layer 23 is formed on the upper surface of the external collector region 12. The material of the first isolation layer 23 includes silicon oxide or silicon oxynitride. An outer base layer 21 is formed, which covers the first isolation layer 23 and the surface of the substrate 10. The material of the outer base layer 21 includes polycrystalline silicon, and the process for forming the outer base layer 21 is a deposition process, such as plasma chemical vapor deposition, low-pressure chemical vapor deposition, or sub-atmospheric pressure chemical vapor deposition. A second isolation layer 22 is formed on the upper surface of the outer base layer 21, which can be achieved by PVD (physical vapor deposition) or CVD (chemical vapor deposition). The second isolation layer 22 includes, for example, one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, silicon carbide nitride, and silicon carbide nitride. The substrate 10 is made of materials including, but not limited to, Si, Ge, SiGe, GaAs, InAs, InP, and all other group III / V compound semiconductors. The substrate 10 may also be a layered substrate comprising the same or different semiconducting materials such as Si, SiGe, etc.

[0039] An opening K is formed in the second isolation layer 22 and the outer base layer 21 by photolithography and etching, exposing the first isolation layer 23. A first sidewall 24 is formed, located on the sidewall of the opening K, with its bottom surface on the first isolation layer 23. The first sidewall 24 can be a nitride film or a oxynitride film.

[0040] like Figure 3 As shown, a sidewall material layer 25 is formed, which at least covers the sidewall of the first sidewall 24 and the first isolation layer 23. The deposition thickness of the sidewall material layer 25 can be adjusted as needed.

[0041] like Figure 4As shown, the sidewall material layer 25 is dry-etched, exposing a portion of the first isolation layer 23. The remaining sidewall material layer 25 is etched to form a second sidewall 250. The second sidewall 250 covers the lower portion (closer to the first isolation layer 23) of the sidewall of the first sidewall 24, and the bottom of the second sidewall 250 covers a portion of the first isolation layer 23. The material of the second sidewall 250 includes silicon oxide or silicon oxynitride. The process parameters for dry etching of the sidewall material layer 25 include: the etching gas is a mixture of polyfluorofluorocarbon gas, chlorine-based gas, and auxiliary gas. The polyfluorofluorocarbon gas is one or a combination of several of SiF4, NF3, SF6, CF4, CF3I, CHF3, CH3F, CH2F2, C2F6, C2F6, C3F8, and C4F8. The chlorine-based gas includes one or a combination of several of Cl2, CH2Cl2, and CH3Cl. The auxiliary gas is one or a combination of several of the following: O2, N2, NO, N2O, NH3CO, CO2, COS, He, H2, and Ar.

[0042] Figure 5 As a counterexample, when the second sidewall 250 is not formed on the sidewall of the first sidewall 24, the first isolation layer 23 is directly wet-etched and side-holes (drilling) occur. As the etching solution used in wet etching, such as HF solution, corrodes the first isolation layer 23 downwards, the periphery of the first isolation layer 23 is also damaged. That is, the first isolation layer 23 drills to both sides to form depressions aa. The existence of these depressions a is not conducive to the subsequent filling of the emitter 26 in the space enclosed by the first sidewall 24 and the first isolation layer 23.

[0043] like Figure 4 and Figure 6 As shown, wet etching of the first isolation layer 23 exposes the substrate 10. During wet etching, the second sidewall 250 acts as a barrier layer. The second sidewall 250 is sacrificed during wet etching, protecting the first isolation layer 23 beneath it and preventing side cuts from forming. For example, the sidewalls of the formed first isolation layer 23 are perpendicular to the surface of the substrate 10, and the regularity of the sidewalls facilitates the subsequent filling of the emitter 26. The first sidewall 24 and the first isolation layer 23 after wet etching form the emitter window C.

[0044] like Figure 7As shown, the emitter 26 is formed, and the material of the emitter 26 includes polysilicon, and the emitter 26 is formed by a deposition process, such as a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process. Specifically, a deposition process can be used to form a layer of the material of the emitter 26 in the emitter window C and on the surface of the second isolation layer 22, and a chemical mechanical polishing (CMP) process is used to planarize the layer of the material of the emitter 26, and the planarization is stopped when the second isolation layer 22 is reached, and the layer of the material of the emitter 26 remaining in the emitter window C serves as the emitter 26. The first isolation layer 23 separates the emitter 26 from the outer base region 210.

[0045] Next, photoresist is coated on the surfaces of the second isolation layer 22 and the emitter 26, and the outer base region 210 is defined by photolithography and etching. The outer base region 210 covers part of the outer collector region 12 and part of the isolation region 13, and exposes the collector lead-out region 14. Subsequently, a dielectric layer (not shown) covering the substrate 10, the outer base region 210, and the second isolation layer 22 can be formed, and contact holes are formed in the dielectric layer to lead out from the collector lead-out region 14, the emitter 26, and the outer base region, respectively.

[0046] The present application also provides a bipolar transistor device, such as Figure 7 As shown, the bipolar transistor device comprises:

[0047] The substrate 10 has the outer collector region 12 formed therein, and the outer base region 210 and the second isolation layer 22 are sequentially formed on the surface of the substrate 10, and the opening K is formed in the outer base region 210 and the second isolation layer 22, and the sidewalls on both sides of the opening K are formed with the stacked first isolation layer 23 and the first sidewall 24; the emitter 26 is filled in the emitter 26 window surrounded by the first isolation layer 23 and the first sidewall 24, and the emitter 26 is located on the surface of the substrate 10 of the outer collector region 12.

[0048] In summary, the present application provides a bipolar transistor device and a manufacturing method thereof, which comprises: providing a substrate having an outer collector region formed therein, and a first isolation layer formed on the surface of the outer collector region; sequentially forming an outer base region layer and a second isolation layer on the surface of the substrate, and forming an opening in the outer base region layer and the second isolation layer to expose the first isolation layer; forming a first sidewall on the sidewall of the opening; forming a second sidewall covering the sidewall of the lower part of the first sidewall; wet etching the first isolation layer to expose the substrate; and forming an emitter. In the present application, the second sidewall is formed after the first sidewall is formed and before the wet etching, and the second sidewall serves as a barrier layer during the wet etching process, and the second sidewall is consumed during the wet etching process, thereby protecting the first isolation layer below the second sidewall and avoiding the first isolation layer from being undercut during the wet etching process. The sidewall of the first isolation layer is regular, which is beneficial to the subsequent filling of the emitter.

[0049] The various embodiments described in this specification are presented for the purpose of illustration and description. Each of the embodiments described in this specification is presented in a progressive manner, with each embodiment highlighting differences from other embodiments. The same or similar parts and / or methods are cross-referenced between embodiments. For the methods disclosed in the embodiments, the description is relatively simple because the methods correspond to the devices disclosed in the embodiments, and the relevant parts are cross-referenced to the description of the methods.

[0050] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application, using the methods and technical contents disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, shall fall within the protection scope of the present application.

Claims

1. A method of fabricating a bipolar transistor device, characterized by, The application relates to a method for manufacturing a vertical power transistor, and the method comprises the following steps: a substrate is provided, an outer collector region is formed in the substrate, a first isolation layer is formed on the substrate surface of the outer collector region; a substrate surface is further formed with an outer base region layer and a second isolation layer in sequence, an opening is formed in the outer base region layer and the second isolation layer, and the opening exposes the first isolation layer; a first side wall is formed on the side wall of the opening; a second side wall is formed, the second side wall covers the side wall of the lower part of the first side wall, and the bottom of the second side wall is located on the first isolation layer; the second side wall is formed, and the forming process specifically comprises the following steps: a side wall material layer is formed, the side wall material layer at least covers the side wall of the first side wall and the exposed first isolation layer; dry etching is performed on the side wall material layer to expose part of the first isolation layer, and the remaining side wall material layer is etched to form the second side wall; wet etching is performed on the first isolation layer to expose the substrate; the second side wall is sacrificed during the wet etching process, the first isolation layer under the second side wall is protected, and side etching of the first isolation layer during the wet etching process is avoided; an emitter is formed, the emitter fills the emitter window formed by the first side wall and the first isolation layer after the wet etching.

2. The method of fabricating a bipolar transistor device of claim 1, wherein, The process for forming the second side wall by dry etching the side wall material layer comprises the following steps: the etching gas is a mixed gas of a multi-fluorine fluorine-based gas, a chlorine-based gas and an auxiliary gas.

3. The method of fabricating a bipolar transistor device of claim 2, wherein, The multi-fluorine fluorine-based gas is a combination of one or more of SiF4, NF3, SF6, CF4, CF3I, CHF3, CH3F, CH2F2, C2F6, C2F6, C3F8 and C4F8.

4. The method of fabricating a bipolar transistor device of claim 1, wherein, The side wall of the first isolation layer exposed after the wet etching is perpendicular to the substrate surface.

5. The method of fabricating a bipolar transistor device of claim 1, wherein, The material of the outer base region layer and the emitter is polysilicon.

6. The method of fabricating a bipolar transistor device of claim 1, wherein, The material of the first isolation layer comprises silicon oxide or silicon oxynitride.

7. The method of fabricating a bipolar transistor device of claim 1, wherein, Collector lead-out regions are formed in the substrate on both sides of the outer collector region, and an isolation region is formed in the substrate between the outer collector region and the collector lead-out regions.

8. The method of fabricating a bipolar transistor device of claim 7, wherein, After the emitter is formed, the following steps are further included: the second isolation layer and the outer base region layer are etched to form an outer base region, the outer base region covers part of the outer collector region and part of the isolation region and exposes the collector lead-out regions.

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