A semiconductor performance test method and system

Abstract

This invention relates to a semiconductor performance testing method and system, belonging to the field of semiconductor technology, and solves the problem that defects in disordered dielectric layers and interface defects can affect the transport performance of charge carriers in the active layer of a semiconductor. The method includes: fabricating a field-effect transistor (FET), the FET including an air insulating layer between the semiconductor layer to be tested and the gate; measuring the drain current corresponding to the gate voltage as the gate voltage continuously varies within a test voltage range, and plotting a transfer characteristic curve based on the gate voltage value and the corresponding drain current value within the test voltage range; the drain of the FET is connected to a positive power supply voltage, the source is grounded, and the gate is connected to the gate voltage varying within the test voltage range; and obtaining the intrinsic transport performance of the semiconductor layer to be tested based on the transfer characteristic curve. The device structure, which eliminates the influence of insulating layer defects through an air (vacuum) insulating layer, reflects the true intrinsic transport performance of the semiconductor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor performance testing method and system. Background Technology

[0002] Mobility, as an important indicator of semiconductor transport performance, is defined as the drift velocity of electrons under a unit electric field and is a crucial charge transport parameter. There are many techniques for characterizing mobility, such as the time-of-flight method, the space charge-confined current method, and the field-effect transistor (FET) method. The FET method is widely used as a method for fabricating semiconductor materials for FETs. It is generally fabricated as a three-terminal device (gate, source, drain). Under the induction of the gate voltage, charge carriers are injected through the grounded source electrode, forming a drift current under the influence of the source-drain voltage, and the charge carriers are received by the drain.

[0003] For amorphous semiconductors, the energy state density exhibits a Gaussian or exponential distribution, with band edges having a certain slope, i.e., band tail states. The so-called band tail effect refers to the fact that the edges of the conduction band and valence band in a semiconductor are not abrupt. However, in actual semiconductors, due to the formation of defects, doping, etc., the ideal lattice periodicity is disrupted, forming some localized states. In terms of energy state density distribution, this is equivalent to a continuous energy state distribution in the band gap region near the bottom of the conduction band or the top of the valence band, which is essentially a tail in the band gap, i.e., a band tail. Carriers in the band tail state are not good extended states, thus often leading to the degradation of semiconductor electrical properties. When the semiconductor band tail state is small, i.e., the slope is large, carriers can jump into the energy band for transport, resulting in high mobility; when the band tail state is large, the Fermi level is located in the band tail state, and the device mobility is significantly reduced due to the influence of localized carriers in the band tail state. The vertical structure of a commonly used field-effect transistor includes a metal gate, a dielectric layer (insulating layer), and a semiconductor active layer. The presence of numerous defects in the disordered dielectric layer leads to increased band tail states in the semiconductor, impacting carrier transport in the active layer. Furthermore, interface defects between the dielectric and semiconductor layers introduce further disorder, degrading transport performance. Therefore, FET characterization methods are affected by the dielectric layer, making it difficult to accurately reflect the intrinsic transport characteristics of the semiconductor layer. However, studying the intrinsic transport performance of the semiconductor layer is crucial for improving field-effect semiconductor devices.

[0004] By improving the lattice matching between the insulating layer and the semiconductor layer, better interface performance can be obtained. However, for materials such as amorphous oxides and organic semiconductors, there is no insulating layer material that is perfectly matched to them. Therefore, for field-effect transistors made of amorphous oxides and organic semiconductors, eliminating the influence of interface defects between the dielectric layer and the semiconductor layer is a technical problem that urgently needs to be solved in the study of intrinsic semiconductor transport performance. Summary of the Invention

[0005] Based on the above analysis, the embodiments of the present invention aim to provide a semiconductor performance testing method and system to solve the problem that defects existing in the existing disordered dielectric layer and interface defects between the dielectric layer and the semiconductor layer can affect the transport performance of charge carriers in the active layer of the semiconductor.

[0006] On one hand, embodiments of the present invention provide a semiconductor performance testing method, comprising: fabricating a field-effect transistor, wherein the field-effect transistor includes an air insulating layer located between a semiconductor layer to be tested and a gate; measuring a drain current corresponding to the gate voltage as the gate voltage continuously varies within a test voltage range, and plotting a transfer characteristic curve based on the gate voltage value and the corresponding drain current value within the test voltage range, wherein the drain of the field-effect transistor is connected to a positive power supply voltage, the source is grounded, and the gate is connected to a gate voltage varying within the test voltage range; and obtaining the intrinsic transport performance of the semiconductor layer to be tested based on the transfer characteristic curve.

[0007] The beneficial effects of the above technical solution are as follows: The embodiments of the present invention utilize an air (vacuum) insulating layer to eliminate the influence of insulating layer defects, thus reflecting the intrinsic transport properties of the true semiconductor. This device structure is simple to fabricate and therefore can be widely applied in physical research involving various amorphous semiconductor devices.

[0008] Based on further improvements to the above method, the semiconductor layer to be tested includes indium gallium zinc oxide, amorphous silicon, low-temperature polycrystalline silicon, and disordered organic thin films.

[0009] Based on a further improvement of the above method, the fabrication of a field-effect transistor further includes: forming the semiconductor layer to be tested, a source, and a drain over a substrate, wherein the top surface of the semiconductor layer to be tested between the source and the drain is exposed; forming a sidewall layer over the substrate outside the source and the drain, wherein the height of the sidewall layer is greater than the height of the semiconductor layer, the source, and the drain; and forming a gate over the sidewall layer to form the air insulating layer between the bottom surface of the gate and the top surfaces of the source, the drain, and the exposed top surface of the semiconductor layer to be tested.

[0010] Further improvements to the above method include forming the semiconductor layer to be tested, the source electrode, and the drain electrode above the substrate, which further comprises: depositing the semiconductor material to be tested on the substrate by magnetron sputtering; patterning the semiconductor material to be tested to form the semiconductor layer to be tested by ultraviolet lithography and wet etching processes; depositing an electrode material layer on the substrate and the semiconductor layer by photoresist coating and electron beam processes; and patterning the electrode material layer to form the source electrode and the drain electrode.

[0011] Based on a further improvement of the above method, the source electrode includes a source electrode body, a source electrode extension, and a source electrode contact, wherein the source electrode body is located above the semiconductor layer to be tested, the source electrode extension extends perpendicularly outward from the middle of the source electrode body and is located above the substrate, and the source electrode contact is located at the end of the source electrode extension away from the source electrode body; and the drain electrode includes a drain electrode body, a drain electrode extension, and a drain electrode contact, wherein the drain electrode body is located above the semiconductor layer to be tested, the drain electrode extension extends perpendicularly outward from the middle of the drain electrode body and is located above the substrate, and the drain electrode contact is located at the end of the drain electrode extension away from the drain electrode body.

[0012] The beneficial effects of the above technical solution are as follows: the source includes a source body, a source extension and a source contact, and the drain includes a drain body, a drain extension and a drain contact, so as to facilitate the application of power to the source contact and the drain contact and facilitate the testing of the semiconductor layer.

[0013] Based on a further improvement of the above method, the sidewall layer includes a first sidewall layer, a second sidewall layer, and a third sidewall layer, wherein the first sidewall layer has an annular cross-section and surrounds the semiconductor layer to be tested in 360°; the second sidewall layer includes multiple rectangular cross-sections and is located on one side of the first sidewall layer, wherein the source extension is sandwiched between any two of the multiple rectangular cross-sections; and the third sidewall layer includes multiple rectangular cross-sections and is located on the other side of the first sidewall layer, wherein the drain extension is sandwiched between any two of the multiple rectangular cross-sections.

[0014] The beneficial effects of the above technical solution are as follows: the first sidewall layer can completely surround the semiconductor layer, and the first sidewall layer and the second and third sidewall layers located on opposite sides of the first sidewall layer can effectively support the gate, so as to generate a uniform and stable air insulating layer between the semiconductor layer to be tested and the gate.

[0015] A further improvement to the above method, forming a gate above the sidewall layer further includes: cutting a heavily doped silicon wafer and overlapping the cut heavily doped silicon wafer above the sidewall layer as the gate, wherein the gate covers the entire semiconductor layer to be tested, the sidewall layer, the source body, the source extension, the drain body, and the drain extension.

[0016] Further improvements to the above method, obtaining the intrinsic transport properties of the semiconductor layer under test based on the transfer characteristic curve further include: obtaining the fitting slope of the linear region based on the transfer characteristic curve; and obtaining the intrinsic mobility of the semiconductor layer based on the fitting slope of the linear region.

[0017] The beneficial effects of the above technical solution are as follows: the semiconductor performance testing method can greatly reduce the influence of dielectric layer disorder on semiconductor mobility and obtain the intrinsic mobility of semiconductor.

[0018] A further improvement to the above method includes, before measuring the drain current corresponding to the gate voltage, the following steps: fixing the field-effect transistor on a sealed test stage; selectively evacuating the sealed test stage to a vacuum using a vacuum pump; adjusting the temperature of the test stage to 300K to obtain the room-temperature transfer characteristic curve of the semiconductor layer under test based on the measurement results; and adjusting the temperature of the test stage to a temperature different from 300K to obtain the temperature-varying transfer characteristic curve of the semiconductor layer under test based on the measurement results.

[0019] On the other hand, embodiments of the present invention provide a semiconductor performance testing system, including a field-effect transistor and a semiconductor tester, wherein the field-effect transistor is placed in the test chamber of the semiconductor tester, and then the semiconductor layer to be tested in the field-effect transistor is tested using the semiconductor performance testing method according to the above embodiments.

[0020] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0021] 1. This invention provides a vacuum insulating layer device structure that eliminates the influence of insulating layer defects through an air insulating layer, reflecting the true intrinsic transport properties of semiconductors. This device structure is simple to fabricate and therefore can be widely applied in physical research involving various amorphous semiconductor devices.

[0022] 2. The source includes a source body, a source extension, and a source contact, and the drain includes a drain body, a drain extension, and a drain contact, so as to facilitate the application of power to the source and drain contacts and to facilitate the testing of the semiconductor layer.

[0023] 3. The first sidewall layer can completely surround the semiconductor layer, and the second and third sidewall layers located on opposite sides of the first sidewall layer can effectively support the gate, so as to generate a uniform and stable air insulating layer between the semiconductor layer to be tested and the gate.

[0024] 4. The semiconductor layer performance parameters obtained in the embodiments of the present invention can provide theoretical guidance for analyzing the microscopic physical mechanism of semiconductors in field-effect transistors, and can be directly used to analyze the carrier transport characteristics of semiconductor materials, thereby providing guidance for manufacturing high-performance semiconductor devices.

[0025] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0026] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0027] Figure 1 A flowchart of a semiconductor performance testing method according to an embodiment of the present invention.

[0028] Figure 2 A schematic diagram of a field-effect transistor with a vacuum insulating layer according to an embodiment of the present invention is shown.

[0029] Figure 3 This is a top cross-sectional view of a field-effect transistor other than the gate, according to an embodiment of the present invention.

[0030] Figure 4 for Figure 3 A magnified view of the channel of a field-effect transistor.

[0031] Figure 5 The transfer curves and linear region fitting results of the IGZO material obtained through experiments at 300K are shown.

[0032] Figure 6 The transfer curves of the IGZO material obtained through experiments at different temperatures are shown.

[0033] Figure 7 A schematic diagram showing a comparison of the activation energy and density of states of a field-effect transistor with a vacuum insulating layer and a field-effect transistor with a silicon oxide dielectric layer under the same conditions is shown. Detailed Implementation

[0034] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0035] One specific embodiment of the present invention discloses a method for testing semiconductor performance. (See reference...) Figure 1 The semiconductor performance testing method includes: in step S102, fabricating a field-effect transistor, wherein the field-effect transistor includes an air insulating layer located between the semiconductor layer to be tested and the gate; in step S104, as the gate voltage continuously varies within a test voltage range, measuring the drain current corresponding to the gate voltage, and plotting a transfer characteristic curve based on the gate voltage value and the corresponding drain current value within the test voltage range, wherein the drain of the field-effect transistor is connected to the positive power supply voltage, the source is grounded, and the gate is connected to the gate voltage varying within the test voltage range; and in step S106, obtaining the intrinsic transport performance of the semiconductor layer to be tested based on the transfer characteristic curve.

[0036] Compared with existing technologies, the semiconductor performance testing method provided in this embodiment utilizes a vacuum insulating layer device structure that eliminates the influence of insulating layer defects through an air insulating layer, thus reflecting the true intrinsic transport properties of the semiconductor. This device structure is simple to fabricate and therefore can be widely applied in physical research involving various amorphous semiconductor devices.

[0037] The following text will refer to Figures 1 to 7 The steps S102, S104 and S106 of the semiconductor performance testing method according to embodiments of the present invention will be described in detail.

[0038] refer to Figure 1 In step S102, a field-effect transistor is fabricated, wherein the field-effect transistor includes an air insulating layer 17 located between the semiconductor layer 14 to be tested and the gate 16. Hereinafter, reference is made to... Figures 2 to 4 The steps for fabricating field-effect transistors are described in detail.

[0039] refer to Figure 2 Fabricating a field-effect transistor includes: forming a semiconductor layer 14 to be tested, a source 12, and a drain 13 over a substrate 11, wherein the top surface of the semiconductor layer 14 to be tested, between the source 12 and the drain 13, is exposed. A sidewall layer 15 is formed over the substrate 11, excluding the source 12 and the drain 13, wherein the height of the sidewall layer 15 is greater than the height of the semiconductor layer 14, the source 12, and the drain 13. A gate 16 is formed over the sidewall layer 15 to form an air insulating layer 17 between the bottom surface of the gate and the top surfaces of the source 12, the drain 13, and the exposed top surface of the semiconductor layer 14 to be tested.

[0040] Specifically, forming the semiconductor layer 14, source 12, and drain 13 to be tested above the substrate 11 further includes: depositing the semiconductor material to be tested on the substrate by magnetron sputtering; patterning the semiconductor material to be tested to form the semiconductor layer 14 by ultraviolet lithography and wet etching processes; depositing an electrode material layer on the substrate and the semiconductor layer by photoresist coating and electron beam processes; and patterning the electrode material layer to form the source 12 and drain 13. Specifically, refer to... Figure 3 and Figure 4 The source electrode 12 includes a source body 121, a source extension 122, and a source contact 123. The source body 121 is located above the semiconductor layer 14 to be tested. The source extension 122 extends perpendicularly outward from the middle of the source body 121 and is located above the substrate. The source contact 123 is located at the end of the source extension 122 away from the source body 121. The drain electrode 13 includes a drain body 131, a drain extension 132, and a drain contact 132. The drain body 131 is located above the semiconductor layer 14 to be tested. The drain extension 132 extends perpendicularly outward from the middle of the drain body 131 and is located above the substrate. The drain contact 133 is located at the end of the drain extension 132 away from the drain body 131.

[0041] refer to Figure 3 The sidewall layer 15 includes a first sidewall layer 151, a second sidewall layer 152, and a third sidewall layer 153. The first sidewall layer 151 has an annular cross-section and surrounds the semiconductor layer 14 to be tested in 360°. The second sidewall layer 152 includes a plurality of rectangular cross-sections and is located on one side of the first sidewall layer 151, wherein a source extension 122 is sandwiched between any two of the plurality of rectangular cross-sections, such that a source contact 123 extends from any two of the rectangular cross-sections of the second sidewall layer 152. The third sidewall layer 153 includes a plurality of rectangular cross-sections and is located on the other side of the first sidewall layer 151, wherein a drain extension 132 is sandwiched between any two of the plurality of rectangular cross-sections, such that a drain contact 133 extends from any two of the rectangular cross-sections of the third sidewall layer 153.

[0042] refer to Figure 2 and Figure 3 The formation of the gate 16 above the sidewall layer 15 further includes: cutting a heavily doped silicon wafer and overlapping the cut heavily doped silicon wafer above the sidewall layer 15 as the gate 16, wherein the gate covers the entire semiconductor layer 14 to be tested, the sidewall layer 15, the source body 121, the source extension 122, the drain body 131 and the drain extension 132.

[0043] In step S104, as the gate voltage continuously varies within the test voltage range, the drain current corresponding to the gate voltage is measured, and a transfer characteristic curve is plotted based on the gate voltage value and the corresponding drain current value within the test voltage range. The drain of the field-effect transistor is connected to the positive power supply voltage, the source is grounded, and the gate is connected to the gate voltage varying within the test voltage range. Specifically, before measuring the drain current corresponding to the gate voltage, the process further includes: fixing the field-effect transistor on a sealed test stage; selectively evacuating the sealed test stage to a vacuum using a vacuum pump, for example, a mechanical pump or a molecular pump. In an optional embodiment, the field-effect transistor is selectively placed in a nitrogen environment. Specifically, nitrogen is supplied to the sealed test stage to place the field-effect transistor in a nitrogen environment, except that the dielectric constant changes accordingly; the temperature of the test stage is adjusted to 300K to obtain the room-temperature transfer characteristic curve of the semiconductor layer under test based on the measurement results (reference). Figure 5 ); and adjusting the temperature of the test stage to a temperature different from 300K to obtain the temperature-varying transfer characteristic curve of the semiconductor layer under test based on the measurement results (refer to...). Figure 6 The field-effect transistor is placed in a vacuum environment so that the semiconductor layer under test does not come into contact with the insulating material and gas molecules, thus completely eliminating the influence of defects in the insulating material and its interface on the semiconductor layer under test.

[0044] In step S106, the intrinsic transport properties of the semiconductor layer under test are obtained based on the transfer characteristic curve. The applicable range of the semiconductor layer under test includes various amorphous semiconductor systems, such as indium gallium zinc oxide, amorphous silicon, low-temperature polycrystalline silicon, and disordered organic thin films. Obtaining the intrinsic transport properties of the semiconductor layer under test based on the transfer characteristic curve further includes: obtaining the fitting slope of the linear region based on the transfer characteristic curve; and obtaining the intrinsic mobility of the semiconductor layer based on the fitting slope of the linear region.

[0045] In the following text, refer to Figures 2 to 7 The semiconductor performance testing method according to embodiments of the present invention will be described in detail with specific examples.

[0046] The purpose of this invention is to eliminate the influence of defects in the dielectric layer and interface on the semiconductor layer, and to test the intrinsic transport properties of the semiconductor layer itself. This objective is achieved through the following technical solutions.

[0047] Step 1: Fabrication of structural devices with suspended insulating layers

[0048] The device structure invented by this method is as follows: Figure 2As shown. After patterning the semiconductor layer 1), source 12, and drain 13 on the substrate 11, a sidewall layer 15 supporting the vacuum gate dielectric (air insulating layer or nitrogen insulating layer) is fabricated in the area outside the existing patterned area using photoresist coating. The height of the sidewall layer is higher than the semiconductor layer and the source and drain terminals, and it surrounds the semiconductor layer 360° to ensure the stability of the device structure. The top cross-sectional view is shown below. Figure 2 As shown. A heavily doped silicon wafer or a heavily doped silicon wafer with a gold film deposited on it is used as the top gate 16, and an air (vacuum) layer 17 is formed between the semiconductor layer 14 and the top gate 16.

[0049] Step 2: Test the electrical characteristics of the device

[0050] During testing, a vacuum cryogenic probe station is typically used. The test chamber is evacuated to a vacuum using a mechanical or molecular pump (during testing, the device is fixed in a cryogenic vacuum test bench, which is sealed and evacuated; this is not an innovative property of the device itself. Air or nitrogen environments are also acceptable, although the dielectric constant will change accordingly). This ensures that the space between the semiconductor layer and the gate is a vacuum dielectric layer, the height of which is the height difference between the sidewall layer and the semiconductor layer. The electrical characteristics (transfer characteristics I) of the device are measured using a Keithley 4200 (SCS semiconductor parameter analyzer). ds -V g ).

[0051] Step 3: Extract the intrinsic mobility of the amorphous semiconductor.

[0052] Based on step two, the transfer curve of the device at room temperature (300K) in a vacuum environment was obtained (reference). Figure 5 According to formula (1), the intrinsic transport mobility μ of the reactive semiconductor layer, excluding the influence of dielectric disorder, can be calculated.

[0053]

[0054] In the formula, Slope is the transition curve (I ds -V g The slope of the fitted region in the linear region (e.g.) Figure 5 W / L is the transistor channel width-to-length ratio, V ds Source-drain voltage; C i The capacitance per unit area of ​​the dielectric layer is calculated using formula (2).

[0055]

[0056] In the formula, ε0 is the vacuum permittivity, h2 is the height of the sidewall layer, and h1 is the height of the semiconductor layer (if tested in air or nitrogen, formula (2) needs to be multiplied by the relative permittivity of air or nitrogen).

[0057] Furthermore, the transfer curves at different temperature points were tested (refer to...). Figure 6 This can provide more information about the intrinsic transport of the reactive semiconductor layer. (See reference...) Figure 7 , such as activation energy E a And the density of states (DOS) and other parameters (used to study the intrinsic reliability of devices after excluding the influence of the dielectric layer). The field-effect conductance σ of the device can be calculated according to formula (3).

[0058]

[0059] By fitting the curves of conductivity, gate voltage, and temperature in formula (3) using formula (4), the activation energy E corresponding to different gate voltages can be obtained. a

[0060]

[0061] Where A is the fitting constant, k is the Boltzmann constant, and T is the temperature. According to formula (5), the density of states N(E) of this system can be obtained.

[0062]

[0063] In the formula, e is the elementary charge and a is the thickness of the accumulated layer of the semiconductor layer.

[0064] Beneficial effects

[0065] As can be seen from the above technical solution, the present invention has the following beneficial effects:

[0066] 1. In this invention, the influence of defects in the dielectric layer and its interface on the semiconductor layer is eliminated, and the intrinsic transport properties of the semiconductor layer can be obtained.

[0067] 2. The obtained semiconductor layer performance parameters can provide theoretical guidance for analyzing the microscopic physical mechanism of semiconductors in field-effect transistors, and can be directly used to analyze the carrier transport characteristics of semiconductor materials, thereby providing guidance for manufacturing high-performance semiconductor devices.

[0068] Example

[0069] The present invention is further illustrated by using a field-effect transistor with IGZO (Indium gallium zinc oxide) as the semiconductor layer as an example.

[0070] A 300nm thick SiO2 wafer was used as the substrate. An IGZO layer with a thickness of 100nm was deposited on the substrate using magnetron sputtering. After patterning the IGZO using UV lithography and wet etching, the source and drain terminals were deposited using photoresist coating and electron beam evaporation. The material was Ti / Au (direct electron beam evaporation deposition, where the work function of Ti / Au is well-matched to IGZO). The channel aspect ratio of the semiconductor was 1000 / 20 (e.g., ...). Figure 4 (As indicated by the label). In an optional embodiment, the channel width-to-length ratio of the semiconductor can be set as needed. A sidewall layer with a thickness of 1100 nm is fabricated around the pre-formed patterned area using a photoresist coating process. Heavily doped silicon wafers are cut into 1cm × 3cm pieces and overlapped on the sidewall layer, covering all IGZO regions to form an air (vacuum) layer.

[0071] The test was conducted inside the cavity of a vacuum semiconductor tester at a temperature of 300K. For the test transfer output curve, please refer to [link / reference needed]. Figure 5 The slope is estimated to be 1.72 × 10⁻⁵ A / V. According to formulas (1) and (2), its mobility is 77.7 cm. 2 / (V·s). In comparison, under the same conditions, the mobility of an IGZO device with a silicon oxide insulating layer is only 8.9 cm⁻¹. 2 / (V·s), it can be seen that this method can greatly reduce the influence of dielectric layer disorder on semiconductor mobility and obtain the intrinsic mobility of semiconductor.

[0072] By varying the test temperature under different vacuum test conditions, the temperature transition curve of the device can be obtained, such as... Figure 6 As shown. Based on formulas (3), (4), and (5), the experimental data are fitted. The activation energy E of the device can then be calculated. a And the density of states (DOS), compared with the activation energy and density of states of the silicon oxide insulating layer, such as Figure 7 As shown, the field-effect transistor with a vacuum insulating layer has a very small band tail state and is less affected by the energy disorder modulation of the insulating layer and interface, which to some extent directly explains the reason for the high vacuum gate mobility.

[0073] Another specific embodiment of the present invention discloses a semiconductor performance testing system, including a field-effect transistor (FET) and a semiconductor tester. The FET is placed inside the test chamber of the semiconductor tester, and then the semiconductor layer to be tested in the FET is tested using the semiconductor performance testing method described in the above embodiment.

[0074] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0075] 1. This invention provides a vacuum insulating layer device structure that eliminates the influence of insulating layer defects through an air insulating layer, reflecting the true intrinsic transport properties of semiconductors. This device structure is simple to fabricate and therefore can be widely applied in physical research involving various amorphous semiconductor devices.

[0076] 2. The source includes a source body, a source extension, and a source contact, and the drain includes a drain body, a drain extension, and a drain contact, so as to facilitate the application of power to the source and drain contacts and to facilitate the testing of the semiconductor layer.

[0077] 3. The first sidewall layer can completely surround the semiconductor layer, and the second and third sidewall layers located on opposite sides of the first sidewall layer can effectively support the gate, so as to generate an air insulating layer between the semiconductor layer to be tested and the gate.

[0078] 4. The semiconductor layer performance parameters obtained in the embodiments of the present invention can provide theoretical guidance for analyzing the microscopic physical mechanism of semiconductors in field-effect transistors, and can be directly used to analyze the carrier transport characteristics of semiconductor materials, thereby providing guidance for manufacturing high-performance semiconductor devices.

[0079] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0080] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor performance testing method, characterized in that, include: Fabricating a field-effect transistor, wherein the field-effect transistor includes an air insulating layer located between a semiconductor layer to be tested and a gate, the semiconductor layer to be tested, a source, and a drain are formed over a substrate, and a sidewall layer is formed over the substrate outside the source and the drain; As the gate voltage continuously varies within the test voltage range, the drain current corresponding to the gate voltage is measured, and a transfer characteristic curve is plotted based on the gate voltage value and the corresponding drain current value within the test voltage range. The drain of the field-effect transistor is connected to the positive power supply voltage, the source is grounded, and the gate is connected to the gate voltage varying within the test voltage range. The intrinsic transport properties of the semiconductor layer under test are obtained based on the transfer characteristic curve. The source includes a source body, a source extension, and a source contact. The drain includes a drain body, a drain extension, and a drain contact. The sidewall layer includes a first sidewall layer, a second sidewall layer, and a third sidewall layer. The source body is located above the semiconductor layer under test. The source extension extends perpendicularly outward from the middle of the source body and is located above the substrate. The source contact is located at the end of the source extension away from the source body. The drain body is located above the semiconductor layer under test. The drain extension extends perpendicularly outward from the middle of the drain body and is located above the substrate. The drain contact is located at the end of the drain extension away from the drain body. The first sidewall layer has an annular cross-section and surrounds the semiconductor layer under test in 360°. The second sidewall layer includes multiple rectangular cross-sections and is located on one side of the first sidewall layer, wherein the source extension is sandwiched between any two of the multiple rectangular cross-sections. The third sidewall layer includes multiple rectangular cross-sections and is located on the other side of the first sidewall layer, wherein the drain extension is sandwiched between any two of the multiple rectangular cross-sections. The gate is supported by the first sidewall layer, the second sidewall layer and the third sidewall layer to generate a uniform and stable air insulating layer between the semiconductor layer under test and the gate.

2. The semiconductor performance testing method according to claim 1, characterized in that, The semiconductor layers to be tested include indium gallium zinc oxide, amorphous silicon, low-temperature polycrystalline silicon, and disordered organic thin films.

3. The semiconductor performance testing method according to claim 2, characterized in that, Further fabrication of field-effect transistors include: The top surface of the semiconductor layer to be tested is located between the source and the drain. Wherein, the height of the sidewall layer is greater than the height of the semiconductor layer, the source electrode, and the drain electrode; and A gate is formed above the sidewall layer to form the air insulating layer between the bottom surface of the gate and the top surface of the source, the drain, and the exposed top surface of the semiconductor layer to be tested.

4. The semiconductor performance testing method according to claim 3, characterized in that, Forming the semiconductor layer to be tested, the source, and the drain over the substrate further includes: The semiconductor material to be tested is deposited on the substrate by magnetron sputtering. The semiconductor material to be tested is patterned using ultraviolet lithography and wet etching processes to form the semiconductor layer to be tested; Electrode material layers are deposited over the substrate and the semiconductor layer using photoresist coating and electron beam processes; and The electrode material layer is patterned to form the source and the drain.

5. The semiconductor performance testing method according to claim 3, characterized in that, Forming a gate above the sidewall layer further includes: A heavily doped silicon wafer is cut and the cut heavily doped silicon wafer is overlapped on the sidewall layer as the gate, wherein the gate covers the entire semiconductor layer to be tested, the sidewall layer, the source body, the source extension, the drain body, and the drain extension.

6. The semiconductor performance testing method according to claim 2, characterized in that, Obtaining the intrinsic transport properties of the semiconductor layer under test based on the transfer characteristic curve further includes: The slope of the linear region is obtained from the transfer characteristic curve; and The intrinsic mobility of the semiconductor layer is obtained based on the fitting slope of the linear region.

7. The semiconductor performance testing method according to claim 1, characterized in that, The process further includes, before measuring the drain current corresponding to the gate voltage: The field-effect transistor is fixed on a sealed test stage; The sealed test bench is selectively evacuated using a vacuum pump; The temperature of the test stage is adjusted to 300K to obtain the room-temperature transfer characteristic curve of the semiconductor layer under test based on the measurement results; and The temperature of the test stage is adjusted to a temperature different from 300K to obtain the temperature transfer characteristic curve of the semiconductor layer under test based on the measurement results.

8. A semiconductor performance testing system, characterized in that, Including field-effect transistors and semiconductor testers, among which, The field-effect transistor is placed in the test chamber of the semiconductor tester, and then the semiconductor layer to be tested in the field-effect transistor is tested using the semiconductor performance testing method according to any one of claims 1 to 7.

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