Array substrate and manufacturing method thereof, and display panel

Abstract

The present invention discloses an array substrate, a method for manufacturing the same, and a display panel. The array substrate comprises: a substrate; a pixel driving circuit formed on the substrate; the pixel driving circuit includes a capacitor; the capacitor comprises: a first capacitor plate disposed on the substrate; a second capacitor plate disposed on a side of the first capacitor plate away from the substrate; along the thickness direction of the array substrate, the second capacitor plate is at least partially opposed to the first capacitor plate; the array substrate further comprises an interlayer insulating layer disposed between the first capacitor plate and the second capacitor plate, the interlayer insulating layer having at least two grooves formed in portions corresponding to the capacitor. The present invention can improve the phenomenon of uneven display.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the development of display technology, the application of display panels is becoming more and more extensive, and the corresponding requirements for display panels are also becoming higher and higher.

[0003] However, existing display panels are prone to uneven display during display, which seriously affects the display effect. Summary of the Invention

[0004] The present invention provides an array substrate and a preparation method thereof, and a display panel, so as to solve the problem of uneven display of the display panel.

[0005] According to one aspect of the present invention, an array substrate is provided, comprising:

[0006] A substrate; a pixel driving circuit is formed on the substrate, the pixel driving circuit includes a capacitor, and the capacitor includes:

[0007] A first capacitor plate is provided on the substrate;

[0008] a second capacitor plate, disposed on a side of the first capacitor plate away from the substrate; along the thickness direction of the array substrate, the second capacitor plate is at least partially opposite to the first capacitor plate;

[0009] The array substrate further includes an interlayer insulating layer disposed between the first capacitor plate and the second capacitor plate. At least two grooves are formed on a portion of the interlayer insulating layer corresponding to the capacitor.

[0010] Optionally, the interlayer insulating layer is an inorganic layer, an organic layer, or a stacked structure of an organic layer and an inorganic layer.

[0011] Optionally, the at least two grooves have the same size.

[0012] Optionally, the array substrate further includes a through hole penetrating the interlayer insulating layer;

[0013] The size of the groove is the same as that of the through hole.

[0014] Optionally, the at least two grooves are arranged in an array.

[0015] Optionally, the first capacitor plate is a planar structure parallel to the substrate, and the second capacitor plate is a bent structure extending along inner walls of the at least two grooves.

[0016] Optionally, the pixel driving circuit further includes a thin film transistor,

[0017] The first capacitor plate is arranged in the same layer as the gate electrode of the thin film transistor, and the second capacitor plate is arranged in the same layer as the source and drain electrode of the thin film transistor.

[0018] According to another aspect of the present invention, a display panel is provided, comprising the above-mentioned array substrate.

[0019] According to another aspect of the present invention, a method for preparing an array substrate is provided, for preparing the above-mentioned array substrate, the method for preparing the array substrate comprising:

[0020] forming the first capacitor plate on the substrate;

[0021] forming the interlayer insulating layer covering the first capacitor plate;

[0022] forming at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor;

[0023] The second capacitor plate is formed on the interlayer insulating layer.

[0024] Optionally, the interlayer insulating layer is an inorganic layer, and forming at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor includes:

[0025] half-engraving the inorganic layer to form at least two grooves;

[0026] Alternatively, the interlayer insulating layer is an organic layer, and the forming of at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor includes:

[0027] half-etching the organic layer to form at least two grooves;

[0028] Alternatively, the interlayer insulating layer is a stacked structure of an organic layer and an inorganic layer, and the forming of at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor includes:

[0029] A portion of the film layer in the stacked structure is fully etched, and another portion of the film layer in the stacked structure is retained to form at least two of the grooves, wherein the fully etched film layer is at least one film layer in the stacked structure that is etched starting from the film layer farthest from the substrate toward the direction close to the substrate.

[0030] Optionally, the array substrate further includes a through hole penetrating the interlayer insulating layer;

[0031] The method for preparing the array substrate further includes:

[0032] The size of the through hole is monitored by using a size monitoring device.

[0033] The technical solution of an embodiment of the present invention adopts an array substrate including a substrate; a pixel driving circuit formed on the substrate, the pixel driving circuit including a capacitor, the capacitor including: a first capacitor plate disposed on the substrate; a second capacitor plate disposed on a side of the first capacitor plate away from the substrate; along the thickness direction of the array substrate, the second capacitor plate and the first capacitor plate are at least partially opposite; the array substrate also includes an interlayer insulating layer disposed between the first capacitor plate and the second capacitor plate, and the interlayer insulating layer has at least two grooves formed in the portion corresponding to the capacitor. By providing at least two grooves, each groove is manufactured with high precision, resulting in a smaller difference in capacitance between different pixel driving circuits, thereby improving the problem of uneven display on the display panel.

[0034] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 This is a structural diagram of an array substrate in the prior art;

[0037] Figure 2 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0038] Figure 3 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0039] Figure 4 A top view of a second capacitor plate provided by an embodiment of the present invention;

[0040] Figure 5 A schematic structural diagram of a display device provided by an embodiment of the present invention;

[0041] Figure 6 A flow chart of a method for preparing an array substrate provided in an embodiment of the present invention;

[0042] Figure 7 A schematic diagram of a product structure formed corresponding to the method for preparing an array substrate provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] As mentioned in the background art, existing display panels have the problem of uneven display. After careful research, the inventors found that the cause of this technical problem is: Figure 1 This is a schematic diagram of the structure of an array substrate in the prior art. Figure 1 , the array substrate includes a pixel driving circuit, and the pixel driving circuit includes a thin film transistor 20' and a capacitor 30'. The thin film transistor 20' may specifically include an active layer 201', a gate 202' and a source and drain 203', and the capacitor may specifically include a first capacitor plate 201' and a second capacitor plate 302'. In order to reduce the number of masks and process steps, the first capacitor plate 301' is usually set on the same layer as the gate layer 202', and the second capacitor plate 302' is usually set on the same layer as the source and drain 203'. At the same time, since a smaller distance is required between the two plates of the capacitor to increase the capacitance, it is necessary to etch a groove on the interlayer insulating layer. The existing technology usually etches a large groove, so that the size CD of the groove is larger. During the preparation of the array substrate, the structure to be etched will be monitored and the size will be adjusted using a size monitoring device, and multiple through holes need to be etched in the array substrate, such as Figure 1A through-hole connection is required between the source and drain electrodes 203' and the active layer 201'. Dimension monitoring equipment can only monitor one dimension, and typically monitors the through-hole dimension, making it impossible to monitor the groove dimension. A significant difference between the groove and through-hole dimensions will result in poor groove etching accuracy, leading to differences in the capacitance values of capacitors in the pixel driver circuits of the array substrate, resulting in differences in data voltage writing, and ultimately causing uneven display.

[0046] In view of the above technical problems, the present invention proposes the following solutions:

[0047] Figure 2 A schematic structural diagram of an array substrate provided by an embodiment of the present invention, referring to Figure 2 The array substrate includes: a substrate 101; a pixel driving circuit is formed on the substrate 101, the pixel driving circuit includes a capacitor 30, and the capacitor 30 includes: a first capacitor plate 301, which is arranged on the substrate 101; a second capacitor plate 302, which is arranged on a side of the first capacitor plate 301 away from the substrate 101; along the thickness direction of the array substrate, the second capacitor plate 302 is at least partially opposite to the first capacitor plate 301; the array substrate also includes an interlayer insulating layer 104, the interlayer insulating layer 104 is arranged between the first capacitor plate 301 and the second capacitor plate 302, and at least two grooves 303 are formed on the part of the interlayer insulating layer 104 corresponding to the capacitor 30, and the second capacitor plate 302 covers the side wall and bottom wall of the groove 303.

[0048] Specifically, the substrate 101 can be, for example, any one of the substrates 101 including but not limited to a conductive silicon (Si) substrate, a silicon oxide (Al2O3) substrate (i.e., a sapphire substrate), a silicon carbide (SiC) substrate, and a gallium nitride (GaN) substrate; of course, the substrate 101 can also be a flexible substrate, for example, a flexible substrate composed of polyimide PI. A pixel driving circuit is provided on the substrate 101, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The specific circuit structure of the pixel driving circuit is well known to those skilled in the art and will not be repeated here. The pixel driving circuit includes a thin film transistor 20 and a capacitor 30. A buffer layer 102 can be first provided on the substrate 101, and then an active layer 201 of the transistor 20 can be provided. The array substrate is also provided with a gate insulating layer 103 covering the active layer 201.

[0049] In this embodiment, at least two grooves 303 are provided on the interlayer insulating layer 104. Compared with the prior art in which one large groove is provided, the size CD of each groove 303 is smaller, so the difference between the size of each groove 303 and the size of the through hole in the array substrate is also smaller. When the size monitoring equipment is used to monitor and adjust the size of the through hole, the size of each groove 303 and the corresponding film thickness are monitored and adjusted with high accuracy. The difference between the size and depth of the grooves 303 in different pixel driving circuits is also smaller, so that the capacitance difference of the capacitor 30 in different pixel driving circuits is smaller, and thus the difference in the written voltage is also smaller, thereby achieving the effect of improving display unevenness.

[0050] The technical solution of this embodiment employs an array substrate comprising a substrate; a pixel driving circuit formed on the substrate, the pixel driving circuit including a capacitor, the capacitor comprising: a first capacitor plate disposed on the substrate; a second capacitor plate disposed on a side of the first capacitor plate away from the substrate; the second capacitor plate at least partially opposing the first capacitor plate along the thickness direction of the array substrate; and an interlayer insulating layer disposed between the first capacitor plate and the second capacitor plate, the interlayer insulating layer having at least two grooves formed in portions corresponding to the capacitors. By providing at least two grooves, each groove is manufactured with high precision, minimizing the difference in capacitance between different pixel driving circuits, thereby improving the problem of uneven display on the display panel.

[0051] Optionally, continue to refer to Figure 1 The interlayer insulating layer 104 is a stacked structure of an organic layer and an inorganic layer.

[0052] Specifically, in Figure 1 In the illustrated structure, the interlayer insulating layer 104 may include an inorganic layer 1041 and an organic layer 1042. The inorganic layer 1041 covers the first capacitor plate 301, and the organic layer 1042 covers the inorganic layer 1041. In this embodiment, the organic layer 1042 also serves as a planarization layer. When the interlayer insulating layer 104 has a laminated structure, the groove 303 can be formed by fully etching the organic layer 1042. It should be noted that the full etching described in this embodiment refers to fully etching the organic layer 1042 in the thickness direction of the array substrate, thereby exposing the inorganic layer 1041.

[0053] Alternatively, in other embodiments, Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of another array substrate provided in an embodiment of the present invention. In this embodiment, the interlayer insulating layer 104 is a single-layer structure, and in this case, the interlayer insulating layer 104 is an organic layer or an inorganic layer. Furthermore, when etching to form the groove 303, the interlayer insulating layer 104 is half-etched, where half-etching means that the interlayer insulating layer is half-etched in the thickness direction of the array substrate.

[0054] Of course, in some other embodiments, the interlayer insulating layer may also be an interlayer insulating layer including three or more dielectric layers, and the groove 303 may be formed by fully or half-etching at least one dielectric layer, which is not specifically limited in the embodiment of the present invention.

[0055] Optionally, Figure 4 A top view of a second capacitor plate provided by an embodiment of the present invention, combined with Figure 2 and Figure 4 , at least two grooves 303 have the same size.

[0056] Specifically, by setting the size of each groove 303 to be the same, the monitoring accuracy of each groove 303 during manufacturing can be the same, thereby ensuring that the manufacturing accuracy of the capacitor in each pixel driving circuit is consistent, which is more conducive to improving the display unevenness phenomenon.

[0057] Furthermore, in the above embodiment, the array substrate further includes a through hole penetrating the interlayer insulating layer 104 ; the size CD of the groove 303 is the same as the size of the through hole.

[0058] Specifically, during the array substrate manufacturing process, dimension monitoring equipment is used to monitor the dimensions of the through-holes. This results in high manufacturing precision for each through-hole in the array substrate, with minimal dimensional variation between them. By setting the groove 303 to be the same size as the through-holes, the accuracy of the groove 303 dimensions can be precisely controlled during manufacturing, ensuring the same capacitor size across all pixel driver circuits, further improving display unevenness.

[0059] It should be noted that in the above embodiment, the number of grooves 303 should not be too large. If there are too many grooves, the cumulative size and depth errors of the multiple grooves will be large, which will ultimately lead to large differences in capacitance in different pixel driving circuits. Preferably, the number of grooves corresponding to each capacitor is less than or equal to 100.

[0060] Preferably, if Figure 4 As shown, at least two grooves 303 are arranged in an array, which can make the arrangement of the capacitors corresponding to the grooves 303 more uniform, and the capacitance of the capacitors 303 easier to control, which is conducive to reducing the design difficulty of the array substrate.

[0061] Optionally, continue to refer to Figure 2 and Figure 3 In this embodiment, the first capacitor plate 301 is a planar structure parallel to the substrate 101 , and the second capacitor plate 302 is a bent structure extending along the inner walls of the at least two grooves 303 .

[0062] Specifically, in this embodiment, the first capacitor plate 301 has a planar structure, while the second capacitor plate 302 has a bent structure. In other words, there are non-parallel portions between the first capacitor plate 301 and the second capacitor plate 302. This arrangement results in the interlayer insulating layer 104 between the first capacitor plate 301 and the second capacitor plate 302 not being uniformly thin, but rather being thicker in some areas and thinner in others, unlike the uniform parasitic capacitance structure of the interlayer insulating layer in the array substrate. This avoids the problem of the parasitic capacitance film layer structure in the array substrate being consistent with the storage capacitor structure, which would result in excessive parasitic capacitance on the data line in the array substrate, increasing the output requirements for the driver chip and reducing the pixel charging capability.

[0063] Alternatively, as Figure 2 As shown in FIG3 , the pixel driving circuit further includes a thin film transistor 20; a first capacitor plate 301 is provided in the same layer as the gate electrode 202 of the thin film transistor 20, and a second capacitor plate 302 is provided in the same layer as the source and drain electrodes 203 of the thin film transistor 20. In this embodiment, the first capacitor plate 301 can be patterned simultaneously with the gate electrode 202, and the second capacitor plate 302 can be patterned simultaneously with the source and drain electrodes 203. Of course, in other embodiments, the first capacitor plate 301 can also be provided in the same layer as the active layer 201, using the material of the active layer and being heavily doped to form a conductive structure.

[0064] Optionally, continue to refer to Figure 2 The array substrate also includes a power metal layer 105, an anode 106, a light-emitting functional layer 107, a pixel defining layer 108, a support column 109 and a cathode layer (not shown). The functions and materials of the above-mentioned film layers are well known to those skilled in the art and will not be repeated here.

[0065] An embodiment of the present invention further provides a display panel. The display panel includes the array substrate provided by any embodiment of the present invention, and thus has the same beneficial effects, which will not be described in detail here.

[0066] The embodiment of the present invention further provides a display device, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, which includes a display panel provided in an embodiment of the present invention. The display device can be a mobile phone, tablet computer, MP3, MP4, smartwatch, smart helmet, video intercom, or other wearable device. Since it includes the display panel provided in an embodiment of the present invention, it also has the same beneficial effects, and therefore will not be described in detail here.

[0067] The embodiment of the present invention further provides a method for preparing an array substrate. Figure 6 A flowchart of a method for preparing an array substrate provided by an embodiment of the present invention is provided. Figure 7Schematic diagram of the product structure formed by the manufacturing method of the array substrate provided in the embodiment of the present invention, combined with Figure 6 and Figure 7 , the preparation method of the array substrate includes:

[0068] Step S101, forming a first capacitor plate on a substrate;

[0069] Specifically, a buffer layer 102 can be first formed on the substrate 101, and an active layer 201 can be formed on the buffer layer 102; then a gate insulating layer 103 covering the active layer 201 is formed; a metal layer is formed on the gate insulating layer 103, and the metal layer is patterned to form the gate 202 and the first capacitor plate 301.

[0070] Step S102, forming an interlayer insulating layer covering the first capacitor plate;

[0071] Specifically, the interlayer insulating layer can be formed, for example, by growth or the like; the interlayer insulating layer can be an inorganic layer, an organic layer, or a stacked structure of an organic layer and an inorganic layer.

[0072] Step S103, forming at least two grooves in the portion of the interlayer insulating layer corresponding to the capacitor;

[0073] Specifically, when the interlayer insulating layer is a single-layer inorganic layer, the groove can be formed by half-etching the inorganic layer; when the interlayer insulating layer is a single-layer organic layer, the groove can be formed by half-etching the organic layer; when the interlayer insulating layer is a stacked structure of organic and inorganic layers, a portion of the film layer in the stacked structure is fully etched, and another portion of the film layer in the stacked structure is retained to form at least two grooves, wherein the fully etched film layer is at least one film layer in the stacked structure that is etched from the film layer farthest from the substrate toward the substrate. For example, if the organic layer is arranged on the side of the inorganic layer away from the first capacitor plate, the organic layer can be fully etched to form the groove. It should be noted that the above-mentioned half-etching and full-etching both refer to etching the film layer in the thickness direction of the array substrate, half-etching is etching a portion of the film layer in the thickness direction of the array substrate, and full-etching is etching the entire film layer in the thickness direction of the array substrate.

[0074] Step S104, forming a second capacitor plate on the interlayer insulating layer;

[0075] Specifically, the second capacitor plate can be formed simultaneously with the source and drain of the transistor. For example, a metal layer can be formed first, and then the metal layer can be patterned to form the source, drain and the second capacitor plate.

[0076] The technical solution of this embodiment forms at least two grooves, so that each groove is manufactured with high precision, which reduces the difference in capacitance between different pixel driving circuits and improves the problem of uneven display of the display panel.

[0077] Optionally, the array substrate further includes a through hole penetrating the interlayer insulating layer; and the method for preparing the array substrate further includes: monitoring the size of the through hole by using a size monitoring device.

[0078] Specifically, the size monitoring device is, for example, a CD player. During the array substrate manufacturing process, the size monitoring device monitors the size of the through-holes, resulting in high manufacturing precision for each through-hole in the array substrate and minimal dimensional variation between the through-holes. Preferably, the groove 303 is configured to be the same size as the through-hole. This allows for precise control of the size of the groove 303 during manufacturing, ensuring the same size capacitors in each pixel driver circuit, further improving display unevenness.

[0079] It can be understood that the preparation method of the array substrate may also include forming a power metal layer, an anode, a light-emitting functional layer, a pixel defining layer, a support column and a cathode layer. The preparation methods and preparation processes of the above-mentioned film layers are well known to those skilled in the art and will not be repeated here.

[0080] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0081] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate includes: A substrate; a pixel driving circuit is formed on the substrate, the pixel driving circuit includes a capacitor, and the capacitor includes: A first capacitor plate is provided on the substrate; a second capacitor plate, disposed on a side of the first capacitor plate away from the substrate; along the thickness direction of the array substrate, the second capacitor plate is at least partially opposite to the first capacitor plate; The array substrate further includes an interlayer insulating layer disposed between the first capacitor plate and the second capacitor plate, wherein at least two grooves are formed in a portion of the interlayer insulating layer corresponding to the capacitor; The first capacitor plate is a planar structure parallel to the substrate, and the second capacitor plate is a bent structure extending along the inner walls of the at least two grooves.

2. The array substrate according to claim 1, wherein: The interlayer insulating layer is an inorganic layer, an organic layer, or a stacked structure of an organic layer and an inorganic layer.

3. The array substrate according to claim 1, wherein: The at least two grooves have the same size.

4. The array substrate according to claim 3, wherein: The array substrate further includes a through hole penetrating the interlayer insulating layer; The size of the groove is the same as that of the through hole.

5. The array substrate according to claim 1, wherein: The at least two grooves are arranged in an array.

6. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 5.

7. A method for preparing an array substrate, for preparing the array substrate according to any one of claims 1 to 5, characterized in that: The method for preparing the array substrate includes: forming the first capacitor plate on the substrate; forming the interlayer insulating layer covering the first capacitor plate; forming at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor; The second capacitor plate is formed on the interlayer insulating layer.

8. The method for preparing an array substrate according to claim 7, wherein: The interlayer insulating layer is an inorganic layer, and the forming of at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor includes: half-engraving the inorganic layer to form at least two grooves; Alternatively, the interlayer insulating layer is an organic layer, and the forming of at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor includes: half-etching the organic layer to form at least two grooves; Alternatively, the interlayer insulating layer is a stacked structure of an organic layer and an inorganic layer, and the forming of at least two grooves in a portion of the interlayer insulating layer corresponding to the capacitor includes: A portion of the film layer in the stacked structure is fully etched, and another portion of the film layer in the stacked structure is retained to form at least two of the grooves, wherein the fully etched film layer is at least one film layer in the stacked structure that is etched starting from the film layer farthest from the substrate toward the direction close to the substrate.

9. The method for preparing an array substrate according to claim 7, wherein: The array substrate further includes a through hole penetrating the interlayer insulating layer; The method for preparing the array substrate further includes: The size of the through hole is monitored by using a size monitoring device.

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