Solar cells and photovoltaic modules

Abstract

The application discloses a solar cell and a photovoltaic module. The solar cell comprises a silicon substrate, a first electrode and a second electrode. One side of the silicon substrate is provided with a tunneling oxide layer in a direction away from the silicon substrate. The tunneling oxide layer is provided with at least two layers of doped polysilicon layers on a side away from the silicon substrate. A barrier layer is arranged between adjacent doped polysilicon layers. A plurality of first electrodes are electrically connected to different doped polysilicon layers. The application can not only reduce the total thickness of the polysilicon layer, but also reduce parasitic absorption by using a thinner polysilicon layer, thereby improving the short-circuit current. In addition, the barrier layer can block the risk of slurry burning through the tunneling oxide layer, and reduce metal recombination, thereby improving the open-circuit voltage of the solar cell, and further improving the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more specifically, to a solar cell and a photovoltaic module. Background Technology

[0002] TOPCon cells (short for Tunnel Oxide Passivated Contact) are fabricated using tubular LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment. The tunnel oxide layer and the doped polycrystalline silicon layer together form the passivation contact structure. This tunnel oxide passivation contact structure allows majority carriers to pass through the oxide layer while blocking minority carriers, effectively achieving selective carrier passage and thus greatly reducing the recombination rate of minority carriers and improving the cell efficiency.

[0003] TOPCon batteries typically achieve good passivation with a polycrystalline silicon doped layer of around 30nm. However, due to limitations in current slurry and sintering technologies, the polycrystalline silicon doped layer needs to be around 110-120nm to effectively reduce the risk of silver particles burning through and tunneling the oxide layer. Furthermore, since the polycrystalline silicon doped layer itself has strong near-infrared light absorption, a thicker polycrystalline silicon layer can not only lead to a loss of short-circuit current, thus affecting battery performance, but also increase production costs. In summary, the problem of balancing light absorption and metallization in thin-layer polycrystalline silicon cannot be solved.

[0004] Therefore, there is an urgent need to provide a solar cell and photovoltaic module that comprehensively solves the problem of light absorption and metallization balance in thin-layer polycrystalline silicon. Summary of the Invention

[0005] In view of this, the present invention provides a solar cell, comprising a silicon substrate, a first electrode, and a second electrode;

[0006] A tunneling oxide layer is disposed on one side of the silicon substrate in a direction away from the silicon substrate. At least two doped polysilicon layers are disposed on the side of the tunneling oxide layer away from the silicon substrate. A barrier layer is disposed between adjacent doped polysilicon layers. Multiple first electrodes are electrically connected to different doped polysilicon layers.

[0007] Optionally, the phosphorus doping concentration in the doped polycrystalline silicon layer closer to the silicon substrate is lower than the phosphorus doping concentration in the doped polycrystalline silicon layer farther from the silicon substrate.

[0008] Optionally, the at least two doped polysilicon layers include a first doped polysilicon layer, a second doped polysilicon layer, and a third doped polysilicon layer. A first barrier layer is provided between the first doped polysilicon layer and the second doped polysilicon layer, and a second barrier layer is provided between the second doped polysilicon layer and the third doped polysilicon layer. The first doped polysilicon layer is located closer to the tunneling oxide layer, and the third doped polysilicon layer is located away from the tunneling oxide layer.

[0009] The first doped polycrystalline silicon layer is doped with phosphorus, and the second and third doped polycrystalline silicon layers are doped with phosphorus, carbon, or nitrogen, respectively.

[0010] Optionally, the first electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode being electrically connected to the third doped polysilicon layer, and the second sub-electrode being electrically connected to the first doped polysilicon layer and / or the second doped polysilicon layer.

[0011] Optionally, the phosphorus doping concentration in the first doped polysilicon layer is less than the phosphorus doping concentration in the second doped polysilicon layer, and the phosphorus doping concentration in the second doped polysilicon layer is less than the phosphorus doping concentration in the third doped polysilicon layer.

[0012] Optionally, the carbon and nitrogen doping ratios in the second and third doped polysilicon layers are less than 5 wt%.

[0013] Optionally, the phosphorus doping concentration ratio in the first doped polycrystalline silicon layer and the third doped polycrystalline silicon layer is 0.4-1.

[0014] Optionally, along a direction perpendicular to the silicon substrate, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer does not exceed 70 nm.

[0015] Optionally, along a direction perpendicular to the silicon substrate, the thickness of the first doped polysilicon layer, the second doped polysilicon layer, and / or the third doped polysilicon layer ranges from 5 to 40 nm.

[0016] Optionally, the thicknesses of the first barrier layer and the second barrier layer range from 0.5 to 2.5 nm along a direction perpendicular to the silicon substrate.

[0017] Optionally, the silicon substrate includes a base region and an emitter, the emitter being located on the side of the base region away from the tunneling oxide layer, and a passivation layer being disposed on the side of the emitter away from the base region;

[0018] The second electrode penetrates the passivation layer and is electrically connected to the emitter.

[0019] The present invention also provides a photovoltaic module comprising a first encapsulation panel, a first encapsulation film, a battery string, a second encapsulation film, and a second encapsulation panel stacked together, wherein the battery string is formed by electrically connecting multiple solar cells as described above.

[0020] Compared with the prior art, the solar cells and photovoltaic modules provided by the present invention achieve at least the following beneficial effects:

[0021] The present invention provides a solar cell and a photovoltaic module. The solar cell includes a silicon substrate, a first electrode, and a second electrode. A tunneling oxide layer is disposed on one side of the silicon substrate in a direction away from the silicon substrate. At least two doped polycrystalline silicon layers are disposed on the side of the tunneling oxide layer away from the silicon substrate. A barrier layer is disposed between adjacent doped polycrystalline silicon layers. Multiple first electrodes are electrically connected to different doped polycrystalline silicon layers. By adopting the above solution, the overall problem of light absorption and metallization balance in thin-layer polycrystalline silicon is solved. Specifically, it can not only reduce the total thickness of the polycrystalline silicon layer, but also reduce parasitic absorption and thus increase the short-circuit current. Furthermore, the barrier layer prevents the risk of the paste burning through the tunneling oxide layer, while reducing metal recombination, thereby increasing the open-circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0022] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0023] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0025] Figure 1 This is a schematic diagram of a solar cell structure provided by the present invention;

[0026] Figure 2 This is a schematic flowchart of a method for preparing a solar cell provided by the present invention;

[0027] Figure 3 This is a schematic diagram of a photovoltaic module provided by the present invention. Detailed Implementation

[0028] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0029] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0030] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0031] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0032] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0033] Figure 1 This is a schematic diagram of a solar cell structure provided by the present invention; see reference. Figure 1 As shown, this embodiment provides a solar cell including a silicon substrate 1, a first electrode 2 and a second electrode 3; a tunneling oxide layer 4 is disposed on one side of the silicon substrate 1 along the direction away from the silicon substrate 1, and at least two doped polycrystalline silicon layers 5 are disposed on the side of the tunneling oxide layer 4 away from the silicon substrate 1, a barrier layer 6 is disposed between adjacent doped polycrystalline silicon layers 5, and multiple first electrodes 2 are electrically connected to different doped polycrystalline silicon layers 5.

[0034] Specifically, the solar cell can be a TOPCon cell, including a silicon substrate 1, a first electrode 2 and a second electrode 3, wherein the silicon substrate 1 can be an N-type silicon substrate, and the first electrode 2 and the second electrode 3 can both be metals, such as silver, aluminum, copper, nickel, etc.

[0035] A tunneling oxide layer 4 is disposed on one side of the silicon substrate 1 along the direction away from the silicon substrate 1. The tunneling oxide layer 4 allows majority carrier electrons to tunnel into the doped polycrystalline silicon layer 5 while blocking minority carrier hole recombination. Electrons then undergo lateral transport in the doped polycrystalline silicon layer 5 and are collected by the metal, thereby significantly reducing the metal-to-metal recombination current and improving the open-circuit voltage and short-circuit current of the TOPCon cell. Multiple doped polycrystalline silicon layers 5 are disposed on the side of the tunneling oxide layer 4 away from the silicon substrate 1, with a barrier layer 6 disposed between adjacent doped polycrystalline silicon layers 5. The polysilicon layer 5 can be a three-layer doped polysilicon layer 5, a four-layer doped polysilicon layer 5, or a five-layer doped polysilicon layer 5. Preferably, a three-layer doped polysilicon layer 5 is provided on the side of the tunneling oxide layer 4 away from the silicon substrate 1, and a barrier layer 6 is provided between two adjacent doped polysilicon layers 5. The barrier layer 6 is denser than the doped polysilicon layer 5 and can provide a barrier effect. Specifically, the barrier layer 6 can prevent the paste (such as silver particles) from burning through without affecting electron transport. The barrier layer 6 includes, but is not limited to, silicon oxide, silicon oxynitride, and aluminum oxide.

[0036] Multiple first electrodes 2 are electrically connected to different doped polycrystalline silicon layers 5. For example, some first electrodes 2 are burned to the outermost doped polycrystalline silicon layer 5 (the side away from the tunneling oxide layer 4) and then stop; some first electrodes 2 are burned to the innermost doped polycrystalline silicon layer 5 (the side close to the tunneling oxide layer 4) and then stop; some first electrodes 2 are burned to the doped polycrystalline silicon layer 5 between the innermost and outermost layers and then stop. Due to the presence of the barrier layer 6, the risk of burning through the tunneling oxide layer 4 is reduced as much as possible, so as to avoid affecting the open circuit voltage, fill factor and conversion efficiency of the TOPCon cell.

[0037] The silicon substrate 1 includes a base region 11 and an emitter 12. The emitter 12 is located on the side of the base region 11 away from the tunneling oxide layer 4. A passivation layer 7 is disposed on the side of the emitter 12 away from the base region 11. The second electrode 3 penetrates the passivation layer 7 and is electrically connected to the emitter.

[0038] As can be seen from the above embodiments, the solar cell provided in this embodiment achieves at least the following beneficial effects:

[0039] The solar cell provided in this embodiment includes a silicon substrate 1, a first electrode 2, and a second electrode 3. A tunneling oxide layer 4 is disposed on one side of the silicon substrate 1 in a direction away from the silicon substrate 1. At least two layers of doped polycrystalline silicon 5 are disposed on the side of the tunneling oxide layer 4 away from the silicon substrate 1. A barrier layer 6 is disposed between adjacent doped polycrystalline silicon layers 5. Multiple first electrodes 2 are electrically connected to different doped polycrystalline silicon layers 5. By adopting the above scheme, the problem of light absorption and metallization balance of thin polycrystalline silicon is solved as a whole. Specifically, it can not only reduce the total thickness of the polycrystalline silicon layer, but also reduce parasitic absorption and thus increase the short-circuit current. Moreover, the barrier layer 6 can prevent the risk of the paste burning through the tunneling oxide layer 4, while reducing metal recombination, thereby increasing the open-circuit voltage of the solar cell and thus improving the photoelectric conversion efficiency of the solar cell.

[0040] In one embodiment, reference continues... Figure 1 As shown, the phosphorus doping concentration in the polycrystalline silicon layer 5 near the silicon substrate 1 is lower than that in the polycrystalline silicon layer 5 far from the silicon substrate 1. This not only ensures good passivation of the battery but also reduces the risk of phosphorus penetration into the silicon substrate 1, effectively improving the on-state voltage and short-circuit current. Simultaneously, it ensures good contact between the battery and the paste, reduces contact resistance, and increases the battery's fill factor. Specifically, the phosphorus doping concentration in the polycrystalline silicon layer 5 near the silicon substrate 1 can be in the range of 2 × 10⁻⁶. 20 / cm 3 ~2×10 21 / cm 3 Specifically, the phosphorus doping concentration in the doped polycrystalline silicon layer 5 near the silicon substrate 1 can be 2 × 10⁻⁶. 20 / cm 3 11×10 20 / cm 3 Or 2×10 21 / cm 3 The phosphorus doping concentration in the polycrystalline silicon layer 5, which is far from the silicon substrate 1, can range from 5 × 10⁻⁶. 20 / cm 3 ~5×10 21 / cm 3 Specifically, the phosphorus doping concentration in the doped polycrystalline silicon layer 5, which is far from the silicon substrate 1, can be 5 × 10⁻⁶. 20 / cm 3 27.5×10 20 / cm 3 Or 5×10 21 / cm 3 .

[0041] In one embodiment, reference continues... Figure 1As shown, at least two doped polysilicon layers 5 include a first doped polysilicon layer 51, a second doped polysilicon layer 52, and a third doped polysilicon layer 53. A first barrier layer 61 is provided between the first doped polysilicon layer 51 and the second doped polysilicon layer 52, and a second barrier layer 62 is provided between the second doped polysilicon layer 52 and the third doped polysilicon layer 53. The first doped polysilicon layer 51 is located on the side closer to the tunneling oxide layer 4, and the third doped polysilicon layer 53 is located on the side away from the tunneling oxide layer 4.

[0042] The first doped polycrystalline silicon layer 51 is doped with phosphorus, while the second doped polycrystalline silicon layer 52 and the third doped polycrystalline silicon layer 53 are doped with phosphorus and carbon or nitrogen, respectively. In other words, the first doped polycrystalline silicon layer 51, the second doped polycrystalline silicon layer 52, and the third doped polycrystalline silicon layer 53 are all doped with phosphorus. The second doped polycrystalline silicon layer 52 and the third doped polycrystalline silicon layer 53 are also doped with carbon or nitrogen in addition to phosphorus, which can increase the optical gap and reduce parasitic absorption. Of course, depending on the actual situation, the second doped polycrystalline silicon layer 52 can also be doped with only phosphorus without carbon or nitrogen, while the third doped polycrystalline silicon layer 53 can also be doped with carbon or nitrogen in addition to phosphorus, which can also increase the optical gap and reduce parasitic absorption.

[0043] In one embodiment, reference continues... Figure 1 As shown, the first electrode 2 includes a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 is electrically connected to the third doped polysilicon layer 53, and the second sub-electrode 22 is electrically connected to the first doped polysilicon layer 51 and / or the second doped polysilicon layer 52.

[0044] Specifically, the first electrode 2 includes a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 is electrically connected to the third doped polycrystalline silicon layer 53, and the second sub-electrode 22 is electrically connected to the second doped polycrystalline silicon layer 52. Alternatively, the second sub-electrode 22 is electrically connected to the first doped polycrystalline silicon layer 51. Or, a portion of the second sub-electrode 22 is electrically connected to the second doped polycrystalline silicon layer 52, and another portion of the second sub-electrode 22 is electrically connected to the first doped polycrystalline silicon layer 51. This more effectively reduces metal recombination, thereby increasing the open-circuit voltage of the solar cell and thus improving the photoelectric conversion efficiency of the solar cell.

[0045] In one embodiment, reference continues... Figure 1 As shown, the phosphorus doping concentration in the first doped polysilicon layer 51 is less than the phosphorus doping concentration in the second doped polysilicon layer 52, and the phosphorus doping concentration in the second doped polysilicon layer 52 is less than the phosphorus doping concentration in the third doped polysilicon layer 53.

[0046] Specifically, the phosphorus doping concentration in the first doped polysilicon layer 51, the second doped polysilicon layer 52, and the third doped polysilicon layer 53 gradually increases. Specifically, the phosphorus doping concentration in the first doped polysilicon layer 51 is low, which can reduce the risk of phosphorus diffusion into the battery and ensure good passivation effect. The phosphorus doping concentration in the third doped polysilicon layer 53 is high, which can ensure good contact between the battery and the slurry, reduce contact resistance, and improve the battery's fill factor. The phosphorus doping concentration in the second doped polysilicon layer 52 is between the phosphorus doping concentration in the first doped polysilicon layer 51 and the phosphorus doping concentration in the third doped polysilicon layer 53.

[0047] In one embodiment, reference continues... Figure 1 As shown, the carbon and nitrogen doping ratios in the second doped polysilicon layer 52 and the third doped polysilicon layer 53 are less than 5 wt%.

[0048] Specifically, if the carbon and nitrogen doping ratios in the second doped polysilicon layer 52 and the third doped polysilicon layer 53 are greater than 5 wt%, it will affect electron transport and passivation, thereby affecting battery efficiency. Therefore, reducing the carbon and nitrogen doping ratios in the second doped polysilicon layer 52 and the third doped polysilicon layer 53 to less than 5 wt% is beneficial to electron transport and passivation, thereby improving battery efficiency. Optionally, carbon and nitrogen are doped in the third doped polysilicon layer 53. Specifically, the carbon and nitrogen doping ratios in the second doped polysilicon layer 52 and the third doped polysilicon layer 53 can be 0.01 wt%, 1 wt%, 2 wt%, 3 wt%, 4 wt%, or 5 wt%.

[0049] In one embodiment, reference continues... Figure 1 As shown, the doping concentration ratio of phosphorus in the first doped polysilicon layer 51 and the third doped polysilicon layer 53 ranges from 0.4 to 1.

[0050] Specifically, if the phosphorus doping concentration ratio of the first doped polysilicon layer 51 to the third doped polysilicon layer 53 is less than 0.4, the phosphorus doping concentration in the third doped polysilicon layer 53 is too high, resulting in severe Auger recombination, which affects the short-circuit current and passivation effect of the battery, thus affecting the battery efficiency. If the phosphorus doping concentration ratio of the first doped polysilicon layer 51 to the third doped polysilicon layer 53 is greater than 1, the phosphorus doping concentration in the third doped polysilicon layer 53 is too low, resulting in high contact resistance, reducing the fill factor of the battery, and affecting the battery efficiency. Therefore, the ratio of the first doped polysilicon layer 51 to the third doped polysilicon layer 53 is... The phosphorus doping concentration ratio in the doped polycrystalline silicon layer 53 is set at 0.4-1. This not only avoids excessive phosphorus doping concentration in the third doped polycrystalline silicon layer 53, thereby reducing Auger recombination and improving the short-circuit current and passivation effect of the battery, but also prevents excessively low phosphorus doping concentration in the third doped polycrystalline silicon layer 53, thereby reducing contact resistance, improving the fill factor of the battery, and thus improving battery efficiency. Specifically, the phosphorus doping concentration ratio in the first doped polycrystalline silicon layer 51 and the third doped polycrystalline silicon layer 53 can be 0.4, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.

[0051] In one embodiment, reference continues... Figure 1 As shown, along the direction perpendicular to the silicon substrate 1, the total thickness of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and the third doped polysilicon layer 53 does not exceed 70 nm.

[0052] Specifically, if the total thickness of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and the third doped polysilicon layer 53 exceeds 70 nm along the direction perpendicular to the silicon substrate 1, it is impossible to reduce the total thickness of the polysilicon layer and improve parasitic absorption of light. Therefore, if the total thickness of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and the third doped polysilicon layer 53 does not exceed 70 nm along the direction perpendicular to the silicon substrate 1, the total thickness of the polysilicon layer can be reduced, parasitic absorption of light can be reduced, and production costs can be reduced. Specifically, the total thickness of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and the third doped polysilicon layer 53 can be 60 nm, 65 nm, or 70 nm along the direction perpendicular to the silicon substrate 1.

[0053] In one embodiment, reference continues... Figure 1 As shown, along the direction perpendicular to the silicon substrate 1, the thickness of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and / or the third doped polysilicon layer 53 ranges from 5 nm to 40 nm.

[0054] Specifically, if the thicknesses of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and the third doped polysilicon layer 53 are less than 5 nm along the direction perpendicular to the silicon substrate 1, there is a risk that the paste will burn through the tunnel oxide layer 4; if the thicknesses of the first doped polysilicon layer 51, the second doped polysilicon layer 52, or the third doped polysilicon layer 53 are less than 5 nm along the direction perpendicular to the silicon substrate 1, the uniformity of the doped polysilicon layers is difficult to control; if the thicknesses of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and ... less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon layers is less than 5 nm, the uniformity of the doped polysilicon If the thickness of the doped polysilicon layer 52 and / or the third doped polysilicon layer 53 is greater than 40 nm, it will increase the production cost. Therefore, along the direction perpendicular to the silicon substrate 1, the thickness of the first doped polysilicon layer 51, the second doped polysilicon layer 52, and / or the third doped polysilicon layer 53 is designed to be between 5 nm and 40 nm. This not only reduces the risk of the paste burning through the tunnel oxide layer 4, but also helps to control the uniformity of each doped polysilicon layer, while reducing the production cost. Specifically, along the direction perpendicular to the silicon substrate 1, the thickness of the first doped polysilicon layer 52 and / or the third doped polysilicon layer 53 is between 5 nm and 40 nm. The thickness of silicon layer 51 can be 40nm, 35nm, 30nm, 25nm, 20nm, 15nm, 10nm, or 5nm; along the direction perpendicular to silicon substrate 1, the thickness of second doped polysilicon layer 52 can be 40nm, 30nm, 20nm, 10nm, or 5nm; along the direction perpendicular to silicon substrate 1, the thickness of third doped polysilicon layer 53 can be 5nm, 10nm, 20nm, 30nm, or 40nm. Optionally, the thickness of first doped polysilicon layer 51 can be 40nm. The thickness of the first doped polysilicon layer 51 can be 35 nm, the thickness of the second doped polysilicon layer 52 can be 30 nm, and the thickness of the third doped polysilicon layer 53 can be 5 nm; or, the thickness of the first doped polysilicon layer 51 can be 30 nm, the thickness of the second doped polysilicon layer 52 can be 30 nm, and the thickness of the third doped polysilicon layer 53 can be 10 nm.

[0055] In one embodiment, reference continues... Figure 1 As shown, along the direction perpendicular to the silicon substrate 1, the thicknesses of the first barrier layer 61 and the second barrier layer 62 range from 0.5 nm to 2.5 nm, respectively.

[0056] Specifically, if the thickness of both the first barrier layer 61 and the second barrier layer 62 is less than 0.5 nm along the direction perpendicular to the silicon substrate 1, then the thickness of the first barrier layer 61 and the second barrier layer 62 is too thin, making it difficult to control uniformity in the manufacturing process, and the effect of preventing the paste from burning through will be poor. If the thickness of both the first barrier layer 61 and the second barrier layer 62 is greater than 2.5 nm along the direction perpendicular to the silicon substrate 1, then electron transport will be affected, severely impacting the fill factor of the battery. Therefore, the thickness range of the first barrier layer 61 and the second barrier layer 62 along the direction perpendicular to the silicon substrate 1 is designed to be within... The thickness of the first barrier layer 61 to 2.5 nm can not only avoid the first barrier layer 61 and the second barrier layer 62 being too thin, which is beneficial to the process control of the uniformity of the first barrier layer 61 and the second barrier layer 62, but also to electron transport and improve the fill factor of the battery. Specifically, along the direction perpendicular to the silicon substrate 1, the thickness of the first barrier layer 61 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm or 2.5 nm; along the direction perpendicular to the silicon substrate 1, the thickness of the second barrier layer 62 can be 0.5 nm, 1 nm, 1.5 nm, 2 nm or 2.5 nm.

[0057] Figure 2 This is a schematic flowchart of a method for preparing a solar cell provided by the present invention; continue referring to... Figure 1 and Figure 2 As shown, this embodiment provides a method for fabricating a solar cell, including the following steps: S1 Cleaning and texturing a silicon substrate 1;

[0058] S2 performs boron diffusion on the texturized silicon substrate 1 to form a boron-doped silicon layer;

[0059] S3 removes the borosilicate glass from the borosilicate layer on the back side, and then performs alkaline polishing on the back side.

[0060] After S4 alkaline polishing, a doped polycrystalline silicon layer 5 is deposited on the back side;

[0061] After the doped polycrystalline silicon layer 5 described in S5 is deposited, phosphorus diffusion is performed on the back side. After phosphorus diffusion, annealing is performed to crystallize the doped polycrystalline silicon layer 5 and activate the impurities.

[0062] After S6 annealing, the front doped polysilicon layer, front borosilicate glass, and back phosphosilicate glass are removed, and then films are deposited on the front and back.

[0063] S7 has the first electrode 2 and the second electrode 3 printed on the front and back coated surfaces, respectively;

[0064] After the first electrode 2 and the second electrode 3 are printed in S8, they are sintered. Multiple first electrodes 2 are electrically connected to different doped polycrystalline silicon layers 5.

[0065] Specifically, this embodiment also provides a method for fabricating a solar cell. This method can be a TOPCon cell fabrication method, using an N-type monocrystalline silicon wafer with a resistivity range of 0.3–2.1 Ohm·cm and a minority carrier lifetime >2.5 ms. The damaged layer on the silicon wafer surface is removed in a mixed solution of KOH and H₂O₂, followed by texturing in a KOH solution to form a pyramidal textured surface. The size of the pyramidal textured surface is controlled to be 1–5 μm. After texturing, the emitter is fabricated on the front side of the silicon wafer using boron diffusion, with a sheet resistance of 110–15 ohms. 0 Ohm.cm, the front borosilicate glass thickness is 50-120nm. After removing the borosilicate glass from the back of the silicon wafer, alkaline polishing is performed to achieve a reflectivity greater than 40% on the back side. After alkaline polishing, a doped polycrystalline silicon layer 5 is deposited on the back side using an LPCVD device. After the doped polycrystalline silicon layer 5 is deposited, it is directly doped using a phosphorus diffusion device and annealed directly with the phosphorus diffusion device to crystallize the polycrystalline silicon and promote and activate impurities (P). The annealing process conditions are: annealing at 800-1000℃ for 10-150min, with an annealing atmosphere of N2 (nitrogen) or pre-treated N2. After annealing, the silicon is cleaned using O2 (oxygen) in the later stages; alternatively, a doped polycrystalline silicon layer is deposited using PECVD equipment, with phosphorus doping occurring simultaneously during polycrystalline silicon deposition, followed by annealing to crystallize the polycrystalline silicon and promote and activate impurities (P). After annealing, the front-side doped polycrystalline silicon layer, the front-side borosilicate glass, and the back-side phosphorus silicate glass are removed, followed by another cleaning. After cleaning, films are deposited on both the front and back sides, such as depositing an aluminum oxide layer using ALD on the front side of the silicon wafer and preparing a silicon nitride layer using PECVD; a first passivation layer is deposited on the back side of the silicon wafer to complete the preparation of the battery precursor; surface After passivation, metallization is performed on the front and back sides of the silicon wafer. The first electrode 2 is printed on the back side of the silicon wafer and the second electrode 3 is printed on the front side by screen printing. Since the paste (silver particles) are of different sizes and shapes, the depth to which the first electrode 2 is burned into the doped polycrystalline silicon layer 5 is also different. Multiple first electrodes 2 are electrically connected to different doped polycrystalline silicon layers 5. After screen printing the first electrode 2 and the second electrode 3, the first electrode 2 is burned into the doped polycrystalline silicon layer 5 at a high temperature of 850°-950°, and the second electrode 3 is burned into the emitter layer, thus completing the battery fabrication.

[0066] As can be seen from the above embodiments, the method for preparing solar cells provided in this embodiment achieves at least the following beneficial effects:

[0067] The method for fabricating a solar cell provided in this embodiment involves cleaning and texturing a silicon substrate 1; performing boron diffusion on the texturized silicon substrate 1 to form a boron-doped silicon layer; removing the borosilicate glass from the boron-doped silicon layer on the back side, followed by alkaline polishing of the back side; depositing a doped polycrystalline silicon layer 5 on the back side after alkaline polishing; removing the doped polycrystalline silicon layer 5 on the front side and then coating the back side with a phosphorus-containing liquid dopant, followed by drying; annealing the dried phosphorus-containing liquid dopant to crystallize the doped polycrystalline silicon layer 5 and activate impurities; depositing films on the front and back sides; printing a first electrode 2 and a second electrode 3 on the surfaces of the films on the front and back sides, respectively; and sintering after printing the first electrode 2 and the second electrode 3. Multiple first electrodes 2 are electrically connected to different doped polycrystalline silicon layers 5. This method reduces metal recombination, thereby increasing the open-circuit voltage of the solar cell and improving its photoelectric conversion efficiency.

[0068] In one embodiment, reference continues... Figure 1 As shown, after alkaline polishing, the deposition of the back-side stacked doped polysilicon layer 5 includes: firstly, preparing a tunneling oxide layer 4 and depositing a first doped polysilicon layer 51; secondly, preparing a first barrier layer 61 and depositing a second doped polysilicon layer 52; and finally, preparing a second barrier layer 62 and depositing a third doped polysilicon layer 53.

[0069] Specifically, the deposition of the stacked doped polycrystalline silicon layer 5 can be performed using PECVD (Plasma Enhanced Chemical Vapor Deposition) at a temperature of 350-480℃ and a power of 6000W-15000W; the tunneling oxide layer 4 is grown using N2O (laughing gas) with a processing time of 10-60s; the first doped polycrystalline silicon layer 51 is grown in situ using a mixed gas of PH3 (phosphine) and SiH4 (silane) with a processing time of 100-300s; after the first doped polycrystalline silicon layer 51 is grown, the first barrier layer 61 is grown using N2O with a processing time of 10-60s; or the first barrier layer 61 is grown using a mixed gas of SiH4, N2O, and NH3. A barrier layer 61 is formed, with a process time of 1-10 seconds. After the first barrier layer 61 is grown, the second doped polysilicon layer 52, the second barrier layer 62, and the third doped polysilicon layer 53 are grown sequentially in the above manner. When growing the second doped polysilicon layer 52 and / or the third doped polysilicon layer 53, a mixed gas of PH3, SiH4, and CH4 (or NH3) can be used for growth, with a process time of 30-300 seconds. By adopting the above scheme, not only can the total thickness of the polysilicon layer be reduced, but the thinner polysilicon layer can reduce parasitic absorption, thereby increasing the short-circuit current. Moreover, the barrier layer 6 prevents the risk of the slurry burning through the tunnel oxide layer 4.

[0070] In one embodiment, reference continues... Figure 1As shown, the first electrode 2 includes a first sub-electrode 21 and a second sub-electrode 22. The first sub-electrode 21 is electrically connected to the third doped polycrystalline silicon layer 53, and the second sub-electrode 22 is electrically connected to the first doped polycrystalline silicon layer 51 and / or the second doped polycrystalline silicon layer 52. The first electrode 2 has been described in detail in the solar cell and will not be repeated here.

[0071] Figure 3 This is a schematic diagram of a photovoltaic module provided by the present invention, with reference to... Figure 3 As shown, this embodiment provides a photovoltaic module, including a first encapsulation panel 201, a first encapsulation film 202, a cell string 203, a second encapsulation film 204, and a second encapsulation panel 205 stacked together. The cell string 203 is formed by electrically connecting multiple of the above-mentioned solar cells.

[0072] Specifically, the photovoltaic module includes a first encapsulation panel 201, a first encapsulation film 202, a cell string 203, a second encapsulation film 204, and a second encapsulation panel 205 stacked together. The cell string 203 is formed by electrically connecting multiple solar cells. The first encapsulation panel 201 can be made of tempered glass with high light transmittance, reaching over 92%, and is generally made of low-iron tempered patterned glass. The second encapsulation panel 205 can be made of glass, TPT (polyvinyl fluoride composite film), or TPE (thermoplastic elastomer). The second encapsulation panel 205 is used to protect the internal encapsulation materials and cells from mechanical damage. It is resistant to mechanical damage and external environmental corrosion, and also possesses excellent insulation properties, which largely determine the service life of the component. It exhibits excellent weather resistance, low water vapor permeability, good electrical insulation, and a certain degree of bonding strength. The first encapsulating film 202 and the second encapsulating film 204 can be made of EVA (ethylene-vinyl acetate copolymer), POE (random copolymer elastomer of ethylene and high-carbon α-olefins), or PVB (polyvinyl butyral). EVA material, due to the introduction of vinyl acetate monomers into the molecular chain, can reduce high crystallinity and improve toughness, impact resistance, filler compatibility, and heat-sealing performance. The molecular structure of POE material gives it excellent mechanical properties, rheological properties, and UV resistance, and it also features good affinity with polyolefins, good low-temperature toughness, and a high performance-price ratio. PVB material is soluble in methanol, ethanol, ketones, haloalkanes, and aromatic solvents. It has good compatibility with phthalates, sebacic acid esters, benzene plasticizers, nitrocellulose, phenolic resins, and epoxy resins. It has high transparency, cold resistance, impact resistance, and UV radiation resistance. It also has good adhesion to metals, glass, wood, ceramics, and fiber products. The first encapsulation film 202 and the second encapsulation film 204 are used to encapsulate and protect the battery cells, preventing external environmental factors from affecting their performance. They bond the first encapsulation panel 201, the solar cells, and the second encapsulation panel 205 together, exhibiting a certain bonding strength, high light transmittance, reasonable cross-linking degree, excellent UV aging resistance, excellent damp heat aging resistance, extremely low shrinkage rate, and long-term strong adhesion to various first encapsulation panels 201 and second encapsulation panels 205. It also has high volume resistivity. The battery string 203 is formed by electrically connecting multiple solar cells (not shown in the figure), with two adjacent solar cells electrically connected by solder ribbons (not shown in the figure).

[0073] As can be seen from the above embodiments, the solar cell and photovoltaic module provided by the present invention achieve at least the following beneficial effects:

[0074] The present invention provides a solar cell and a photovoltaic module. The solar cell includes a silicon substrate, a first electrode, and a second electrode. A tunneling oxide layer is disposed on one side of the silicon substrate along the direction away from the silicon substrate. At least two doped polycrystalline silicon layers are disposed on the side of the tunneling oxide layer away from the silicon substrate. A barrier layer is disposed between adjacent doped polycrystalline silicon layers. Multiple first electrodes are electrically connected to different doped polycrystalline silicon layers. By adopting the above solution, the problem of light absorption and metallization balance in thin-layer polycrystalline silicon is solved as a whole. Specifically, it can not only reduce the total thickness of the polycrystalline silicon layer, but also reduce parasitic absorption and thus increase the short-circuit current. Moreover, the barrier layer prevents the risk of the paste burning through the tunneling oxide layer, while reducing metal recombination, thereby increasing the open-circuit voltage of the solar cell and improving the photoelectric conversion efficiency of the solar cell.

[0075] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A solar cell, characterized in that, Includes a silicon substrate, a first electrode, and a second electrode; A tunneling oxide layer is disposed on one side of the silicon substrate in a direction away from the silicon substrate. At least two doped polysilicon layers are disposed on the side of the tunneling oxide layer away from the silicon substrate. A barrier layer is disposed between adjacent doped polysilicon layers. Multiple first electrodes are electrically connected to different doped polysilicon layers.

2. The solar cell according to claim 1, characterized in that, The phosphorus doping concentration in the doped polycrystalline silicon layer closer to the silicon substrate is less than the phosphorus doping concentration in the doped polycrystalline silicon layer farther from the silicon substrate.

3. The solar cell according to claim 1, characterized in that, The at least two doped polysilicon layers include a first doped polysilicon layer, a second doped polysilicon layer, and a third doped polysilicon layer. A first barrier layer is provided between the first doped polysilicon layer and the second doped polysilicon layer, and a second barrier layer is provided between the second doped polysilicon layer and the third doped polysilicon layer. The first doped polysilicon layer is located on the side closer to the tunneling oxide layer, and the third doped polysilicon layer is located on the side farther away from the tunneling oxide layer. The first doped polycrystalline silicon layer is doped with phosphorus, and the second and third doped polycrystalline silicon layers are doped with phosphorus, carbon, or nitrogen, respectively.

4. The solar cell according to claim 3, characterized in that, The first electrode includes a first sub-electrode and a second sub-electrode. The first sub-electrode is electrically connected to the third doped polysilicon layer, and the second sub-electrode is electrically connected to the first doped polysilicon layer and / or the second doped polysilicon layer.

5. The solar cell according to claim 3, characterized in that, The phosphorus doping concentration in the first doped polysilicon layer is less than that in the second doped polysilicon layer, and the phosphorus doping concentration in the second doped polysilicon layer is less than that in the third doped polysilicon layer.

6. The solar cell according to claim 3, characterized in that, The carbon and nitrogen doping ratios in the second and third doped polysilicon layers are less than 5 wt%.

7. The solar cell according to claim 3, characterized in that, The phosphorus doping concentration ratio in the first doped polycrystalline silicon layer and the third doped polycrystalline silicon layer is 0.4-1.

8. The solar cell according to claim 3, characterized in that, Along a direction perpendicular to the silicon substrate, the total thickness of the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer does not exceed 70 nm.

9. The solar cell according to claim 8, characterized in that, Along a direction perpendicular to the silicon substrate, the thickness of the first doped polysilicon layer, the second doped polysilicon layer, and / or the third doped polysilicon layer ranges from 5 to 40 nm.

10. The solar cell according to claim 3, characterized in that, Along a direction perpendicular to the silicon substrate, the thicknesses of the first barrier layer and the second barrier layer range from 0.5 to 2.5 nm, respectively.

11. The solar cell according to any one of claims 1-10, characterized in that, The silicon substrate includes a base region and an emitter, the emitter being located on the side of the base region away from the tunneling oxide layer, and a passivation layer being disposed on the side of the emitter away from the base region; The second electrode penetrates the passivation layer and is electrically connected to the emitter.

12. A photovoltaic module, characterized in that, It includes a first encapsulation panel, a first encapsulation film, a battery string, a second encapsulation film, and a second encapsulation panel stacked together, wherein the battery string is formed by electrical connections of a solar cell as described in any one of claims 1-11.

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