FPGA implementation method for 64-parallel LDPC decoder to solve different lifting values

Abstract

The application relates to an FPGA implementation method for a 64-parallel LDPC decoder to solve different lifting values, which comprises the following steps: obtaining a group of variable node input matrices X 1*i in a decoder by demodulation, wherein the group of variable node input matrices represent i minimum load routing LLRs of variable nodes; dividing the group of variable node input matrices X 1*i into Q parts by using a decoding parallel degree P to obtain a group of variable node reshaped matrices X _new ; when a cyclic shift value CS corresponding to a variable node of the input matrix X Q*P is greater than or smaller than P, judging whether an intermediate variable CS _new is equal to 0 to confirm a number of shifted rows of the group of variable node reshaped matrices X _new ; and sequentially splicing input data of the group of variable node reshaped matrices X _new by shifting the number of rows downward according to the number of shifted rows of the group of variable node reshaped matrices X _new . Therefore, the application can not only reduce the parallel degree size of a decoding process, but also save hardware resources of an FPGA.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication and digital signal processing, and relates to an FPGA implementation method for a 64-parallel LDPC decoder to decode different boost values. Background Technology

[0002] LDPC codes, or Low Density Parity Check codes, are a class of linear block codes with sparse parity-check matrices proposed by Dr. Robert G. Gallager in 1963. They not only offer good performance approaching the Shannon limit but also have low decoding complexity and flexible structure, making them a hot research topic in channel coding in recent years. Over time, LDPC codes have been widely applied in various digital mobile communication systems, becoming a coding scheme in standards such as EEE802.11ad and DVB-S2. Furthermore, in October 2016, they were successfully selected from multiple coding schemes as the medium-length block coding scheme for the data channel of the 5G standard enhanced Mobile Broadband service.

[0003] Because LDPC codes have low decoding complexity, they are well-suited for parallel decoding and support high-throughput transmission. Properly designed LDPC codes have a very low error plateau, fully meeting the requirements of high-throughput transmission and reliability in 5G. In 2001, Lin Shu et al., combining algebraic and geometric theories, proposed a novel structured LDPC code. Because the parity-check matrix of this code has a quasi-cyclic structure, it was named Quasi-Cyclic LDPC Codes (QC-LDPC Codes). Compared to random-structured LDPC codes, QC-LDPC codes exhibit superior performance in hardware implementation and error rate, thus gaining widespread popularity in practical applications. Given the excellent characteristics of QC-LDPC, NR LDPC codes also adopt this quasi-cyclic structure.

[0004] Because the 3GPP protocol specifies that 5G uses a variety of values ​​for the enhancement value Zc, when Zc equals the maximum value of 384, decoding with low parallelism takes longer than decoding with high parallelism. Furthermore, high parallelism decoders also consume excessive hardware resources. Therefore, how to achieve maximum throughput while minimizing hardware resource consumption is a new research topic. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide an FPGA implementation method for a 64-parallel LDPC decoder that decodes different boost values, thereby solving the technical problem of how to achieve low hardware resource consumption while ensuring maximum throughput.

[0006] To achieve the above objectives, this invention provides an FPGA implementation method for a 64-parallel LDPC decoder that decodes different boost values, wherein:

[0007] Demodulation yields a set of variable node input matrices in the decoder. The input matrix of this set of variable nodes represents the i minimum load routing (LLR) of the variable nodes, where , Zc is the decoder boost value;

[0008] The set of variable nodes are input into the matrix using the decoding parallelism P. After dividing the variable nodes into Q equal parts, the reshaping matrix of this group of variable nodes is obtained. ,in The X Q* P The specific matrix representation is as follows:

[0009]

[0010] in, , , ;

[0011] When the reshaping matrix When the cyclic shift value CS corresponding to the variable node is greater than or less than P, determine the intermediate variable. Whether it equals 0 is used to confirm the reshaping matrix of this group of variable nodes. Number of rows to shift; where CS is the reshaping matrix. The cyclic shift value corresponding to the variable node, m is the reshaping matrix when Zc is at its maximum value. The cyclic shift value corresponding to the variable node;

[0012] Reshape the matrix based on this set of variable nodes. Shifting down by row number sequentially reshapes the matrix of the variable nodes in this group. The input data is then concatenated.

[0013] Preferably, when the reshaped matrix The cyclic shift value CS corresponding to the variable node is greater than P and When the value is not equal to 0, the set of variable nodes reshapes the matrix. Line 0 to Shifting the row K positions to the right reshapes the matrix for that group of variable nodes. No. Move to the right when you reach line Q Bit; when the reshaping matrix The cyclic shift value CS corresponding to the variable node is greater than P and When the value is 0, the set of variable nodes reshapes the matrix. Shift right by K positions.

[0014] Preferably, when the reshaped matrix The cyclic shift value CS corresponding to the variable node is less than P and When the value is not equal to 0, the set of variable nodes reshapes the matrix. Line 0 to Shifting the row M positions to the right reshapes the matrix for that group of variable nodes. Q-CS _new Move to the right when you reach line Q Bit; when the reshaping matrix The cyclic shift value CS corresponding to the variable node is less than P and When the value is 0, the set of variable nodes reshapes the matrix. Move right Bit.

[0015] More preferably, the formula for calculating K is as follows: .

[0016] More preferably, the formula for calculating M is as follows: .

[0017] More preferably, the decoder's de-boost value .

[0018] The beneficial effects of this invention are as follows: This invention achieves high-throughput decoding requirements by reshaping the decoder input matrix, reducing the parallelism of the decoding process and saving FPGA hardware resources. Attached Figure Description

[0019] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the following figures are provided for illustration:

[0020] Figure 1 This is a basic flowchart of the implementation method in the embodiments of the present invention;

[0021] Figure 2 This is a graph showing the FPGA resource usage curves for direct and grouped cyclic shifting in an embodiment of the present invention. Detailed Implementation

[0022] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] The 3GPP protocol mentions that the core of the entire encoding / decoding process includes: the base map (BG), the boost value (Zc), and the cyclic shift value (CS). The BG is the prerequisite for the design of the LDPC code PCM (Parity-Check Matrix) and determines the macroscopic characteristics and overall performance of the LDPC code. There are two cases for the BG, which can generally be represented by an H matrix. The H matrix is ​​divided into six parts: A, B, C, D, 0, and I. The size of B is fixed at 4×4, 0 represents the zero matrix (a matrix where all elements are 0), and I represents the identity matrix (a matrix with 1s on the main diagonal). The H matrix has two forms depending on the base map, as shown in Tables 1 and 2.

[0024] 4 A B 0 42 C D I

[0025] Table 1 Base Map (64*68)

[0026] 4 A B 0 38 C D I

[0027] Table 2 Base Map (42*52)

[0028] The boost value Zc in an LDPC decoder is obtained based on the encoding method. QC-LDPC is mainly reflected in the decoding process, and will use... The identity matrix is ​​used to fill the position of each point in the base map. The identity matrix is ​​cyclically shifted according to different cyclic shift values ​​(CS), and then multiplied with the information to achieve information exchange. The essence of the LDPC decoding process is the exchange of information between the variable node (the position of the code to be corrected) and the check node (the layer number of the code to be corrected). Currently, there are LDPC decoders with a parallelism of 128 on the market. This study chooses 64 as the decoding parallelism size, which not only saves hardware resources but also makes it very easy to implement cyclic shifts using the Banyan network when the parallelism is 64. Therefore, this invention provides a 64-parallelism LDPC decoder implementation method for different boost values ​​on FPGA, such as... Figure 1 As shown, the specific steps are explained below:

[0029] Demodulation yields a set of variable node input matrices in the decoder. The input matrix of this set of variable nodes represents the i minimum load routing (LLR) of the variable nodes, where , Zc is the boost value of the decoder. The LLR is obtained through demodulation, which is the process of recovering the message from the modulated signal carrying the message. Commonly used demodulation methods include BPSQ, 16QAM, 64QAM, and 256QAM, with the specific method chosen based on the actual situation. The boost values ​​of Zc are shown in Table 3. Since the 3GPP TS 38.212 V16.1.0 protocol mentions that 5G uses a variety of boost values ​​for Zc, when Zc equals the maximum value of 384 specified in the protocol, decoding with 64 parallelism will take longer than decoding with 384 parallelism.

[0030]

[0031] Table 3. Values ​​of Zc

[0032] The set of variable nodes are input into the matrix using the decoding parallelism P. After dividing the variable nodes into Q equal parts, the reshaping matrix of this group of variable nodes is obtained. ,in The The specific matrix representation is as follows:

[0033]

[0034] in, , , ;

[0035] When the reshaping matrix When the cyclic shift value CS corresponding to the variable node is greater than or less than P, determine the intermediate variable. Whether it equals 0 is used to confirm the reshaping matrix of this group of variable nodes. Number of rows to shift; where CS is the reshaping matrix. The cyclic shift value corresponding to the variable node, m is the input matrix when Zc is at its maximum value. The cyclic shift value corresponding to the variable node; the maximum value of the decoder's solution boost Zc is 384;

[0036] Reshape the matrix based on this set of variable nodes. Shifting down by row number sequentially reshapes the matrix of the variable nodes in this group. The input data is concatenated. The algorithm principle in this embodiment mentions that the data will shift downwards, but this downward shift does not actually occur in FPGA operation. Therefore, the downward shift can be achieved through subsequent data concatenation. This is because we used a special grouping method when splitting 384 into 64, requiring data concatenation to be performed according to the order of the split array. For example, assuming the first three groups of data are shifted right by K positions, and the last three groups of data are shifted right by K-1 positions, the data concatenation order is: the first data of the 4th group, the first data of the 5th group, the first data of the 6th group, the first data of the 1st group, the first data of the 2nd group, the first data of the 3rd group, the second data of the 4th group, and so on.

[0037] When the reshaping matrix The cyclic shift value CS corresponding to the variable node is greater than P and When the value is not equal to 0, the set of variable nodes reshapes the matrix. Line 0 to Shifting the row K positions to the right reshapes the matrix for that group of variable nodes. No. Move to the right when you reach line Q Bit; when the reshaping matrix X _new The cyclic shift value CS corresponding to the variable node is greater than P and When the value is 0, the set of variable nodes reshapes the matrix. Shift right by K bits. The formula for calculating K is as follows: .

[0038] When the reshaping matrix The cyclic shift value CS corresponding to the variable node is less than P and When the value is not equal to 0, the set of variable nodes reshapes the matrix. Line 0 to Shifting the row M positions to the right reshapes the matrix for that group of variable nodes. No. Move to the right when you reach line Q Bit; when the reshaping matrix X _new The cyclic shift value CS corresponding to the variable node is less than P and When the value is 0, the set of variable nodes reshapes the matrix. Move right The formula for calculating M is as follows: .

[0039] To better understand the embodiments of the present invention, the specific details are as follows:

[0040] First, it needs to be explained that the FPGA implementation transforms the written Verilog code into fixed-size hardware resources. Therefore, the 64 parallelism used in decoding means that at most 64 LLRs contained in each variable node can be processed at one time, where LLRs represent probability values ​​of 0 or 1. However, the specific number of LLRs for each variable node will be the same as Zc, and the cyclic shift value (CS) corresponding to different Zcs is different. Therefore, the purpose of this embodiment is to achieve data processing of 384 LLRs when the resource size is fixed at 64. It should be noted that the number of LLRs corresponding to each variable node after demodulation is determined by the encoding boost value, while the decoding boost value is fixed at 64.

[0041] For the decoding process of QC-LDPC code layered minimum sum, the information transfer between check nodes and variable nodes during the decoding process is completed through matrix looping. When the lift value Zc equals 384, it is equivalent to filling the positions of variable nodes with a size of 384*384 in the base matrix with the variable node being 1. This is based on the standard protocol of 5G mobile communication. Figure 1 The specific implementation plan is illustrated using an example.

[0042] ① Input parameters:

[0043] Assuming the demodulated LLR is an ordered array, let the information contained in the first variable node be... It contains 384 LLRs, and then: .

[0044] Because the 3GPP TS 38.212 V16.1.0 protocol stipulates that the boost value during encoding should be consistent with the boost value during decoding, but the FPGA size in this technical solution is only 64, the actual boost value during encoding and the boost value during decoding are different. Assuming the boost value during encoding is Zc_encode=384 and the boost value during decoding is Zc_decode=64;

[0045] Assume the cyclic shift value corresponding to the first variable node is m;

[0046] ② In this technical solution, the decoding parallelism P is 64, meaning that at most 64 LLRs can be processed at a time. Therefore, the LLR of this variable node is divided into 6 equal parts (i.e., Q equals 6), and reshaped into the following matrix. :

[0047]

[0048] The formula for calculating Q is as follows: ,

[0049] ③Assuming the cyclic shift number (CS) is m when Zc=384, then

[0050] First, calculate the relevant parameters as follows:

[0051] ,

[0052] ,

[0053] ;

[0054] Let's discuss the cases separately as follows:

[0055] When CS is greater than 64 and When it is not equal to 0, then Line 0 to 6 (subtract) Shift the row to the right by K positions. No. Move the row to the right by K-1 positions when it reaches the 6th row.

[0056] When CS is greater than 64 and When it equals 0, then Shift right by K positions.

[0057] When CS is less than or equal to 64 and n is not equal to 0, then Line 0 to 6 (subtract) Shift the row M positions to the right. No. Move to the right after reaching line 6 bit, i.e., left shift Bit.

[0058] When CS is less than 64 and n equals 0, A is shifted to the right by -CS divided by 6 bits, which is equivalent to shifting A to the left by CS divided by 6 bits.

[0059] ③ In the FPGA implementation, only 64 LLRs are processed at a time. Therefore, all 6 sets of data need to be cyclically shifted before data splicing. The splicing order is determined by the number of rows shifted down, thus realizing the solution of 384 parallel data with 64 parallelism.

[0060] ④ Pass the shifted data to the next module (i.e., the verification node update module) to complete the addition and subtraction functions. After all 6 sets of data have been processed, the data splicing is completed.

[0061] like Figure 2As shown, in an FPGA, a LUT (Look-Up Table) is essentially a RAM where data is pre-stored. When a signal is input, the table is looked up based on the address pointed to by the signal to find the corresponding content for output. Before grouping, the FPGA resources occupied were 23314, which are reduced to 1464 after grouping using the implementation method of this embodiment. Similarly, before grouping, the FPGA resources occupied by FFs (flip-flops) were 7430, which are reduced to 401 after grouping using the implementation method of this embodiment.

[0062] In summary, this embodiment of the invention completes the decoding requirement of a boost value of 384 by using a decoder with a boost value of 64, reducing the parallelism of the decoding process and saving FPGA hardware resources. At the same time, it can also be used as an analogy to decode 384 using a 64 decoder, and can be extended to implement the 64 decoder to the LLR corresponding to any boost value Zc specified by the 3GPP TS 38.212 V16.1.0 protocol.

[0063] Finally, it should be noted that the above preferred embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail through the above preferred embodiments, those skilled in the art should understand that various changes can be made to it in form and detail without departing from the scope defined by the claims of the present invention.

Claims

1. A method for implementing a 64-parallel LDPC decoder with different boost values ​​on an FPGA, characterized in that: Demodulation yields a set of variable node input matrices in the decoder. The input matrix of this set of variable nodes represents the i minimum load routing (LLR) of the variable nodes, where , Zc is the decoder boost value; The set of variable nodes are input into matrix X using the decoding parallelism P. 1* i After dividing the variable nodes into Q equal parts, the reshaping matrix X of this group of variable nodes is obtained. _new , where X _new =X Q* P The X Q* P The specific matrix representation is as follows: ， in, , , ; When the reshaping matrix When the cyclic shift value CS corresponding to the variable node is greater than P, determine the intermediate variable. Whether it equals 0 is used to confirm the reshaping matrix of this group of variable nodes. Shift row number; or when the reshaped matrix When the cyclic shift value CS corresponding to a variable node is less than P, check whether the intermediate variable CS_new is equal to 0 to confirm that the matrix of that group of variable nodes has been reshaped. Number of rows to shift; where CS is the reshaping matrix. The cyclic shift value corresponding to the variable node, m is the reshaping matrix when Zc is at its maximum value. The cyclic shift value corresponding to the variable node; Reshape the matrix based on this set of variable nodes. Shifting down by row number sequentially reshapes the matrix of the variable nodes in this group. The input data is then concatenated.

2. The FPGA implementation method for a 64-parallel LDPC decoder with different boost values ​​according to claim 1, characterized in that: When the reshaping matrix The cyclic shift value CS corresponding to the variable node is greater than P and When the value is not equal to 0, the set of variable nodes reshapes the matrix. Line 0 to Shifting the row K positions to the right reshapes the matrix for that group of variable nodes. No. Move to the right when you reach line Q Bit; when the input matrix The cyclic shift value CS corresponding to the variable node is greater than P and When the value is 0, the set of variable nodes reshapes the matrix. Shift right by K bits, where K is calculated using the following formula: .

3. The FPGA implementation method for a 64-parallel LDPC decoder with different boost values ​​according to claim 1, characterized in that: When the reshaping matrix The cyclic shift value CS corresponding to the variable node is less than P and When the value is not equal to 0, the set of variable nodes reshapes the matrix. Line 0 to Shifting the row M positions to the right reshapes the matrix for that group of variable nodes. No. Move to the right when you reach line Q Bit; when the reshaping matrix The cyclic shift value CS corresponding to the variable node is less than P and When the value is 0, the set of variable nodes reshapes the matrix. Move right The specific formula for calculating M is as follows: .

4. The FPGA implementation method for a 64-parallel LDPC decoder with different boost values ​​according to claim 1, characterized in that: The decoder's de-boost value .

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