A flash memory array and a flash memory chip

Abstract

The application discloses a flash memory array and a flash memory chip. The flash memory array comprises a plurality of flash memory modules arranged in an array; the flash memory module comprises a memory and computing unit and at least one dummy unit; the memory and computing unit and the dummy unit are arranged alternately; the dummy unit comprises a first substrate, a first drain region, a first source region and a first channel region located in the first substrate, and a first selection gate, a first control gate and a first floating gate located on the first substrate; wherein the first control gate and the first floating gate are located on a first side of the first selection gate; the first drain region is located on a second side of the first selection gate in the first substrate; the dummy unit further comprises a first silicide structure, the first silicide structure is located on a surface of the first drain region away from the first substrate, and the first silicide structure is not connected with the first substrate. The technical scheme of the embodiment of the application improves the programming efficiency and accuracy of the memory and computing unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flash memory, and particularly relates to a flash memory array and a flash memory chip. BACKGROUND

[0002] Flash memory is a kind of non-volatile memory, and data will not be lost after power-off, so it is widely used. With the increasing requirements of flash memory technology, the storage and computing integrated flash memory unit has developed rapidly.

[0003] When the storage and computing flash memory unit is included in the flash memory chip, the select gates of the two storage and computing flash memory units need to be separated to avoid interference of the storage and computing flash memory unit on the adjacent storage and computing flash memory unit during programming operation. When the select gates of the storage and computing flash memory units are separated, in order to avoid damage to the storage and computing flash memory unit, a dummy flash memory unit is arranged between the two storage and computing flash memory units.

[0004] However, the channel of the dummy flash memory unit in the existing scheme is more susceptible to process deviation, which causes larger leakage current of the dummy flash memory unit, and interference to the voltage of the storage and computing flash memory unit in programming, thereby affecting the programming ability or programming efficiency of the storage and computing flash memory unit. SUMMARY

[0005] The present application provides a flash memory array and a flash memory chip to solve the problem that the dummy flash memory unit affects the programming ability or programming efficiency of the storage and computing flash memory unit.

[0006] According to an aspect of the present application, a flash memory array is provided, characterized in that it comprises a plurality of flash memory modules arranged in an array; the flash memory module comprises one storage and computing unit and at least one dummy unit;

[0007] The storage and computing unit and the dummy unit are arranged alternately;

[0008] The dummy unit comprises a first substrate, a first drain region, a first source region and a first channel region located in the first substrate, and a first select gate, a first control gate and a first floating gate located on the first substrate; wherein the first control gate and the first floating gate are located on a first side of the first select gate; the first drain region is located on a second side of the first select gate in the first substrate;

[0009] The dummy unit further comprises a first silicide structure, the first silicide structure is located on the surface of the first drain region away from the first substrate, and the first silicide structure is not connected with the first substrate.

[0010] Optionally, the storage and computing unit comprises a second substrate, a second drain region, a second source region and a second channel region located in the second substrate, and a second select gate, a second control gate and a second floating gate located on the second substrate; wherein the second control gate and the second floating gate are located at a first side of the second select gate; a projection of the second drain region on the second substrate is located at a second side of a projection of the second select gate on the second substrate.

[0011] The first drain region and the second drain region have the same size.

[0012] Optionally, the flash memory array further comprises a plurality of source lines.

[0013] The source lines are connected to the source regions of the storage and computing units one by one; wherein, when a target storage and computing unit is programmed, the source lines adjacent to the target source line are used to write a protection voltage to the corresponding storage and computing units; wherein, the target source line is the source line corresponding to the target storage and computing unit.

[0014] Optionally, the first drain region is a shallow trench.

[0015] Optionally, the projection of the first select gate on the first substrate comprises a first part overlapping the projection of the first channel region on the first substrate, and a second part exposed to the first channel region.

[0016] The length of the first part is greater than a first preset length; wherein, the preset length is half of the width of the first select gate; the length of the first part and the width of the first select gate are the dimensions of a first direction, and the first direction is the direction in which the first side of the first select gate points to its second side.

[0017] The width of the second part is greater than a process deviation value.

[0018] Optionally, the storage and computing unit comprises a second substrate, a second drain region, a second source region and a second channel region located in the second substrate, and a second select gate, a second control gate and a second floating gate located on the second substrate; wherein the second control gate and the second floating gate are located at a first side of the second select gate; a projection of the second drain region on the second substrate is located at a second side of a projection of the second select gate on the second substrate.

[0019] The dummy unit further comprises a first spacer located at a second side of the first select gate.

[0020] The length of the first drain region in the first direction is greater than a second preset length, and the length difference of the first drain region and the second drain region in the first direction is greater than a third preset length; wherein the first direction is a direction in which a first side of the first select gate points to a second side of the first select gate; the second preset length is a sum of the length of the first spacer in the first direction and a process deviation value, and the third preset length is one half of a photolithography pitch.

[0021] Optionally, in one of the flash memory modules, the first select gate of the dummy cell and the second select gate of the storage and computing cell are an integral select gate.

[0022] The select gates between adjacent two of the flash memory modules are not connected.

[0023] Optionally, the dummy cell further comprises a first erase gate.

[0024] The first erase gate is located on the first source region, and the first erase gate is located on a side of the first control gate away from the first select gate.

[0025] The storage and computing cell comprises a second substrate, a second drain region, a second source region and a second channel region located in the second substrate, and a second select gate, a second control gate, a second floating gate and a second erase gate located on the second substrate; wherein the orthographic projection of the second control gate and the second floating gate on the second substrate is located on a first side of the orthographic projection of the second select gate on the second substrate; the orthographic projection of the second drain region on the second substrate is located on a second side of the orthographic projection of the second select gate on the second substrate; the second erase gate is located on a side of the second control gate away from the second select gate, and the second erase gate is located on the second source region.

[0026] Optionally, in one of the flash memory modules, the first erase gate and the second erase gate are an integral erase gate.

[0027] The erase gates between adjacent two of the flash memory modules are not connected.

[0028] According to another aspect of the present application, there is provided a flash memory chip comprising the flash memory array according to any of the embodiments of the present application.

[0029] The technical scheme of the embodiment of the present application is characterized in that the first silicide structure of the dummy unit is not connected with the first substrate, that is, the first channel region of the dummy unit is not connected with the first substrate, so that the electrons cannot leak from the first substrate to the first source region through the first silicide structure, thereby avoiding the leakage of the first source region of the dummy unit to the first substrate, and greatly reducing the leakage of the dummy unit, thereby avoiding the interference of the dummy unit to the programming storage and computing unit, and improving the programming efficiency and accuracy of the storage and computing unit.

[0030] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0032] Figure 1 is a cross-sectional view of a dummy flash memory unit in the prior art;

[0033] Figure 2 is a top plan view of a flash memory array provided by an embodiment of the present application;

[0034] Figure 3 is Figure 2 is a cross-sectional view along the A1-A2 direction;

[0035] Figure 4 is Figure 2 is a cross-sectional view along the B1-B2 direction;

[0036] Figure 5 is a top plan view of another flash memory array provided by an embodiment of the present application;

[0037] Figure 6 is Figure 5 is a cross-sectional view along the C1-C2 direction;

[0038] Figure 7 is a circuit structure schematic diagram of a flash memory array provided by an embodiment of the present application;

[0039] Figure 8is a top plan view of yet another flash memory array provided by embodiments of the invention;

[0040] Figure 9 is Figure 8 is a cross-sectional view along the D1-D2 direction;

[0041] Figure 10 is a top plan view of yet another flash memory array provided by embodiments of the invention;

[0042] Figure 11 is Figure 10 is a cross-sectional view along the E1-E2 direction;

[0043] Figure 12 is a top plan view of yet another flash memory array provided by embodiments of the invention;

[0044] Figure 13 is a top plan view of yet another flash memory array provided by embodiments of the invention;

[0045] Figure 14 is a top plan view of yet another flash memory array provided by embodiments of the invention. DETAILED DESCRIPTION

[0046] In order to make the persons skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without creative work should belong to the protection scope of the present application.

[0047] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the term "comprising" and any variation thereof is intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to the clearly listed steps or units, but can include other steps or units that are not clearly listed or inherent to the process, method, product or device.

[0048] Figure 1 is a cross-sectional view of a dummy flash memory cell in the prior art, as Figure 1As shown, the dummy flash memory cell includes a dummy drain 10, a dummy source 11, a dummy select gate 12, a dummy control gate 13, a dummy floating gate 14, a dummy silicide structure 15, and a dummy substrate 16. Due to process deviation, the size of the dummy drain 10 is small, so that the surface of the dummy drain 10 is insufficient to support the dummy silicide structure 15, thereby the dummy silicide structure 15 is short-circuited with the dummy substrate 16, resulting in more leakage from the dummy source 11 to the dummy substrate 16, so that the leakage current of the dummy flash memory cell is large, which interferes with the voltage of the storage and computing flash memory cell in programming, thereby affecting the programming ability or programming efficiency of the storage and computing flash memory cell.

[0049] To solve the above technical problems, the embodiment provides a flash memory array, Figure 2 is a top plan view of a flash memory array provided by the embodiment of the present application, Figure 3 is Figure 2 is a sectional view along the direction of A1-A2, referring to Figure 2 and Figure 3 The flash memory array includes a plurality of flash memory modules 100 arranged in an array; the flash memory module 100 includes one storage and computing unit 110 and at least one dummy unit 120; the storage and computing unit 110 and the dummy unit 120 are arranged alternately; the dummy unit 120 includes a first substrate 121, a first drain region 122, a first source region 123, and a first channel region 124 located in the first substrate 121, and a first select gate 125, a first control gate 126, and a first floating gate 127 located on the first substrate 121; wherein the first control gate 126 and the first floating gate 127 are located on a first side of the first select gate 125; the first drain region 122 is located on a second side of the first select gate 125 in the orthographic projection of the first substrate 121; the dummy unit 120 further includes a first silicide structure 128, the first silicide structure 128 is located on the surface of the first drain region 122 away from the first substrate 121, and the first silicide structure 128 is not connected with the first substrate 121.

[0050] The flash memory module 100 can include one memory and calculation unit 110 and one dummy unit 120, or one memory and calculation unit 110 and two dummy units 120 arranged on both sides of the memory and calculation unit 110. The memory and calculation unit 110 is a memory and calculation integrated flash memory unit, which can perform memory and calculation and programming operation. The dummy unit 120 does not perform memory and programming. By arranging the dummy unit 120, when the plurality of memory and calculation units 110 are segmented, the memory and calculation unit 110 can be prevented from being damaged, thereby achieving the effect of protecting the memory and calculation unit 110. The first substrate 121 has a supporting effect. By writing a higher voltage to the first source region 123 and a lower voltage to the first drain region 122, the electrons of the first drain region 122 move along the first channel region 124 to the first source region 123. By arranging the first silicide structure 128, the subsequent electrode can be easily led out to apply a voltage for corresponding operation.

[0051] Specifically, by arranging the first silicide structure 128 not connected with the first substrate 121, that is, ensuring that the first channel region 124 is not connected with the first substrate 121, the electrons will not leak from the first substrate 121 to the first source region 123 through the first silicide structure 128, thereby avoiding that the first source region 123 leaks too much to the first substrate 121, and further greatly reducing the leakage of the dummy unit 120, thereby avoiding the interference of the dummy unit 120 to the memory and calculation unit 110 being programmed, and improving the programming efficiency and accuracy of the memory and calculation unit 110.

[0052] For example, by arranging the first drain region 122 to have a larger size, the surface of the first drain region 122 can carry the first silicide structure 128, thereby ensuring that the first silicide structure 128 is not connected with the first substrate 121. Alternatively, the size of the first drain region 122 can be zero, that is, the first drain region 122 is a trench, the first channel region 124 is hidden below the first select gate 125, and no real drain region or first silicide structure is formed, and the size of the first silicide structure 128 is zero. The trench will not have electrons flowing from the first channel region 124 to the first source region 123, thereby avoiding the formation of a leakage current, and further greatly reducing the leakage of the dummy unit 120, thereby avoiding the interference of the dummy unit 120 to the memory and calculation unit 110 being programmed, and improving the programming efficiency and accuracy of the memory and calculation unit 110.

[0053] It should be noted that, Figure 2 and Figure 3 only the case that the size of the first drain region 122 is larger is shown, but it is not limited thereto. Moreover, Figure 3Only one case of the first silicide structure 128 is shown, and the specific structure of the first silicide structure 128 is not limited, as long as the first silicide structure 128 is not connected with the first substrate 121.

[0054] The technical scheme of the embodiment, by setting the first silicide structure of the dummy unit not connected with the first substrate, that is, ensuring that the first channel region of the dummy unit is not connected with the first substrate, so that electrons cannot leak from the first substrate to the first source region through the first silicide structure, thereby avoiding the first source region of the dummy unit from leaking more to the first substrate, and further greatly reducing the leakage of the dummy unit, thereby avoiding the interference of the dummy unit on the programming storage and computing unit, and improving the programming efficiency and accuracy of the storage and computing unit. The technical scheme of the embodiment solves the problem that the dummy unit affects the programming ability or efficiency of the storage and computing unit, and achieves the effect of improving the programming efficiency and accuracy of the storage and computing unit.

[0055] On the basis of the above technical scheme, Figure 4 is Figure 2 The cross-sectional view along the B1-B2 direction, optionally, referring to Figure 2 and Figure 4 The storage and computing unit 110 includes a second substrate 111, a second drain region 112, a second source region 113 and a second channel region 114 located in the second substrate 111, and a second selection gate 115, a second control gate 116 and a second floating gate 117 located on the second substrate 111; wherein the second control gate 116 and the second floating gate 117 are located on the first side of the second selection gate 115; the second drain region 112 is located on the second side of the second selection gate 115 in the second substrate 111.

[0056] Specifically, the second substrate 111 has a supporting effect. By writing a higher voltage to the second source region 113 and a lower voltage to the second drain region 112, the electrons of the second drain region 112 move along the second channel region 114 to the second source region 113, thereby forming a current. By writing a selected voltage to the second selection gate 115, the storage and computing unit 110 to be programmed can be selected, and the corresponding storage and computing unit 110 can be programmed. And, as Figure 4 The storage and computing unit 110 also includes a second silicide structure 118, which is located in the second drain region 112, and the second silicide structure 118 is located on the surface of the second drain region 112 away from the second substrate 111. By setting the second silicide structure 118, it is convenient to lead out the electrode for subsequent operation.

[0057] It should be noted that, referring to Figure 2In one flash memory module 100, the first select gate 125 and the second select gate 115 are integrated, the first control gate 126 and the second control gate 116 are integrated, and the first floating gate 127 and the second floating gate 117 are integrated.

[0058] On the basis of the above technical solutions, in order to ensure that the first silicide structure 128 is not connected with the first substrate 121, the size of the first drain region 122 can be set to be large, so that the surface of the first drain region 122 can carry the first silicide structure 128; or the size of the first drain region 122 can be set to be zero, that is, the first drain region 122 is a trench, so that no electrons flow from the first channel region 124 to the first source region 123, thereby no leakage current is formed, and the leakage of the dummy cell 120 is greatly reduced. The structure of the first drain region 122 will be further described below, but it is not intended to limit the present application.

[0059] In one embodiment, Figure 5 is a top view of another flash memory array provided by an embodiment of the present application, Figure 6 is Figure 5 is a sectional view along the C1-C2 direction. Optionally, reference is made to Figure 6 The size of the first drain region 122 is the same as that of the second drain region 112.

[0060] Specifically, by setting the size of the first drain region 122 to be the same as that of the second drain region 112, that is, the length of the first drain region 122 in the first direction X1 (the arrangement direction of the first select gate 125 and the first control gate 126) is the same as that of the second drain region 112, and the length of the first drain region 122 in the second direction X2 (the thickness direction of the first substrate 121, that is, the arrangement direction of the first control gate 126 and the first floating gate 127) is also the same. Therefore, the size of the first drain region 122 can be set to be large, and the size of the first drain region 122 in the first direction X1 can be large enough to carry the first silicide structure 128. The size of the first drain region 122 in the second direction X2 is large, that is, the depth of the first drain region 122 is large. In summary, by setting the size of the first drain region 122 to be the same as that of the second drain region 112, it can be ensured that the first silicide structure 128 is not connected with the first substrate 121, and thus the first channel region 124 is not connected with the first substrate 121, and no electrons leak from the first substrate 121 to the first source region 123 through the first silicide structure 128, thereby avoiding too much leakage from the first source region 123 to the first substrate 121, and greatly reducing the leakage of the dummy cell 120, thereby avoiding the interference of the dummy cell 120 with the programming of the computing cell 110, and improving the programming efficiency and accuracy of the computing cell 110.

[0061] Figure 7 is a circuit structure schematic diagram of a flash memory array provided by an embodiment of the present application. Optionally, referring to Figure 7 The flash memory array further includes a plurality of source lines; the source lines are connected to the sources of the storage and computing units 110 one by one; wherein, when the target storage and computing unit 110a is programmed, the source line SLm+1 adjacent to the target source line SLm is used to write a protection voltage to the corresponding storage and computing unit 110b; wherein, the target source line SLm is the source line corresponding to the target storage and computing unit 110a.

[0062] Specifically, the source of the storage and computing unit 110 is the second source region 113 of the storage and computing unit 110. When the size of the first drain region 122 is the same as that of the second drain region 112, the dummy unit 120 forms a complete first channel region 124, that is, the dummy unit 120 can generate a channel current. The selected target flash memory module includes a target storage and computing unit 110a and a target dummy unit 120 (not shown in the figure), and the flash memory module adjacent to the target flash memory module includes an adjacent storage and computing unit 110b and an adjacent dummy unit 120 (not shown in the figure), and the target dummy unit 120 is connected to the adjacent dummy unit 120. When the selected target storage and computing unit 110a is programmed, if the voltage on the adjacent source line SLm+1 is 0, that is, the source of the adjacent dummy unit 120 is 0, then the source of the adjacent dummy unit 120 and the source of the target dummy unit 120 form a voltage difference, the target dummy unit 120 generates a larger leakage current, changes the storage state of the target dummy unit 120, and then interferes with the programmed state of the target storage and computing unit 110a through the mode of capacitive coupling. Therefore, the adjacent source line SLm+1 of the target source line SLm writes a protection voltage Vinhibit, so that the target dummy unit 120 does not form a channel current, thereby avoiding the change of the state of the target dummy unit 120 to interfere with the target storage and computing unit 110a. Wherein, m is an integer greater than 0.

[0063] Further, the flash memory array also includes a plurality of control gate lines, a control gate line CGn-1 for writing a control voltage to the second control gate 116 of the memory and computing unit 110 of the n-1th row, a control gate line CGn for writing a control voltage to the second control gate 116 of the memory and computing unit 110 of the nth row, a control gate line CGn+1 for writing a control voltage to the second control gate 116 of the memory and computing unit 110 of the n+1th row, and a control gate line CGn+2 for writing a control voltage to the second control gate 116 of the memory and computing unit 110 of the n+2th row. Wherein n is an integer greater than 1. The flash memory array also includes a plurality of select gate lines, a select gate line WLBn-1 for writing a selected voltage to the second select gate 115 of the memory and computing unit 110 of the even row in the n-1th column, a select gate line WLTn-1 for writing a selected voltage to the second select gate 115 of the memory and computing unit 110 of the odd row in the n-1th column, a select gate line WLBn for writing a selected voltage to the second select gate 115 of the memory and computing unit 110 of the even row in the nth column, a select gate line WLTn for writing a selected voltage to the second select gate 115 of the memory and computing unit 110 of the odd row in the nth column, a select gate line WLBn+1 for writing a selected voltage to the second select gate 115 of the memory and computing unit 110 of the even row in the n+1th column, and a select gate line WLTn+1 for writing a selected voltage to the second select gate 115 of the memory and computing unit 110 of the odd row in the n+1th column.

[0064] In another embodiment, Figure 8 is a top plan view of yet another flash memory array provided by an embodiment of the present application, Figure 9 is Figure 8 is a sectional view along the D1-D2 direction. Optionally, reference is made to Figure 8 and Figure 9 The first drain region 122 is a shallow trench 122a.

[0065] Specifically, by setting the first drain region 122 as a shallow trench 122a, no real drain is formed, and no first silicide structure is formed, and the size of the first silicide structure 128 is zero; the trench 122a will not have electrons flowing from the first channel region 124 to the first source region 123, so as to not form a leakage current, thereby greatly reducing the leakage of the dummy cell 120, so as to avoid the dummy cell 120 from interfering with the memory and computing unit 110 being programmed, and improve the programming efficiency and accuracy of the memory and computing unit 110.

[0066] Optionally, reference is made to Figure 8 and Figure 9The first selection gate 125 includes a first part 125a overlapping the first channel region 124 in the orthographic projection of the first substrate 121 and a second part 125b exposed to the first channel region 124. The length d1 of the first part 125a is greater than a first preset length. The preset length is half of the width d of the first selection gate 125. The length d1 of the first part 125a and the width of the first selection gate 125 are dimensions in the first direction X1, and the first direction X1 is a direction in which the first side of the first selection gate 125 points to the second side thereof. The width d2 of the second part 125b is greater than a process deviation value.

[0067] Specifically, by setting the width d2 of the second part 125b of the first selection gate 125 to be greater than the process deviation value, it can be ensured that the first channel region 124 is located below the first selection gate 125, avoiding the process deviation from causing the first channel region 124 to extend below the first selection gate 125, so as to ensure that no real drain is formed, thereby ensuring that the first drain region 122 is a shallow trench 122a, and the trench 122a will not have electrons flowing from the first channel region 124 to the first source region 123, so as to avoid forming a leakage current, and further greatly reducing the leakage of the dummy cell 120. By setting the length d1 of the first part 125a of the first selection gate 125 to be greater than the first preset length, it can be ensured that the first channel region 124 will not be too small. If the first channel region 124 is too small, it will affect the channel environment and affect the performance of the in-memory computing unit 110, such as electron mobility and threshold voltage.

[0068] In another embodiment, Figure 10 is a top-down plan view of another flash memory array provided by an embodiment of the present application, Figure 11 is a top-down plan view of another flash memory array provided by an embodiment of the present application, Figure 10 is a cross-sectional view along the E1-E2 direction. Optionally, reference is made to Figure 10 and Figure 11 The dummy cell 120 further includes a first spacer 129 located at the second side of the first selection gate 125. The length d3 of the first drain region 122 in the first direction X1 is greater than a second preset length, and the length difference d4 between the first drain region 122 and the second drain region 112 in the first direction X1 is greater than a third preset length. The first direction X1 is a direction in which the first side of the first selection gate points to the second side thereof. The second preset length is the sum of the length of the first spacer 129 in the first direction X1 and a process deviation value. The third preset length is half of a lithography pitch.

[0069] Specifically, the first spacer 129 has an electrically insulating effect, a spacer can also be arranged between the first select gate 125 and the first floating gate 127, and a spacer can also be arranged between the first select gate 125 and the first control gate 126 to avoid voltage crosstalk. By setting the length d3 of the first drain region 122 in the first direction X1 to be greater than the second preset length, the second preset length being the sum of the length of the first spacer 129 in the first direction X1 and a process deviation value, it is ensured that the size of the first drain region 122 is relatively large, the first drain region 122 extends beyond the first spacer 129, so that the first drain region 122 is sufficient to carry the first silicide structure 128, so that the first silicide structure 128 is not connected to the first substrate 121, that is, it is ensured that the first channel region 124 is not connected to the first substrate 121, so that electrons cannot leak from the first substrate 121 to the first source region 123 through the first silicide structure 128, thereby avoiding too much leakage of the first source region 123 to the first substrate 121, and further greatly reducing the leakage of the dummy cell 120, thereby avoiding interference of the dummy cell 120 with the storage and computing cell 110 being programmed, and improving the programming efficiency and accuracy of the storage and computing cell 110.

[0070] Furthermore, the length difference d4 of the second drain region 112 and the first drain region 122 in the first direction X1 is greater than a third preset length, and the third preset length is one-half of the photolithography pitch, so that in the first direction X1, the length difference of the second drain region 112 and the first drain region 122 in the first direction X1 is greater than the photolithography pitch, thereby meeting the photolithography requirement for the first drain region 122 and ensuring that the photolithography process can proceed normally.

[0071] In summary, by setting the size of the first drain region 122 to be the same as that of the second drain region 112, or setting the length d3 of the first drain region 122 in the first direction X1 to be greater than the second preset length, and the length difference d4 of the second drain region 112 and the first drain region 122 in the first direction X1 to be greater than the third preset length, or setting the first drain region 122 to be a shallow trench 122a, it is ensured that the first silicide structure 128 is not connected to the first substrate 121, that is, it is ensured that the first channel region 124 is not connected to the first substrate 121, so that electrons cannot leak from the first substrate 121 to the first source region 123 through the first silicide structure 128, thereby avoiding too much leakage of the first source region 123 to the first substrate 121, and further greatly reducing the leakage of the dummy cell 120, thereby avoiding interference of the dummy cell 120 with the storage and computing cell 110 being programmed, and improving the programming efficiency and accuracy of the storage and computing cell 110.

[0072] As a further implementation of the embodiment, on the basis of each of the above technical solutions, optionally, in one flash memory module 100, the first select gate 125 of the dummy cell 120 and the second select gate 115 of the storage and computing cell 110 are integrated as one select gate; the select gates between adjacent two flash memory modules 100 are not connected.

[0073] Specifically, the select gates between adjacent two flash memory modules 100 are not connected, so that any one of the flash memory modules 100 can be selected individually, that is, the programming operation can be performed on any one of the storage and computing cells 110 without interference to the adjacent storage and computing cells 110.

[0074] Figure 12 is a top-down plan view of another flash memory array provided by an embodiment of the application, Figure 13 is a top-down plan view of another flash memory array provided by an embodiment of the application, Figure 14 is a top-down plan view of another flash memory array provided by an embodiment of the application, optionally, referring to Figure 12 、 Figure 13 and Figure 14 , the dummy cell 120 further includes a first erase gate 130; the first erase gate 130 is located on the first source region 123, and the first erase gate 130 is located on the side of the first control gate 126 away from the first select gate 125; the storage and computing cell 110 includes a second substrate 111, a second drain region 112, a second source region 113 and a second channel region 114 located in the second substrate 111, and a second select gate 115, a second control gate 116, a second floating gate 117 and a second erase gate 119 located on the second substrate 111; wherein the orthographic projection of the second control gate 116 and the second floating gate 117 on the second substrate 111 is located on the first side of the orthographic projection of the second select gate 115 on the second substrate 111; the orthographic projection of the second drain region 112 on the second substrate 111 is located on the second side of the orthographic projection of the second select gate 115 on the second substrate 111; the second erase gate 119 is located on the side of the second control gate 116 away from the second select gate 115, and the second erase gate 119 is located on the second source region 113.

[0075] Specifically, by setting the first erase gate 130 and the second erase gate 119, writing an erase voltage to the first erase gate 130 and the second erase gate 119, an erase operation is performed on the corresponding storage and computing cell 110.

[0076] Optionally, referring to Figure 12 、 Figure 13 and Figure 14 , in one flash memory module, the first erase gate 130 and the second erase gate 119 are integrated as one erase gate; the erase gates between adjacent two flash memory modules 100 are not connected.

[0077] Specifically, the erase gates between two adjacent flash memory modules 100 are not connected, thus allowing individual erase operations to be performed on any one memory cell 110 without interfering with adjacent memory cells 110. For example... Figure 12 As shown, by setting the first drain region 122 and the second drain region 112 to have the same size, it can be ensured that the first silicide structure 128 will not connect to the first substrate 121, thereby ensuring that the first channel region 124 will not connect to the first substrate 121. Electrons will not leak from the first substrate 121 through the first silicide structure 128 to the first source region 123, thus avoiding excessive leakage from the first source region 123 to the first substrate 121. This significantly reduces the leakage current of the dummy unit 120, thereby preventing the dummy unit 120 from interfering with the in-memory unit 110 being programmed, and improving the programming efficiency and accuracy of the in-memory unit 110. Figure 13 As shown, by setting the width d2 of the second portion 125b of the first selection gate 125 to be greater than the process deviation value, it can be ensured that the first channel region 124 is located below the first selection gate 125, avoiding process deviations that cause the first channel region 124 to extend below the first selection gate 125, thus preventing the formation of a true drain. No electrons will flow from the first channel region 124 to the first source region 123 in the trench 122a, thereby significantly reducing leakage current in the dummy cell 120. By setting the length d1 of the first portion 125a of the first selection gate 125 to be greater than the first preset length, it can be ensured that the first channel region 124 is not too small. If the first channel region 124 is too small, it will affect the channel environment and the performance of the memory cell 110, such as electron mobility and threshold voltage. Figure 14 As shown, by setting the length d3 of the first drain region 122 in the first direction X1 to be greater than the second preset length, where the second preset length is the sum of the length of the first spacer 129 in the first direction X1 and the process deviation value, the size of the first drain region 122 is ensured to be larger, and the first drain region 122 extends beyond the first spacer 129. This ensures that the first drain region 122 is sufficient to support the first silicide structure 128, so that the first silicide structure 128 is not connected to the first substrate 121. In other words, it ensures that the first channel region 124 is not connected to the first substrate 121, and electrons will not leak from the first substrate 121 through the first silicide structure 128 to the first source region 123. This avoids excessive leakage from the first source region 123 to the first substrate 121, thereby significantly reducing the leakage current of the dummy unit 120. This prevents the dummy unit 120 from interfering with the programmed memory unit 110, and improves the programming efficiency and accuracy of the memory unit 110.

[0078] The technical scheme of the embodiment also provides a flash memory chip, which comprises the flash memory array provided by any of the implementation solutions.

[0079] The specific implementation described above does not constitute a limitation on the protection scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A flash memory array, characterized in that, It includes multiple flash memory modules arranged in an array; each flash memory module includes a storage unit and at least one virtual unit; The stored computing units and the virtual units are arranged alternately. The virtual units are not stored or programmed and are located between the two stored computing units. The dummy unit includes a first substrate, a first drain region, a first source region and a first channel region located within the first substrate, and a first select gate, a first control gate and a first floating gate located on the first substrate; wherein the first control gate and the first floating gate are located on a first side of the first select gate; the orthographic projection of the first drain region onto the first substrate is located on a second side of the orthographic projection of the first select gate onto the first substrate. The dummy unit further includes a first silicide structure, which is located on the surface of the first drain region away from the first substrate, and the first silicide structure is not connected to the first substrate.

2. The flash memory array according to claim 1, characterized in that, The memory cell includes a second substrate, a second drain region, a second source region and a second channel region located within the second substrate, and a second selection gate, a second control gate and a second floating gate located on the second substrate; wherein the second control gate and the second floating gate are located on a first side of the second selection gate; the orthographic projection of the second drain region onto the second substrate is located on a second side of the orthographic projection of the second selection gate onto the second substrate; The first drain region has the same size as the second drain region.

3. The flash memory array according to claim 2, characterized in that, It also includes multiple source lines; The multiple source lines are respectively connected one-to-one with the source of the multiple rows of memory computing units in the multiple flash memory modules; wherein, when programming the target memory computing unit, the source lines adjacent to the target source line are used to write a protection voltage to the corresponding memory computing unit; wherein, the target source line is the source line corresponding to the target memory computing unit.

4. The flash memory array according to claim 1, characterized in that, The memory cell includes a second substrate, a second drain region, a second source region and a second channel region located within the second substrate, and a second selection gate, a second control gate and a second floating gate located on the second substrate; wherein the second control gate and the second floating gate are located on a first side of the second selection gate; the orthographic projection of the second drain region onto the second substrate is located on a second side of the orthographic projection of the second selection gate onto the second substrate; The dummy unit further includes a first spacer, which is located on the second side of the first selection gate; The length of the first drain region in the first direction is greater than the second preset length, and the length difference between the second drain region and the first drain region in the first direction is greater than the third preset length; wherein, the first direction is the direction from the first side of the first selected gate to its second side; the second preset length is the sum of the length of the first spacer in the first direction and the process deviation value, and the third preset length is half of the photolithographic spacing.

5. The flash memory array according to any one of claims 1-4, characterized in that, In one of the flash memory modules, the first selection gate of the dummy unit and the second selection gate of the memory unit are an integrated selection gate; The select gates between two adjacent flash memory modules are not connected.

6. The flash memory array according to any one of claims 1-4, characterized in that, The dummy unit also includes a first erase gate; The first erase gate is located on the first source region, and the first erase gate is located on the side of the first control gate away from the first select gate; The memory cell includes a second substrate, a second drain region, a second source region and a second channel region located within the second substrate, and a second select gate, a second control gate, a second floating gate and a second erase gate located on the second substrate; wherein the orthographic projections of the second control gate and the second floating gate onto the second substrate are located on the first side of the orthographic projection of the second select gate onto the second substrate. The second drain region is projected onto the second substrate on the second side of the second selection gate's projection onto the second substrate; the second erase gate is located on the side of the second control gate away from the second selection gate, and the second erase gate is located on the second source region.

7. The flash memory array according to claim 6, characterized in that, In one of the flash memory modules, the first erase gate and the second erase gate are an integral erase gate; The erase gates between two adjacent flash memory modules are not connected.

8. A flash memory chip, characterized in that, Includes the flash memory array as described in any one of claims 1-7.

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