Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a display area and a frame area. The display area includes a driving structure layer and a first light-emitting structure layer. The first light-emitting structure layer includes a plurality of first light-emitting devices. The frame area includes a circuit structure layer and a second light-emitting structure layer. The second light-emitting structure layer includes a plurality of second light-emitting devices. The driving structure layer includes a plurality of circuit units. Each circuit unit includes a first pixel driving circuit and a second pixel driving circuit. The first light-emitting devices are connected to the first pixel driving circuits. The second light-emitting devices are connected to the second pixel driving circuits. The present disclosure sets light-emitting devices in the frame area, so that part of the frame area is used for display. The display area of the display device is effectively increased, the area of the non-display area of the display device is correspondingly reduced, the frame width of the display device is maximally reduced, and narrow frame of the display device is achieved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a preparation method thereof, and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] With the development of display technology, consumers have increasingly high requirements for the display effect of display products, and extremely narrow frame has become a new trend in the development of display products. Therefore, frame narrowing is a technical problem to be solved in the field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the exemplary embodiments of the present disclosure is to provide a display substrate, a preparation method thereof, and a display device to realize narrow frame of the display device.

[0006] The present disclosure provides a display substrate, comprising a display area and a frame area located at least one side of the display area; in a plane perpendicular to the display substrate, the display area comprises a driving structure layer disposed on a substrate and a first light emitting structure layer disposed on a side of the driving structure layer away from the substrate, the first light emitting structure layer comprising a plurality of first light emitting devices; the frame area comprises a circuit structure layer disposed on a substrate and a second light emitting structure layer disposed on a side of the circuit structure layer away from the substrate, the second light emitting structure layer comprising a plurality of second light emitting devices; the driving structure layer comprises a plurality of circuit units, at least one circuit unit comprising a first pixel driving circuit and a second pixel driving circuit, the first light emitting device being connected to the first pixel driving circuit, and the second light emitting device being connected to the second pixel driving circuit.

[0007] In an exemplary embodiment, along a direction away from the display area, the frame area comprises a circuit region, a cathode overlap region, a partition region, and a cutting region arranged in sequence, and the second light emitting structure layer is disposed in the circuit region.

[0008] In an example embodiment, the display area includes a normal driving area and a combined driving area, the combined driving area is arranged between the normal driving area and the frame area, the circuit unit of the normal driving area includes a first pixel driving circuit, and the circuit unit of the combined driving area includes the first pixel driving circuit and a second pixel driving circuit.

[0009] In an example embodiment, the first light emitting device includes a first pixel opening defining a light emitting area, and the second light emitting device includes a second pixel opening defining a light emitting area; a distance between adjacent second pixel openings in the frame area is greater than or equal to a distance between adjacent first pixel openings in the display area, the distance being a distance between centers of the pixel openings, the center of the pixel opening being a geometric center of the pixel opening.

[0010] In an example embodiment, in the frame area, the distance between adjacent second pixel openings gradually increases in a direction away from the display area.

[0011] In an example embodiment, the first light emitting device includes a first pixel opening defining a light emitting area, and the second light emitting device includes a second pixel opening defining a light emitting area; an area of the second pixel opening in the frame area is less than or equal to an area of the first pixel opening in the display area.

[0012] In an example embodiment, in the frame area, the area of the second pixel opening gradually decreases in a direction away from the display area.

[0013] In an example embodiment, the second light emitting device of the frame area is connected to the second pixel driving circuit of the display area through an anode connection line.

[0014] In an example embodiment, the circuit structure layer of the frame area includes at least a first source-drain metal layer and a second source-drain metal layer, and the anode connection line is arranged in the second source-drain metal layer.

[0015] In an example embodiment, the circuit structure layer of the frame area includes at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, and the anode connection line is arranged in the third source-drain metal layer.

[0016] In an example embodiment, the circuit structure layer of the frame area includes at least a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, and the anode connection line includes a first anode connection line and a second anode connection line, the first anode connection line is arranged in the second source-drain metal layer, and the second anode connection line is arranged in the third source-drain metal layer.

[0017] In an example embodiment, the second light-emitting structure layer of the frame region comprises, in sequence on the circuit structure layer, an anode conductive layer, a pixel definition layer, an organic light-emitting layer, and a cathode; the anode conductive layer comprises a cathode overlap electrode and at least one second anode, the cathode overlap electrode is provided with a hollow area, and the at least one second anode is arranged in the hollow area; the pixel definition layer is provided with a second pixel opening and a connection opening, the second pixel opening exposes the second anode, and the connection opening exposes the cathode overlap electrode; the organic light-emitting layer is connected with the second anode through the second pixel opening, the cathode is connected with the organic light-emitting layer, and the cathode is connected with the cathode overlap electrode through the connection opening.

[0018] The present disclosure also provides a display device comprising the aforementioned display substrate.

[0019] The present disclosure also provides a preparation method of a display substrate, the display substrate comprising a display region and a frame region located at least one side of the display region; the preparation method comprising:

[0020] forming a driving structure layer and a circuit structure layer in the display region and the frame region respectively; the driving structure layer comprises a plurality of circuit units, and at least one circuit unit comprises a first pixel driving circuit and a second pixel driving circuit;

[0021] forming a first light-emitting structure layer and a second light-emitting structure layer in the display region and the frame region respectively; the first light-emitting structure layer comprises a plurality of first light-emitting devices, and the second light-emitting structure layer comprises a plurality of second light-emitting devices, the first light-emitting devices are connected with the first pixel driving circuit, and the second light-emitting devices are connected with the second pixel driving circuit.

[0022] The present disclosure provides a display substrate and a preparation method thereof, and a display device, by arranging light-emitting devices in the frame region, part of the frame region is enabled to display, the display area of the display device is effectively increased, the area of the non-display region of the display device is correspondingly reduced, the frame width of the display device is maximally reduced, the frame width can be reduced to about 0.3mm to 0.4mm, and narrow frame of the display device is achieved.

[0023] Other aspects can become apparent after consideration of the drawing and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0025] Figure 1 A structural schematic diagram of a display device;

[0026] Figure 2 A structural schematic diagram of a display substrate;

[0027] Figure 3 A structural schematic diagram of a display area in a display substrate;

[0028] Figure 4 An equivalent circuit schematic diagram of a pixel driving circuit;

[0029] Figure 5 A working timing diagram of a pixel driving circuit;

[0030] Figure 6 A structural schematic diagram of a frame area according to an example embodiment of the present disclosure;

[0031] Figure 7 A structural schematic diagram of a combined driving area according to an example embodiment of the present disclosure;

[0032] Figure 8 A schematic diagram of a connection of a light emitting device in a circuit area according to an example embodiment of the present disclosure;

[0033] Figure 9 A structural schematic diagram of a display substrate according to an example embodiment of the present disclosure;

[0034] Figure 10 A schematic diagram after forming a transistor structure layer pattern according to an example embodiment of the present disclosure;

[0035] Figure 11 A schematic diagram after forming a first planar layer pattern according to an example embodiment of the present disclosure;

[0036] Figure 12 A schematic diagram after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0037] Figure 13 A schematic diagram after forming a second planar layer pattern according to an example embodiment of the present disclosure;

[0038] Figure 14 A schematic diagram after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0039] Figure 15 A schematic diagram after forming a third planar layer pattern according to an example embodiment of the present disclosure;

[0040] Figure 16 A schematic diagram after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0041] Figure 17 A schematic diagram of a planar structure of a cathode overlap electrode in a circuit region according to an embodiment of the present disclosure;

[0042] Figure 18 A schematic diagram after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0043] Figure 19 A schematic diagram after forming a partition structure layer pattern according to an exemplary embodiment of the present disclosure;

[0044] Figure 20 A schematic diagram after forming an organic light-emitting layer pattern according to an exemplary embodiment of the present disclosure;

[0045] Figure 21 A schematic diagram after forming a cathode pattern according to an exemplary embodiment of the present disclosure;

[0046] Figure 22 A schematic diagram after forming an encapsulation structure layer pattern according to an exemplary embodiment of the present disclosure.

[0047] BRIEF DESCRIPTION OF THE DRAWINGS

[0048] 10 - substrate; 11 - first insulating layer; 12 - second insulating layer;

[0049] 13 - third insulating layer; 14 - fourth insulating layer; 15 - fifth insulating layer;

[0050] 16 - first planar layer; 17 - second planar layer; 18 - third planar layer;

[0051] 21 - first anode; 22 - second anode; 23 - cathode overlap electrode;

[0052] 24 - pixel definition layer; 25 - organic light-emitting layer; 26 - cathode;

[0053] 31 - first encapsulation layer; 32 - second encapsulation layer; 33 - third encapsulation layer.

[0054] 41 - organic layer; 42 - inorganic layer; 50 - power supply line;

[0055] 51 - first cathode electrode; 52 - second cathode electrode; 61 - first connection electrode;

[0056] 62 - second connection electrode; 71 - first transition electrode; 72 - second transition electrode;

[0057] 81 - first anode connection line; 82 - second anode connection line; 90 - isolation dam;

[0058] 91 - first partition structure; 92 - second partition structure; 93 - third partition structure;

[0059] 100 - display area; 110 - normally driven area; 120 - combined driven area;

[0060] 200 - frame area; 210 - circuit area; 220 - cathode overlap area;

[0061] 230 - partition area; 240 - cutting area; 300 - binding area. DETAILED DESCRIPTION

[0062] For the purpose of making the purpose, technical solutions and advantages of the present disclosure clearer, the following will describe the embodiments of the present disclosure in detail with reference to the drawings. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the means and content can be changed into various forms without departing from the purpose of the present disclosure and the scope thereof. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0063] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and interval of each film layer, and the width and interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0064] The ordinal numbers "first", "second", "third" and the like in the present specification are set in order to avoid confusion of the components, and are not intended to be limiting in terms of numbers.

[0065] In the present specification, for the convenience of description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0066] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, can be fixedly connected, or detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected via an intervening member, or communication between two elements inside. The specific meaning of the above terms in the present disclosure can be understood in light of the specific circumstances for those skilled in the art.

[0067] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0068] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged, and the "source terminal" and the "drain terminal" can be interchanged.

[0069] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having a variety of functions.

[0070] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0071] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0072] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly defined, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. There can be some small deformations due to tolerances, there can be lead angles, arc edges, and deformations, etc.

[0073] In the present disclosure, "about" means not strictly limited to the boundary, allowing values within the range of process and measurement errors.

[0074] Figure 1 A structural schematic diagram of a display device. As shown in FIG. 1, the display device includes a display panel 100, a backlight unit 200, and a frame 300. Figure 1As shown, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit can include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, o can be a natural number.

[0075] Figure 2 FIG. 1 is a schematic view of a planar structure of a display substrate. Figure 2As shown, in an example embodiment, the display substrate can include a display area 100 and an edge area located outside the display area 100, the edge area can include a binding area 300 located at one side of the display area 100 and a frame area 200 located at other sides of the display area 100. In an example embodiment, the display area 100 can include a plurality of sub-pixels arranged in a matrix manner, the sub-pixel can include a circuit unit and a light-emitting device, the frame area 200 can at least include an isolation dam, a gate driving circuit (Gate Driver on Array, referred to as GOA) for transmitting a scanning signal and a light-emitting signal to the circuit unit of the plurality of sub-pixels, and a power line for transmitting a voltage signal to the plurality of sub-pixels, the binding area 300 can at least include an isolation dam and a binding circuit for connecting the signal line of the plurality of sub-pixels to an external driving device, and the isolation dam of the frame area 200 and the binding area 300 forms an annular structure surrounding the display area 100.

[0076] Figure 3 A schematic diagram of a planar structure of a display area in a display substrate is shown. In an example embodiment, the display area can include a plurality of pixel units P arranged in a matrix manner, at least one pixel unit P can include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light. At least one sub-pixel can include a circuit unit and a light-emitting device, the circuit unit can include a scanning signal line, a data signal line, a light-emitting signal line, and a pixel driving circuit, the pixel driving circuit can be connected to the scanning signal line, the data signal line, and the light-emitting signal line respectively, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device, the light-emitting device is connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0077] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) emitting green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in a diamond shape. In other example embodiments, the four sub-pixels can be arranged in a square shape, horizontally side by side, or vertically side by side, etc. In an example embodiment, the pixel unit can include three sub-pixels, which can be arranged in a horizontal side-by-side, vertical side-by-side, or triangular shape, etc., which is not limited in the present disclosure.

[0078] In an example embodiment, a plurality of sub-pixels arranged in a horizontal direction in sequence are referred to as a pixel row, a plurality of sub-pixels arranged in a vertical direction in sequence are referred to as a pixel column, and the plurality of pixel rows and the plurality of pixel columns form a pixel array arranged in an array.

[0079] Figure 4 Fig. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be of a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. As shown in Fig. 1, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, emission signal line E, initial signal line INIT, first power supply line VDD and second power supply line VSS). Figure 4

[0080] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2 and a third node N3. The first node N1 is connected to a first electrode of the third transistor T3, a second electrode of the fourth transistor T4 and a second electrode of the fifth transistor T5, respectively. The second node N2 is connected to a second electrode of the first transistor, a first electrode of the second transistor T2, a control electrode of the third transistor T3 and a second terminal of the storage capacitor C, respectively. The third node N3 is connected to a second electrode of the second transistor T2, a second electrode of the third transistor T3 and a first electrode of the sixth transistor T6, respectively.

[0081] In an example embodiment, a first terminal of the storage capacitor C is connected to the first power supply line VDD, and a second terminal of the storage capacitor C is connected to the second node N2, i.e., the second terminal of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0082] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits an initial voltage to the control electrode of the third transistor T3, so as to initialize the charge amount of the control electrode of the third transistor T3.

[0083] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3.

[0084] ​The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a drive transistor, and the third transistor T3 determines the amount of drive current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between the control electrode and the first electrode thereof.

[0085] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, or the like, and the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit when an on-level scan signal is applied to the first scan signal line S1.

[0086] The control electrode of the fifth transistor T5 is connected to the emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. The fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS when an on-level emission signal is applied to the emission signal line E.

[0087] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. The seventh transistor T7 transmits an initial voltage to the first electrode of the light emitting device to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device when an on-level scan signal is applied to the first scan signal line S1.

[0088] In the exemplary embodiment, the light emitting device can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0089] In the example embodiment, the second electrode of the light-emitting device is connected to a second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a high-level signal continuously provided. The first scan signal line S1 is a scan signal line in the pixel driving circuit of the current display row, and the second scan signal line S2 is a scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the current display row and the first scan signal line S1 of the previous display row are the same signal line, which can reduce the signal lines of the display panel and achieve a narrow frame of the display panel.

[0090] In the example embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0091] In the example embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon thin film transistors or can be oxide thin film transistors or can be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin film transistor and the oxide thin film transistor on one display substrate forms a low-temperature polysilicon oxide (LTPO) display substrate, which can take advantage of both and can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0092] Figure 5 FIG. 1 is a timing diagram of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 4 The working process of the example pixel driving circuit is used to illustrate the example embodiment of the present disclosure. Figure 4 The pixel driving circuit in FIG. 1 includes seven transistors (the first transistor T1 to the seventh transistor T7) and one storage capacitor C, and the seven transistors are P-type transistors.

[0093] In the example embodiment, taking an OLED as an example, the working process of the pixel driving circuit can include:

[0094] The first stage A1, referred to as a reset stage, the signal of the second scan signal line S2 is a low signal, and the signals of the first scan signal line S1 and the emitting signal line E are high signals. The signal of the second scan signal line S2 is a low signal, so that the first transistor T1 is turned on, and the signal of the initial signal line INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The signals of the first scan signal line S1 and the emitting signal line E are high signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0095] The second stage A2, referred to as a data writing stage or threshold compensation stage, the signal of the first scan signal line S1 is a low signal, the signals of the second scan signal line S2 and the emitting signal line E are high signals, and the data signal line D outputs a data voltage. In this stage, the second end of the storage capacitor C is low, so that the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage in the first electrode is emptied, the initialization is completed, and it is ensured that the OLED does not emit light. The signal of the second scan signal line S2 is a high signal, so that the first transistor T1 is turned off. The signal of the emitting signal line E is a high signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.

[0096] The third stage A3, referred to as an emitting stage, the signal of the emitting signal line E is a low signal, and the signals of the first scan signal line S1 and the second scan signal line S2 are high signals. The signal of the emitting signal line E is a low signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD is provided to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the OLED to emit light.

[0097] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0098] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0099] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power voltage output by the first power supply line VDD.

[0100] At present, with the gradual increase of the resolution of display devices, and in order to ensure the reliability and functionality of the frame area, the frame width of the existing display device is about 1 mm. The resolution (Pixels Per Inch, referred to as PPI) refers to the number of pixels per unit area, which can be referred to as pixel density. The higher the PPI value, the higher the density at which the display substrate can display the picture, and the more detailed the picture. Since the increase of the resolution not only needs to increase the number of gate driving circuits in the frame area, thereby increasing the occupied area of the gate driving circuit, but also needs to increase the width of the power supply line in the frame area to reduce the impedance and voltage drop of the power supply line, so as to ensure the display brightness uniformity, it is very difficult to reduce the frame by reducing the occupied area of the gate driving circuit and the power supply line.

[0101] In order to effectively reduce the frame width of the display device and realize the narrow frame of the display device, the display substrate is provided in the example embodiments of the present disclosure. In the example embodiments, the display substrate can include a display area and a frame area located at least one side of the display area. In a plane perpendicular to the display substrate, the display area can include a driving structure layer disposed on a substrate and a first light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, and the first light-emitting structure layer can include a plurality of first light-emitting devices; the frame area can include a circuit structure layer disposed on a substrate and a second light-emitting structure layer disposed on a side of the circuit structure layer away from the substrate, and the second light-emitting structure layer can include a plurality of second light-emitting devices. The driving structure layer can include a plurality of circuit units, at least one circuit unit can include a first pixel driving circuit and a second pixel driving circuit, the first light-emitting device is connected with the first pixel driving circuit, and the second light-emitting device is connected with the second pixel driving circuit.

[0102] Figure 6 A schematic view of a planar structure of a frame region for an exemplary embodiment of the present disclosure is shown in FIG. 1. A magnified view of a C region in FIG. 1 is shown in FIG. 2. As shown in FIG. 2, in a plane parallel to a display substrate, the display substrate can include a display region 100 and a frame region 200 located at least one side of the display region 100, the display region 100 can include a normal driving area 110 and a combined driving area 120 located between the normal driving area 110 and the frame region 200, and the frame region 200 can include a circuit area 210, a cathode overlap area 220, a partition area 230, and a cutting area 240 arranged in sequence along a direction away from the display region. Figure 2 Figure 6

[0103] In an exemplary embodiment, the normal driving area 110 can include a plurality of circuit units and a plurality of first light emitting devices, each of the circuit units is provided with a first pixel driving circuit, the plurality of first light emitting devices are connected to the first pixel driving circuits in the plurality of circuit units in correspondence, and the first pixel driving circuit is configured to output a current to the connected first light emitting device to make the first light emitting device emit light with a corresponding brightness.

[0104] In an exemplary embodiment, the combined driving area 120 can include a plurality of circuit units and a plurality of first light emitting devices, each of the circuit units is provided with a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuits in the plurality of circuit units are connected to the plurality of first light emitting devices located in the combined driving area 120 in correspondence, and the first pixel driving circuit is configured to output a current to the connected first light emitting device to make the first light emitting device emit light with a corresponding brightness. The second pixel driving circuits in the plurality of circuit units are connected to the plurality of second light emitting devices located in the circuit area 210 in correspondence, and the second pixel driving circuit is configured to output a current to the connected second light emitting device to make the second light emitting device emit light with a corresponding brightness.

[0105] In an exemplary embodiment, the circuit area 210 can include at least a gate driving circuit and a plurality of second light emitting devices, the gate driving circuit can be connected to the plurality of circuit units of the display region 100 to output a scanning signal and a light emitting control signal to the plurality of circuit units, the plurality of second light emitting devices are connected to the second pixel driving circuits in the plurality of circuit units located in the combined driving area 120 in correspondence, and the plurality of second light emitting devices are configured to emit light with a corresponding brightness in response to the current output by the connected second pixel driving circuit.

[0106] ​​In an example embodiment, the cathode overlap region 220 can include at least a power line, an isolation dam, and a first partition structure, the power line can extend along a direction parallel to the display region edge, the power line can be connected with a second power line VSS of the circuit units in the display region, the isolation dam can extend along a direction parallel to the display region edge, the isolation dam is configured to block the organic layer in the encapsulation layer from flowing to the cutting region, and the first partition structure can extend along a direction parallel to the display region edge, the first partition structure is configured to isolate the water and oxygen from the cutting region. In the present disclosure, the display region edge refers to the edge of the display region 100 close to the frame region 200.

[0107] In an example embodiment, the partition region 230 can include at least a second partition structure, the second partition structure can extend along a direction parallel to the display region edge, and the second partition structure is configured to isolate the water and oxygen from the cutting region and avoid the cutting process affecting the film layer structure of the display substrate.

[0108] In an example embodiment, the cutting region 240 can include at least a cutting groove disposed on the composite insulating layer and a third partition structure disposed in the cutting groove, the cutting groove and the third partition structure can extend along a direction parallel to the display region edge, the cutting groove is configured to make the cutting equipment cut along the cutting groove after all the film layers are prepared, and the third partition structure is configured to avoid the cutting process affecting the film layer structure of the display substrate.

[0109] In an example embodiment, in a plane perpendicular to the display substrate, the display region 100 can include a driving structure layer disposed on the substrate and a first light emitting structure layer disposed on a side of the driving structure layer away from the substrate, the plurality of circuit units are located in the driving structure layer, and a plurality of first light emitting devices are located in the first light emitting structure layer.

[0110] In an example embodiment, in a plane perpendicular to the display substrate, the circuit region 210 can include a circuit structure layer disposed on the substrate and a second light emitting structure layer disposed on a side of the circuit structure layer away from the substrate, the circuit structure layer can include a plurality of shift registers constituting a gate driving circuit, and a plurality of second light emitting devices are located in the second light emitting structure layer.

[0111] In an example embodiment, in a plane perpendicular to the display substrate, the cathode overlap region 220, the partition region 230, and the cutting region 240 can include a frame structure layer disposed on the substrate. The frame structure layer of the cathode overlap region 220 can include at least a power line, an isolation dam, and a first partition structure, the frame structure layer of the partition region 230 can include at least a second partition structure disposed on the composite insulating layer, and the frame structure layer of the cutting region 240 can include at least a composite insulating layer with a cutting groove and a third partition structure disposed in the cutting groove.

[0112] Figure 7 A schematic diagram of a planar structure of a combined driving region is provided for the exemplary embodiments of the present disclosure. As shown in the diagram, in a plane parallel to the display substrate, a plurality of circuit units M of the display region can be arranged along a first direction X and a second direction Y respectively, the plurality of circuit units M arranged along the first direction X can be referred to as a unit row, the plurality of circuit units M arranged along the second direction Y can be referred to as a unit column, and the plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, the first direction X and the second direction Y intersecting. Figure 7

[0113] In the exemplary embodiments, one first pixel driving circuit 100A can be provided in one circuit unit M of the normal driving region 110, and the first pixel driving circuit 100A is connected to one first light emitting device 200A corresponding to the region. One first pixel driving circuit 100A and at least one second pixel driving circuit 100B can be provided in one circuit unit M of the combined driving region 120, the first pixel driving circuit 100A is connected to one first light emitting device 200A corresponding to the region, and the second pixel driving circuit 100B is connected to one second light emitting device located in the circuit region 210. Figure 7 In the exemplary embodiments, one rectangle represents one pixel driving circuit.

[0114] In the exemplary embodiments, one circuit unit M of the combined driving region 120 can include a first sub-unit M1 and a second sub-unit M2, the first pixel driving circuit 100A can be provided in the first sub-unit M1, and the second pixel driving circuit 100B can be provided in the second sub-unit M2. The area occupied by the first pixel driving circuit 100A in the combined driving region 120 can be about half of the area occupied by the first pixel driving circuit 100A in the normal driving region 110, or smaller, and the area occupied by the first pixel driving circuit 100A and the area occupied by the second pixel driving circuit 100B in the combined driving region 120 can be substantially equivalent. The first pixel driving circuit 100A should ensure the lighting of the connected first light emitting device 200A, and the second pixel driving circuit 100B should ensure the lighting of the connected second light emitting device.

[0115] In the exemplary embodiments, the width of the combined driving region 120 along the first direction X can be determined according to the number of second light emitting devices provided in the circuit region 210, the arrangement of the anode connection lines, and other factors.

[0116] In the exemplary embodiments, the first sub-unit M1 and the second sub-unit M2 in the circuit unit M of the combined driving region 120 can be arranged in sequence along the first direction X, or can be arranged in sequence along the second direction Y, or can be arranged in sequence along other directions, which are not limited in the present disclosure. ​

[0117] Figure 8 A schematic diagram of the connection of light emitting devices in a circuit region of an exemplary embodiment of the present disclosure is shown. As shown, in a plane parallel to the display substrate, the circuit region 210 can include at least a plurality of shift registers (not shown) and a plurality of second light emitting devices 200B, which can be arranged along a first direction X and a second direction Y respectively. The plurality of second light emitting devices 200B arranged along the first direction X in sequence can be referred to as a pixel row, and the plurality of second light emitting devices 200B arranged along the second direction Y in sequence can be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. Figure 8 Figure 8 In the plane parallel to the display substrate, the combined driving region 120 can include a plurality of circuit units M and a plurality of first light emitting devices 200A. The plurality of first light emitting devices 200A can be arranged along the first direction X and the second direction Y respectively. The plurality of first light emitting devices 200A arranged along the first direction X in sequence can be referred to as a pixel row, and the plurality of first light emitting devices 200A arranged along the second direction Y in sequence can be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array. The plurality of circuit units M can be arranged along the first direction X and the second direction Y respectively. The plurality of circuit units M arranged along the first direction X in sequence can be referred to as a unit row, and the plurality of circuit units M arranged along the second direction Y in sequence can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array. At least one circuit unit M can include a first sub-unit M1 and a second sub-unit M2. The first sub-unit M1 can be provided with a first pixel driving circuit 100A, and the second sub-unit M2 can be provided with a second pixel driving circuit 100B. Figure 8

[0118] In an exemplary implementation, taking the example that the circuit region 210 includes 20 second light emitting devices 200B (2 pixel rows 10 pixel columns) and the combined driving region 120 includes 20 circuit units M (2 unit rows 10 unit columns), the connection of the light emitting devices and the pixel driving circuits can be as follows:

[0119] In the combined driving region 120, each first light emitting device 200A can be connected with the first pixel driving circuit 100A in the corresponding circuit unit.

[0120] ​​In the circuit region 210, the plurality of second light emitting devices 200B of the first pixel row can be connected to the plurality of second pixel driving circuits 100B of the first unit row in the combined driving region 120 through anode connection lines, respectively. For example, the first second light emitting device 200B is connected to the second pixel driving circuit 100B in the first circuit unit M through an anode connection line, the second second light emitting device 200B is connected to the second pixel driving circuit 100B in the second circuit unit M through an anode connection line, and the tenth second light emitting device 200B is connected to the second pixel driving circuit 100B in the tenth circuit unit M through an anode connection line. In the plurality of circuit units M of the first unit row, the first sub-unit M1 in which the first pixel driving circuit 100A is arranged is located at the left side of the circuit unit M, and the second sub-unit M2 in which the second pixel driving circuit 100B is arranged is located at the right side of the circuit unit M.

[0121] In the circuit region 210, the plurality of second light emitting devices 200B of the first pixel row can be connected to the plurality of second pixel driving circuits 100B of the first unit row in the combined driving region 120 through anode connection lines, respectively. For example, the first second light emitting device 200B is connected to the second pixel driving circuit 100B in the first circuit unit M through an anode connection line, the second second light emitting device 200B is connected to the second pixel driving circuit 100B in the second circuit unit M through an anode connection line, and the tenth second light emitting device 200B is connected to the second pixel driving circuit 100B in the tenth circuit unit M through an anode connection line. In the plurality of circuit units M of the first unit row, the first sub-unit M1 in which the first pixel driving circuit 100A is arranged is located at the left side of the circuit unit M, and the second sub-unit M2 in which the second pixel driving circuit 100B is arranged is located at the right side of the circuit unit M.

[0122] It should be noted that, Figure 8 The positions and routing shapes of the anode connection lines shown in the above are only exemplary. In actual implementation, the plurality of anode connection lines can be arranged on the same side of the light emitting device, or can be arranged on different sides of the light emitting device, or can be alternately arranged on both sides of the light emitting device, and the plurality of anode connection lines can be arranged in the same conductive layer or can be arranged in different conductive layers, which are not limited in the present disclosure.

[0123] In the exemplary embodiment, the first light emitting device 200A in the display region 100 can at least include a first pixel opening defining a light emitting region, and the second light emitting device 200B in the frame region 200 can at least include a second pixel opening defining a light emitting region.

[0124] In an example embodiment, the pitch L2 between adjacent second pixel openings in the bezel region 200 can be greater than or equal to the pitch L1 between adjacent first pixel openings in the display region 100. When the pitch L2 is equal to the pitch L1, the resolution of the bezel region 200 can be made to be approximately equal to the resolution of the display region 100. When the pitch L2 is greater than the pitch L1, the resolution of the bezel region 200 can be made to be less than the resolution of the display region 100. Here, the pitch can be the distance between centers of pixel openings, which are geometric centers of the pixel openings. For example, the pitch can be the distance between centers of adjacent pixel openings in the first direction X. For another example, the pitch can be the distance between centers of adjacent pixel openings in the second direction Y.

[0125] In an example embodiment, the pitch L2 between adjacent second pixel openings in the bezel region 200 can be the same at multiple locations of the bezel region 200, forming a pixel array with equally-pitched second pixel openings.

[0126] In an example embodiment, the pitch L2 between adjacent second pixel openings in the bezel region 200 can gradually increase along a direction away from the display region, forming a pixel array with variably-pitched second pixel openings.

[0127] In an example embodiment, the area of the second pixel openings in the bezel region 200 can be equal to the area of the first pixel openings in the display region 100, such that the resolution of the bezel region 200 can be made to be approximately equal to the resolution of the display region 100. Here, the area can be the area of a footprint of a pixel opening on a substrate.

[0128] In an example embodiment, the first pixel openings can include first red pixel openings of first red light-emitting devices, first blue pixel openings of first blue light-emitting devices, and first green pixel openings of first green light-emitting devices, the second pixel openings can include second red pixel openings of second red light-emitting devices, second blue pixel openings of second blue light-emitting devices, and second green pixel openings of second green light-emitting devices, and the area of the second pixel openings being equal to the area of the first pixel openings can include any one or more of: the area of the first red pixel openings being equal to the area of the second red pixel openings, the area of the first blue pixel openings being equal to the area of the second blue pixel openings, and the area of the first green pixel openings being equal to the area of the second green pixel openings.

[0129] In an example embodiment, the area of the second pixel openings in the bezel region 200 can be less than the area of the first pixel openings in the display region 100, such that the resolution of the bezel region 200 is less than the resolution of the display region 100.

[0130] In an example embodiment, the area of the second pixel openings in the bezel region 200 can be the same at multiple locations of the bezel region 200, forming a pixel array with equally-emitting-area second pixel openings.

[0131] In an exemplary embodiment, the area of ​​the second pixel opening in the border area 200 can be gradually reduced along the direction away from the display area, forming a pixel array with variable light-emitting area arrangement.

[0132] In an exemplary embodiment, setting the resolution of the border area 200 to be less than that of the display area 100 can reduce the number of anode connection lines and the arrangement pressure of pixel driving circuits in the combined driving area.

[0133] Figure 9 This is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the cross-sectional structure of the combined driving area 120 in the display region and the circuit area 210, cathode overlap area 220, partition area 230, and cutting area 240 in the bezel area. Figure 9 As shown, in a plane perpendicular to the display substrate, the combined driving region 120 may include a driving structure layer 101 disposed on the substrate 10, a first light-emitting structure layer 102 disposed on the side of the driving structure layer 101 away from the substrate, and an encapsulation structure layer 103 disposed on the side of the first light-emitting structure layer 102 away from the substrate. The circuit region 210 may include a circuit structure layer disposed on the substrate 10, a second light-emitting structure layer disposed on the side of the circuit structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the second light-emitting structure layer away from the substrate. The cathode overlap region 220, the partition region 230, and the cutting region 240 may include a frame structure layer disposed on the substrate 10. The frame structure layer of the cathode overlap region 220 may include at least an isolation dam 90 and a first partition structure 91. The frame structure layer of the partition region 230 may include at least a second partition structure 92. The frame structure layer of the cutting region 240 may include at least a third partition structure 93.

[0134] In an exemplary embodiment, the driving structure layer 101 of the combined driving region 120 may include multiple circuit units, at least one of which may include a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit may each include multiple transistors and a storage capacitor. The circuit structure layer 201 of the circuit region 210 may include multiple cascaded shift registers, and the shift registers may include multiple transistors and a storage capacitor. Figure 9 The diagram only illustrates two circuit units and one shift register. For example, the first pixel driving circuit includes a first transistor 1A and a first storage capacitor 1B, the second pixel driving circuit includes a second transistor 2A and a second storage capacitor 2B, and the shift register includes a third transistor 3A and a third storage capacitor 3B.

[0135] In the example embodiment, the driving structure layer of the combined driving area 120 and the circuit structure layer of the circuit area 210 can at least include: a first insulating layer 11 disposed on the substrate 10, a semiconductor layer disposed on the far side of the first insulating layer 11 from the substrate, a second insulating layer 12 disposed on the far side of the semiconductor layer from the substrate, a first conductive layer disposed on the far side of the second insulating layer 12 from the substrate, a third insulating layer 13 disposed on the far side of the first conductive layer from the substrate, a second conductive layer disposed on the far side of the third insulating layer 13 from the substrate, a fourth insulating layer 14 disposed on the far side of the second conductive layer from the substrate, a third conductive layer disposed on the far side of the fourth insulating layer 14 from the substrate, a fifth insulating layer 15 disposed on the far side of the third conductive layer from the substrate, a first planar layer 16 disposed on the far side of the fifth insulating layer 15 from the substrate, a fourth conductive layer disposed on the far side of the first planar layer 16 from the substrate, a second planar layer 17 disposed on the far side of the fourth conductive layer from the substrate, a fifth conductive layer disposed on the far side of the second planar layer 17 from the substrate, and a third planar layer 18 disposed on the far side of the fifth conductive layer from the substrate. Among them, the semiconductor layer can include a plurality of active layers, the first conductive layer can include a plurality of gate electrodes and capacitor electrodes, the second conductive layer can include a plurality of capacitor electrodes, the third conductive layer can include a plurality of source electrodes and drain electrodes, the fourth conductive layer can include a plurality of first connection electrodes, a plurality of first transition electrodes, and a plurality of first anode connection lines 81, and the fifth conductive layer can include a plurality of second connection electrodes, a plurality of second transition electrodes, and a plurality of second anode connection lines 82.

[0136] In the example embodiment, the first light-emitting structure layer of the combined driving area 120 and the second light-emitting structure layer of the circuit area 210 can at least include: an anode conductive layer disposed on the far side of the driving structure layer 101 from the substrate, a pixel definition layer disposed on the far side of the anode conductive layer from the substrate, an organic light-emitting layer, and a cathode. Among them, the anode conductive layer can include a plurality of first anodes 21 located in the combined driving area 120 and a plurality of second anodes 22 and a cathode connection electrode 23 located in the circuit area 210, the first anodes 21 are connected to the drain electrodes of the first transistors 1A through the first connection electrodes and the second connection electrodes, a part of the second anodes 22 are connected to the drain electrodes of a part of the second transistors 2A through the second transition electrodes and the first anode connection lines 81, another part of the second anodes 22 are connected to the drain electrodes of another part of the second transistors 2A through the second anode connection lines 82 and the first transition electrodes, and the cathode is connected to the cathode connection electrode 23 through the connection via hole opened on the pixel definition layer.

[0137] In the exemplary embodiment, the frame structure layer of the cathode overlap region 220 can at least include: a composite insulating layer disposed on the substrate 10, a power line 50 disposed on the side of the composite insulating layer away from the substrate, a first cathode electrode 51 disposed on the side of the power line 50 away from the substrate, a second cathode electrode 52 disposed on the side of the first cathode electrode 51 away from the substrate, a cathode connecting electrode 23 disposed on the side of the second cathode electrode 52 away from the substrate, an isolation dam 90 and a first partition structure 91 disposed on the side of the cathode connecting electrode 23 away from the substrate. Among them, the first cathode electrode 51 is overlapped with the power line 50, the second cathode electrode 52 is overlapped with the first cathode electrode 51, and the cathode connecting electrode 23 is overlapped with the second cathode electrode 52.

[0138] In the exemplary embodiment, the frame structure layer of the partition region 230 can at least include: a composite insulating layer disposed on the substrate 10, a second partition structure 92 disposed on the side of the composite insulating layer away from the substrate.

[0139] In the exemplary embodiment, the frame structure layer of the cutting region 240 can at least include: a composite insulating layer disposed on the substrate 10, a cutting groove disposed on the composite insulating layer, and a third partition structure 93 disposed in the cutting groove.

[0140] The preparation process of the display substrate is exemplarily illustrated as follows. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, "the orthographic projection of B is located within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0141] In the exemplary embodiment, the preparation process of the display substrate in the exemplary embodiment of the present disclosure can include the following operations.

[0142] (1) Forming a transistor structure layer pattern on a substrate, as shown in Figure 10 In an exemplary embodiment, forming a transistor structure layer pattern on a substrate can include:

[0143] Depositing a first insulating thin film and a semiconductor thin film on the substrate in sequence, patterning the semiconductor thin film by a patterning process, forming a first insulating layer 11 covering the entire substrate 10 and a semiconductor layer pattern disposed on the first insulating layer 11, the semiconductor layer pattern including at least: a plurality of first active layers and a plurality of second active layers located in the combined driving area 120, and a plurality of third active layers located in the circuit area 210.

[0144] Subsequently, a second insulating thin film and a first conductive thin film are deposited in sequence, the first conductive thin film is patterned by a patterning process, forming a second insulating layer 12 covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer 12, the first conductive layer pattern including at least: a plurality of first gate electrodes, a plurality of second gate electrodes, a plurality of first capacitor electrodes and a plurality of second capacitor electrodes located in the combined driving area 120, and a plurality of third gate electrodes and a plurality of third capacitor electrodes located in the circuit area 210. In an exemplary embodiment, the first conductive layer can be referred to as the first gate metal layer (GATE1).

[0145] Subsequently, a third insulating thin film and a second conductive thin film are deposited in sequence, the second conductive thin film is patterned by a patterning process, forming a third insulating layer 13 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 13, the second conductive layer pattern including at least: a plurality of fourth capacitor electrodes and a plurality of fifth capacitor electrodes located in the combined driving area 120, and a plurality of sixth capacitor electrodes located in the circuit area 210, the orthographic projection of the fourth capacitor electrodes on the substrate at least partially overlaps the orthographic projection of the first capacitor electrodes on the substrate, the orthographic projection of the fifth capacitor electrodes on the substrate at least partially overlaps the orthographic projection of the second capacitor electrodes on the substrate, and the orthographic projection of the sixth capacitor electrodes on the substrate at least partially overlaps the orthographic projection of the third capacitor electrodes on the substrate. In an exemplary embodiment, the second conductive layer can be referred to as the second gate metal layer (GATE2).

[0146] Subsequently, a fourth insulating thin film is deposited, and the fourth insulating thin film is patterned by a patterning process to form a fourth insulating layer 14 covering the second conductive layer pattern, the combined driving area 120 and the circuit area 210 form a plurality of active vias, and the cutting area 240 forms a cutting groove.

[0147] In the exemplary embodiment, the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the plurality of active vias in the combined driving region 120 are etched to expose both ends of the plurality of first active layers and the plurality of second active layers, respectively. The fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the plurality of active vias in the circuit region 210 are etched to expose both ends of the plurality of third active layers. The fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the cutting groove in the cutting region 240 are etched to expose the surface of the first insulating layer 11.

[0148] In the exemplary embodiment, the present process can be synchronized with the patterning process of the bending groove in the bending region in the binding area. For example, the fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 are etched by the first mask (Etch Bending A MASK, EBA MASK for short) to form a plurality of active vias in the combined driving region 120 and the circuit region 210, and a cutting groove in the cutting region. The fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the active vias are etched to expose the surface of the corresponding active layer. The fourth insulating layer 14, the third insulating layer 13 and the second insulating layer 12 in the cutting groove are etched to expose the surface of the first insulating layer 11. Then, the first insulating layer in the bending region is etched by the second mask (Etch Bending B MASK, EBB MASK for short) to form a bending groove in the bending region. The first insulating layer in the bending groove is etched to expose the surface of the substrate. In the exemplary embodiment, the EBA MASK and EBB MASK processes can form a bending groove in the bending region in the binding area to reduce the thickness of the bending region.

[0149] Subsequently, a third conductive thin film is deposited, and the third conductive thin film is patterned by a patterning process to form a third conductive layer pattern on the fourth insulating layer 14. The third conductive layer pattern at least includes: a plurality of first source electrodes, a plurality of first drain electrodes, a plurality of second source electrodes and a plurality of second drain electrodes in the combined driving region 120, a plurality of third source electrodes and a plurality of third drain electrodes in the circuit region 210, and a power line 50 in the cathode overlap region 220. The first source electrode and the first drain electrode are connected to the first active layer through the active via, the second source electrode and the second drain electrode are connected to the second active layer through the active via, and the third source electrode and the third drain electrode are connected to the third active layer through the active via. The power line 50 is arranged on the fourth insulating layer 14, and the end of the power line 50 away from the combined driving region 120 has a spacing with the partition region 230. In the exemplary embodiment, the third conductive layer can be referred to as a first source-drain metal layer (SD1).

[0150] At this point, the transistor structure layer pattern is prepared on the substrate, as shown in FIG. 6. Figure 10The transistor structure layer of the combined driving area 120 can include a plurality of transistors and a storage capacitor constituting the first pixel driving circuit and the second pixel driving circuit in the exemplary embodiment. The transistor structure layer of the circuit area 210 can include a plurality of transistors and a storage capacitor constituting the shift register. The first active layer, the first gate electrode, the first source electrode and the first drain electrode of the combined driving area 120 constitute a first transistor 1A, and the first capacitor electrode and the fourth capacitor electrode constitute a first storage capacitor 1B, Figure 10 The two first transistors 1A can be respectively located in the first sub-unit of the two circuit units. The second active layer, the second gate electrode, the second source electrode and the second drain electrode of the combined driving area 120 constitute a second transistor 2A, and the second capacitor electrode and the fifth capacitor electrode constitute a second storage capacitor 2B, Figure 10 The two second transistors 2A can be respectively located in the second sub-unit of the two circuit units. The third active layer, the third gate electrode, the third source electrode and the third drain electrode of the circuit area 210 constitute a third transistor 3A, and the third capacitor electrode and the sixth capacitor electrode constitute a third storage capacitor 3B. In the exemplary embodiment, the first transistor 1A can be a driving transistor in the first pixel driving circuit, the second transistor 2A can be a driving transistor in the second pixel driving circuit, and the third transistor 3A can be a scan transistor outputting a scan (SCAN) signal in the shift register or an enable transistor outputting an enable (EM) signal in the shift register. The driving transistor, the scan transistor and the enable transistor can all be thin film transistors (TFTs).

[0151] In the exemplary embodiment, the transistor structure layer of the cathode overlap area 220 can include a composite insulating layer disposed on the substrate 10 and a power supply line 50 disposed on the side of the composite insulating layer away from the substrate. The transistor structure layer of the partition area 230 can include a composite insulating layer disposed on the substrate 10. The transistor structure layer of the cutting area can include a composite insulating layer disposed on the substrate 10, and a cutting groove is formed on the composite insulating layer. In the exemplary embodiment, the composite insulating layer can include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13 and a fourth insulating layer 14 stacked on the substrate 10.

[0152] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be made of glass or quartz, and the flexible substrate can be formed by a method of manufacturing on a glass carrier plate. For example, the substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier plate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx) or the like, for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si). In an exemplary embodiment, taking the stack structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the manufacturing process can include: first, coating a layer of polyimide on a glass carrier plate, and after curing to form a film, forming a first flexible (PI1) layer; then depositing a layer of barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing to form a film, forming a second flexible (PI2) layer; then depositing a layer of barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, completing the manufacturing of the substrate.

[0153] (2) Forming the fifth insulating layer and the first planar layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the first planar layer pattern can include: depositing a fifth insulating film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating film by a patterning process to form a fifth insulating layer 15 pattern covering the third conductive layer pattern. Subsequently, a first planar film is coated, and the first planar film is patterned by a patterning process to form a first planar layer 16 located in the combined driving area 120 and the circuit area 210 and a first dam foundation 90a located in the cathode overlap area 220, as shown in FIG. 2B. Figure 11

[0154] In an exemplary embodiment, the fifth insulating layer 15 can be formed in the combined driving area 120 and the circuit area 210, and the fifth insulating layer 15 can extend from the circuit area 210 to the cathode overlap area 220 and cover the edge of the power supply line 50 near the display area side to avoid causing film layer edge peeling and improve process quality.

[0155] ​In the example embodiment, the first planar layer 16 between the combination driving region 120 and the circuit region 210 can be disposed on the fifth insulating layer 15, and the fifth insulating layer 15 and the first planar layer 16 are formed with a plurality of first connection vias K1 and a plurality of second connection vias K2. The fifth insulating layer 15 and the first planar layer 16 in the first connection via K1 are removed to expose the surface of the first drain electrode of the first transistor 1A, and the first connection via K1 is configured to allow the subsequently formed first connection electrode to connect with the first drain electrode through the via. The fifth insulating layer 15 and the first planar layer 16 in the second connection via K2 are removed to expose the surface of the second drain electrode of the second transistor 2A, and the second connection via K2 is configured to allow the subsequently formed anode connection line or first transition electrode to connect with the second drain electrode through the via.

[0156] In the example embodiment, the first dam base 90a can be disposed on the fourth insulating layer 14 of the cathode overlap region 220 and the power supply line 50, and the first dam base 90a can cover the edge of the power supply line 50 away from the display area side to avoid causing film layer peeling, thereby improving process quality, and the first dam base 90a is configured to form a dam together with the subsequently formed second dam base and third dam base. In the example embodiment, the cross-sectional shape of the first dam base can be trapezoidal, and the length of the upper base away from the substrate side can be less than the length of the lower base adjacent to the substrate side.

[0157] In the example embodiment, the first planar film between the first planar layer 16 and the first dam base 90a is removed to form an organic groove exposing the surface of the power supply line 50, and the organic groove is configured to form a gas discharge channel to discharge the gas generated by the planarization film and avoid causing film layer peeling, thereby improving process quality.

[0158] (3) Forming a fourth conductive layer pattern. In the example embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive film on the substrate formed with the aforementioned pattern, patterning the fourth conductive film by a patterning process, and forming the fourth conductive layer pattern on the first planar layer 16. The fourth conductive layer pattern can at least include: a plurality of first connection electrodes 61 and a plurality of first transition electrodes 71 in the combination driving region 120, a plurality of first anode connection lines 81 in the circuit region 210, and a first cathode electrode 51 in the cathode overlap region 220, as shown in Figure 12

[0159] In the example embodiment, the plurality of first connection electrodes 61 in the combination driving region 120 are respectively connected with the first drain electrodes of the plurality of first transistors 1A through the first connection vias K1, and the plurality of first connection electrodes 61 are configured to be connected with the plurality of second connection electrodes subsequently formed in the display area 100.

[0160] ​In the example embodiment, the plurality of first transition electrodes 71 in the combined driving region 120 are respectively connected to a part of the second drain electrodes of the second transistors 2A through the second connection vias K2, and the plurality of first transition electrodes 71 are configured to be connected to the plurality of second anode connection lines formed subsequently in the circuit region 210.

[0161] In the example embodiment, the plurality of first anode connection lines 81 of the circuit region 210 are respectively extended to the combined driving region 120 and connected to another part of the second drain electrodes of the second transistors 2A through the second connection vias K2, and the plurality of first anode connection lines 81 are configured to be connected to the plurality of second transition electrodes formed subsequently in the circuit region 210.

[0162] In the example embodiment, the first cathode electrode 51 of the cathode overlap region 220 is overlapped on the power supply line 50, and the first cathode electrode 51 covers the first dam base 90a close to the edge of the display region side away from the display region side to avoid causing film layer edge peeling and improve process quality, and the first cathode electrode 51 is configured to be overlapped with the second cathode electrode formed subsequently in the cathode overlap region 220.

[0163] (4) Forming a second planar layer pattern. In the example embodiment, forming the second planar layer pattern can include: coating a second planar film on the substrate on which the aforementioned pattern is formed, and patterning the second planar film through a patterning process to form the second planar layer 17 located in the combined driving region 120 and the circuit region 210 and the second dam base 90b located in the cathode overlap region 220, as shown in Figure 13 .

[0164] In the example embodiment, the second planar layer 17 of the combined driving region 120 is formed with a plurality of third connection vias K3 and a plurality of fourth connection vias K4. The second planar layer 17 in the third connection via K3 is removed to expose the surface of the first connection electrode 61, and the third connection via K3 is configured to enable the second connection electrode formed subsequently in the display region 100 to be connected to the first connection electrode 61 through the via. The second planar layer 17 in the fourth connection via K4 is removed to expose the surface of the first transition electrode 71, and the fourth connection via K4 is configured to enable the second anode connection line formed subsequently in the circuit region 210 to be connected to the first transition electrode 71 through the via.

[0165] In the example embodiment, the second planar layer 17 of the circuit region 210 is formed with a plurality of fifth connection vias K5, and the second planar layer 17 in the fifth connection via K5 is removed to expose the surface of the first anode connection line 81, and the fifth connection via K5 is configured to enable the second transition electrode formed subsequently in the circuit region 210 to be connected to the first anode connection line 81 through the via.

[0166] In the example embodiment, the second dam base 90a can be disposed on the first dam base 90a of the cathode overlap region 220, and the second dam base 90b can cover the edge of the first cathode electrode 51 away from the display region side to avoid causing film layer edge peeling and improve process quality. The second dam base 90b is configured to form a separation dam together with the first dam base 90a and a third dam base to be formed subsequently. In the example embodiment, the cross-sectional shape of the second dam base 90b can be trapezoidal, and the length of the upper base away from the substrate side can be less than the length of the lower base adjacent to the substrate side.

[0167] In the example embodiment, the process can first form the sixth insulating layer, and then form the second planar layer on the sixth insulating layer, or can first form the second planar layer, and then form the sixth insulating layer on the second planar layer, which is not limited in the present disclosure.

[0168] (5) Forming a fifth conductive layer pattern. In the example embodiment, forming the fifth conductive layer pattern can include: depositing a fifth conductive thin film on the substrate of the aforementioned pattern, patterning the fifth conductive thin film by a patterning process, and forming the fifth conductive layer pattern on the second planar layer 17. The fifth conductive layer pattern can at least include: a plurality of second connection electrodes 62 in the combined driving region 120, a plurality of second transition electrodes 72 and a plurality of second anode connection lines 82 in the circuit region 210, and a second cathode electrode 52 in the cathode overlap region 220, as shown in Figure 14 .

[0169] In the example embodiment, the plurality of second connection electrodes 62 in the combined driving region 120 are respectively connected to the plurality of first connection electrodes 61 through third connection vias K3, and the plurality of second connection electrodes 62 are configured to be connected to a plurality of first anodes to be formed subsequently in the display region 100.

[0170] In the example embodiment, the plurality of second anode connection lines 82 of the circuit region 210 respectively extend to the combined driving region 120 and are connected to the plurality of first transition electrodes 71 through fourth connection vias K4, and the plurality of second anode connection lines 82 are configured to be connected to a plurality of second anodes to be formed subsequently in the circuit region 210.

[0171] In the example embodiment, the plurality of second transition electrodes 72 of the circuit region 210 are respectively connected to the plurality of first anode connection lines 81 through fifth connection vias K5, and the plurality of second transition electrodes 72 are configured to be connected to a plurality of second anodes to be formed subsequently in the circuit region 210.

[0172] In the exemplary embodiment, the second cathode electrode 52 of the cathode overlap region 220 overlaps on the first cathode electrode 51, and the second cathode electrode 52 covers the second dam base 90b close to the edge of the display region side to avoid causing film layer edge peeling and improve process quality, and the second cathode electrode 52 is configured to overlap with the cathode connection electrode formed subsequently in the cathode overlap region 220.

[0173] (6) Forming a third planar layer pattern. In the exemplary embodiment, forming the third planar layer pattern can include: coating a third planar film on the substrate on which the aforementioned patterns are formed, and patterning the third planar film by a patterning process to form the third planar layer 18 located in the combined driving region 120 and the circuit region 210, and the third planar layer of the cathode overlap region 220 and the area outside the cathode overlap region 220 is removed, as shown in Figure 15

[0174] In the exemplary embodiment, the third planar layer 18 of the combined driving region 120 is formed with a plurality of sixth connection vias K6, and the third planar layer 18 in the sixth connection via K6 is removed to expose the surface of the second connection electrode 62, and the sixth connection via K6 is configured to allow the first anode formed subsequently in the display region 100 to be connected to the second connection electrode 62 through the via.

[0175] In the exemplary embodiment, the third planar layer 18 of the circuit region 210 is formed with a plurality of seventh connection vias K7 and a plurality of eighth connection vias K8. The third planar layer 18 in the seventh connection via K7 is removed to expose the surface of the second anode connection line 82, and the seventh connection via K7 is configured to allow the plurality of second anodes formed subsequently in the circuit region 210 to be connected to the second anode connection line 82 through the via. The third planar layer 18 in the eighth connection via K8 is removed to expose the surface of the second transition electrode 72, and the eighth connection via K8 is configured to allow the plurality of second anodes formed subsequently in the circuit region 210 to be connected to the second transition electrode 72 through the via.

[0176] In the exemplary embodiment, the process can first form a seventh insulating layer, and then form a third planar layer on the seventh insulating layer, which is not limited in the present disclosure.

[0177] ​At this point, the driving structure layer is formed in the driving region 120, and the circuit structure layer is formed in the circuit region 210. The driving structure layer and the circuit structure layer can at least include: a first insulating layer 11 disposed on the substrate 10, a semiconductor layer disposed on the first insulating layer 11 away from the substrate, a second insulating layer 12 disposed on the semiconductor layer away from the substrate, a first conductive layer disposed on the second insulating layer 12 away from the substrate, a third insulating layer 13 disposed on the first conductive layer away from the substrate, a second conductive layer disposed on the third insulating layer 13 away from the substrate, a fourth insulating layer 14 disposed on the second conductive layer away from the substrate, a third conductive layer disposed on the fourth insulating layer 14 away from the substrate, a fifth insulating layer 15 disposed on the third conductive layer away from the substrate, a first planar layer 16 disposed on the fifth insulating layer 15 away from the substrate, a fourth conductive layer disposed on the first planar layer 16 away from the substrate, a second planar layer 17 disposed on the fourth conductive layer away from the substrate, a fifth conductive layer disposed on the second planar layer 17 away from the substrate, and a third planar layer 18 disposed on the fifth conductive layer away from the substrate.

[0178] In the exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer. The first insulating layer can be referred to as a buffer (Buffer) layer, the second insulating layer and the third insulating layer can be referred to as a gate insulating (GI) layer, the fourth insulating layer can be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer can be referred to as a passivation (PVX) layer. The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be any one or more of metal materials such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above-mentioned metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure such as Ti / Al / Ti, etc. The first planar layer, the second planar layer, and the third planar layer can be an organic material such as resin, etc. The semiconductor layer can be various materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathienyl, polythiophene, etc., i.e., the present disclosure is applicable to transistors manufactured based on oxide Oxide technology, silicon technology, and organic technology.

[0179] (7) forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the anode conductive thin film through a patterning process, forming the anode conductive layer pattern on the third planar layer 18, which can at least include: the plurality of first anodes 21 in the combined driving area 120, the cathode overlap electrode 23 and the plurality of second anodes 22 in the circuit area 210, and the cathode overlap electrode 23 in the cathode overlap area 220, as shown in Figure 16

[0180] In an exemplary embodiment, the plurality of first anodes 21 in the combined driving area 120 are respectively connected to the plurality of second connection electrodes 62 through the sixth connection via holes K6. Since the second connection electrodes 62 are connected to the first connection electrodes 61 through the via holes, and the first connection electrodes 61 are connected to the first drain electrodes of the first transistors 1A through the via holes, the first anodes 21 in the combined driving area 120 are connected to the first pixel driving circuit in the combined driving area 120 through the second connection electrodes 62 and the first connection electrodes 61.

[0181] In an exemplary embodiment, a part of the plurality of second anodes 22 in the circuit area 210 are respectively connected to the plurality of second anode connection lines 82 through the seventh connection via holes K7, and another part of the plurality of second anodes 22 are respectively connected to the plurality of second transition electrodes 72 through the eighth connection via holes K8. Since the second anode connection lines 82 are connected to the first transition electrodes 71 through the via holes, the first transition electrodes 71 are connected to the second drain electrodes of a part of the second transistors 2A through the via holes, the second transition electrodes 72 are connected to the first anode connection lines 81 through the via holes, and the first anode connection lines 81 are connected to the second drain electrodes of another part of the second transistors 2A through the via holes, the second anodes 22 in the circuit area 210 are connected to the second pixel driving circuit in the combined driving area 120 through the transition electrodes and the anode connection lines.

[0182] In an exemplary embodiment, the cathode overlap electrode 23 in the circuit area 210 can be a full-area structure, which is respectively spaced apart from the plurality of first anodes 21 in the combined driving area 120 and the plurality of second anodes 22 in the circuit area 210, and extends to the cathode overlap area 220 to overlap with the second cathode electrode 52, i.e., the cathode overlap electrodes 23 in the circuit area 210 and the cathode overlap area 220 are an integral structure connected to each other.

[0183] Figure 17 FIG. 6 is a schematic view of a planar structure of a cathode overlap electrode in a circuit area according to an exemplary embodiment of the present disclosure. Figure 17 ​As shown, the cathode overlap electrode 23 of the circuit region 210 and the cathode overlap region 220 can be an integral full-surface structure, and a plurality of hollowed-out regions 23-1 are arranged on the cathode overlap electrode 23 of the circuit region 210. The hollowed-out regions 23-1 are through holes penetrating the anode conductive layer, and a plurality of second anodes 22 are arranged in the plurality of hollowed-out regions 23-1, so that the second anodes 22 are arranged in isolation from the cathode overlap electrode 23.

[0184] In an example embodiment, the cathode overlap electrode 23 can cover the entire circuit region 210, or can cover part of the circuit region 210. For example, the area of the circuit region 210 close to the display area can not be provided with a cathode overlap electrode, and the cathode overlap electrode 23 is arranged only in the area of the circuit region 210 away from the display area and extends to the cathode overlap region 220, and is overlapped with the second cathode electrode 52 in the cathode overlap region 220.

[0185] In an example embodiment, the anode conductive layer can be made of a metal material or a transparent conductive material. The metal material can include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above-mentioned metals. The transparent conductive material can include indium tin oxide (ITO) or indium zinc oxide (IZO). In an example embodiment, the anode conductive layer can be a single-layer structure, or a multi-layer composite structure such as ITO / Al / ITO, etc.

[0186] The present disclosure increases the area of the cathode overlap electrode by arranging a cathode overlap electrode with a larger area in the circuit region, and the cathode overlap electrode with a full-surface structure is a hollowed-out structure, and the second anode is arranged in the hollowed-out region, which not only realizes the light emission of the light-emitting device in the circuit region, but also increases the area of the cathode overlap electrode and improves the reliability of the cathode overlap.

[0187] (8) Forming a pixel definition (PDL) layer pattern. In an example embodiment, forming the pixel definition layer pattern can include: coating a pixel definition film on the substrate on which the aforementioned pattern is formed, and patterning the pixel definition film by a patterning process to form the pixel definition layer 24 located in the combined driving region 120 and the circuit region 210, and the third dam base 90c located in the cathode overlap region 220, as shown. Figure 18

[0188] ​In the example embodiment, the pixel definition layer 24 on the combined driving area 120 is provided with a first pixel opening V1, and the pixel definition film in the first pixel opening V1 is removed to expose the surface of the first anode 21. The pixel definition layer 24 on the circuit area 210 is provided with a second pixel opening V2 and a connection opening K, and the pixel definition film in the second pixel opening V2 is removed to expose the surface of the second anode 22, and the pixel definition film in the connection opening K is removed to expose the surface of the cathode overlap electrode 23. In the plane parallel to the display substrate, the shape of the first pixel opening V1 and the second pixel opening V2 can be any one or more of the following: square, rectangle, pentagon, hexagon, polygon, circle, and ellipse. In the plane perpendicular to the substrate, the cross-sectional shape of the first pixel opening V1 and the second pixel opening V2 can be rectangle or trapezoid, and the inner side wall of the pixel opening can be flat or curved, which is not limited in the present disclosure.

[0189] In the example embodiment, the third dam base 90c can be disposed on the second dam base 90b of the cathode overlap area 220, and the third dam base 90c can cover the edge of the cathode overlap electrode 23 away from the display area to avoid causing film edge peeling and improve process quality. The first dam base 90a, the second dam base 90b, and the third dam base 90c form a separation dam 90. In the example embodiment, the cross-sectional shape of the separation dam 90 can be trapezoidal, and the length of the upper base away from the substrate can be less than the length of the lower base adjacent to the substrate.

[0190] In the example embodiment, the material of the pixel definition layer can include polyimide, acrylic, or polyethylene terephthalate, etc. In the example embodiment, the patterning process of the half-tone or gray-tone mask plate can be used to form the spacer (PS) pattern when forming the pixel definition layer, and the spacers can be disposed on the outside of the pixel opening and configured to support the fine metal mask in the subsequent evaporation process.

[0191] In the example embodiment, the area of the second pixel opening V2 on the circuit area 210 can be the same as the area of the first pixel opening V1 on the combined driving area 120, and the distance between adjacent second pixel openings V2 can be approximately equal to the distance between adjacent first pixel openings V1, so that the resolution of the circuit area 210 can be approximately equal to the resolution of the display area 100. In the present disclosure, the distance between pixel openings refers to the distance between the centers of two pixel openings.

[0192] In the example embodiment, the resolution of the circuit area 210 can be less than the resolution of the combined driving area 120 by differentiating the design of the first pixel opening V1 and the second pixel opening V2.

[0193] In an example embodiment, the area B2 of the second pixel opening V2 in the circuit region 210 can be smaller than the area B1 of the first pixel opening V1 in the combined driving region 120.

[0194] In an example embodiment, the area B2 of the second pixel opening V2 in the circuit region 210 can gradually decrease along a direction away from the display region, such that the resolution of the circuit region 210 gradually decreases along the direction away from the display region.

[0195] In an example embodiment, the spacing between adjacent second pixel openings V2 in the circuit region 210 can be greater than the spacing between adjacent first pixel openings V1 in the combined driving region 120.

[0196] In an example embodiment, the spacing between adjacent second pixel openings V2 in the circuit region 210 can gradually increase along a direction away from the display region, such that the resolution of the circuit region 210 gradually decreases along the direction away from the display region.

[0197] The display substrate provided by the example embodiments of the present disclosure can effectively reduce the number of anode connection lines and the arrangement pressure of pixel driving circuits in the combined driving region by differentiating the design of the second pixel opening in the circuit region and the first pixel opening in the display region, such that the resolution of the circuit region is less than the resolution of the display region.

[0198] (9) Forming the partition structure layer pattern. In an example embodiment, forming the partition structure layer pattern can include: first coating an organic material thin film on the substrate on which the aforementioned pattern is formed, then depositing an inorganic material thin film on the organic material thin film, and patterning the inorganic material thin film and the organic material thin film by a patterning process to form the first partition structure 91, the second partition structure 92, and the third partition structure 93, as shown in FIG. 9. Figure 19

[0199] In an example embodiment, the first partition structure 91 can be located in the cathode overlap region 220, on the side of the isolation dam 90 close to the display region, and disposed on the cathode overlap electrode 23. The second partition structure 92 can be located in the partition region 230 and disposed on the fourth insulating layer 14. The third partition structure 93 can be located in the cutting groove of the cutting region 240 and disposed on the first insulating layer 11.

[0200] In an example embodiment, the first partition structure 91, the second partition structure 92, and the third partition structure 93 can have substantially the same structure, and can include an organic layer 41 and an inorganic layer 42 disposed on the side of the organic layer 41 away from the substrate. Along a direction away from the display region, a plurality of organic grooves are disposed on the organic layer 41, and a plurality of inorganic grooves are disposed on the inorganic layer 42. The plurality of organic grooves and the plurality of inorganic grooves correspond to each other and are in communication with each other, forming a plurality of partition grooves.​

[0201] In the example embodiment, the inorganic slot has a smaller aperture than the aperture of the opening on the organic slot, the orthographic projection of the inorganic slot on the substrate is within the orthographic projection of the organic slot on the substrate, the inorganic layer 42 has a protrusion relative to the sidewall of the organic slot, and the protrusion and the sidewall of the organic slot near the side of the inorganic slot form a recessed structure, forming a “eave” structure. Alternatively, the organic layer 41 between adjacent organic slots and the inorganic layer 42 between adjacent inorganic slots form a “T”-shaped column, the orthographic projection of the inorganic layer 42 on the substrate contains the orthographic projection of the organic layer 41 on the substrate, the inorganic layer 42 has a protrusion relative to the sidewall of the organic layer 41, and forms a “eave” structure. The present disclosure forms a “T”-shaped column barrier structure in the cathode overlap area 220, the partition area 230, and the cutting area 240, which can avoid affecting the film layer structure of the circuit area during the cutting process. The plurality of spaced “T”-shaped columns not only can reduce the stress on the circuit area and cut off the crack transmission to the circuit area, but also can effectively block the water and oxygen from the cutting area.

[0202] In the example embodiment, the organic layer can use photoresist, and the inorganic layer can use any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, multiple layers, or a composite layer.

[0203] In the example embodiment, the process of patterning the inorganic material thin film and the organic material thin film by the patterning process can include: coating a layer of photoresist on the inorganic material thin film, exposing the photoresist using a mask plate, and forming a fully exposed area and an unexposed area after development, the photoresist in the fully exposed area is removed, and the photoresist in the unexposed area is retained. Then, the inorganic material thin film in the fully exposed area is etched using an etching process to form an inorganic layer in the cathode overlap area 220, the partition area 230, and the cutting area 240, the inorganic layer is provided with an inorganic slot, and the inorganic slot exposes the organic material thin film. Subsequently, the exposed organic material thin film is continuously etched to form an organic layer, the organic layer is provided with an organic slot, and the inorganic slot and the organic slot are in communication with each other.

[0204] In the example embodiment, dry etching process can be used for etching, and gases with large organic / inorganic etching ratios, such as O2, CF4, CHF3, etc. can be used. Since the organic / inorganic etching ratio is large, that is, the etching rate of etching the organic material is greater than the etching rate of etching the inorganic material, the organic material thin film is laterally etched when etching the organic material thin film, so that the organic slot is outwardly expanded by a distance relative to the inorganic slot, forming an organic slot with a side etching structure, and the inorganic layer 42 has a protrusion relative to the sidewall of the organic layer 41, forming a “T”-shaped column.

[0205] (10) Forming an organic light emitting layer pattern. In an exemplary embodiment, forming an organic light emitting layer pattern can include forming an organic light emitting layer 25 pattern on the substrate on which the aforementioned patterns are formed by an evaporation method or an inkjet printing method, as shown in FIG. 8. Figure 20

[0206] In an exemplary embodiment, the organic light emitting layer 25 can be formed only in the display area and the circuit area 210, and the organic light emitting layer 25 of the combined driving area 120 is connected to the first anode 21 through the first pixel opening, and the organic light emitting layer 25 of the circuit area 210 is connected to the second anode 22 through the second pixel opening.

[0207] In an exemplary embodiment, since the first partition structure 91 located in the cathode overlap area 220, the second partition structure 92 located in the partition area 230, and the third partition structure 93 located in the cutting area 240 have a "T" shaped pillar structure, the inorganic layer 42 has a protrusion with respect to the sidewall of the organic layer 41, and thus even if the organic light emitting layer is formed in the cathode overlap area 220, the partition area 230, and the cutting area 240, the formed organic light emitting layer is disconnected in the area where the partition structure is located.

[0208] In an exemplary embodiment, the organic light emitting layer can include an emission layer (EML), and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light emitting layer can be formed by an evaporation method using a fine metal mask (FMM) or an open mask, or by an inkjet process.

[0209] In an exemplary embodiment, the organic light emitting layer can be formed by the following method. First, a common layer of a hole injection layer and a hole transport layer is formed on the display substrate by sequentially evaporating the hole injection layer and the hole transport layer using an open mask. Subsequently, an electron blocking layer and a red emission layer are evaporated in the red sub-pixel, an electron blocking layer and a green emission layer are evaporated in the green sub-pixel, and an electron blocking layer and a blue emission layer are evaporated in the blue sub-pixel using a fine metal mask, and the electron blocking layer and the emission layer of adjacent sub-pixels can have a small amount of overlap (for example, the overlap portion accounts for less than 10% of the area of each emission layer pattern), or can be isolated. Subsequently, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially evaporated using an open mask to form a common layer of the hole blocking layer, the electron transport layer, and the electron injection layer on the display substrate.

[0210] ​In the exemplary embodiments, the electron blocking layer can be used as a microcavity adjustment layer of the light-emitting device. By designing the thickness of the electron blocking layer, the thickness of the organic light-emitting layer between the cathode and the anode can be designed to meet the design of the microcavity length. In some exemplary embodiments, the hole transport layer, the hole blocking layer, or the electron transport layer in the organic light-emitting layer can be used as the microcavity adjustment layer of the light-emitting device, which is not limited in the present disclosure.

[0211] In the exemplary embodiments, the light-emitting layer can include a host material and a dopant material doped in the host material, and the doping ratio of the dopant material in the light-emitting layer is 1% to 20%. Within the doping ratio range, on the one hand, the host material in the light-emitting layer can effectively transfer the exciton energy to the dopant material in the light-emitting layer to excite the dopant material in the light-emitting layer to emit light, and on the other hand, the host material in the light-emitting layer can "dilute" the dopant material in the light-emitting layer, effectively improve the fluorescence quenching caused by the mutual collision between the molecules and the mutual collision between the energies of the dopant material in the light-emitting layer, and improve the light-emitting efficiency and the device life. In the exemplary embodiments, the doping ratio refers to the ratio of the mass of the dopant material to the mass of the light-emitting layer, i.e., the mass percentage. In the exemplary embodiments, the host material and the dopant material can be co-evaporated by a multi-source evaporation process to uniformly disperse the host material and the dopant material in the light-emitting layer, and the doping ratio can be adjusted by controlling the evaporation rate of the dopant material during the evaporation process, or by controlling the evaporation rate ratio of the host material and the dopant material. In the exemplary embodiments, the thickness of the light-emitting layer can be about 10 nm to 50 nm.

[0212] In the exemplary embodiments, the hole injection layer can use inorganic oxides such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or can use a p-type dopant and a dopant of a hole transport material with a strong electron-withdrawing system. In the exemplary embodiments, the thickness of the hole injection layer can be about 5 nm to 20 nm.

[0213] In the exemplary embodiments, the hole transport layer can use a material with high hole mobility, such as an arylamine compound, and the substituent group thereof can be carbazole, methylfluorene, spirofluorene, dibenzothiophene, or furan, etc. In the exemplary embodiments, the thickness of the hole transport layer can be about 40 nm to 150 nm.

[0214] In the exemplary embodiments, the hole blocking layer and the electron transport layer can employ an aromatic heterocyclic compound, such as a benzimidazole derivative, an imidazopyridine derivative, a benzimidazophenanthroline derivative, and the like imidazole derivative; a pyrimidine derivative, a triazine derivative, and the like azine derivative; a quinoline derivative, an isoquinoline derivative, a phenanthroline derivative, and the like compound containing a nitrogen-containing six-membered ring structure (also including a compound having a phosphine oxide group as a substituent on the heterocycle); and the like. In the exemplary embodiments, the thickness of the hole blocking layer can be about 5 nm to 15 nm, and the thickness of the electron transport layer can be about 20 nm to 50 nm.

[0215] In the exemplary embodiments, the electron injection layer can employ an alkali metal or a metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), and the like material, or a compound of these alkali metal or metal, and the like. In the exemplary embodiments, the thickness of the electron injection layer can be about 0.5 nm to 2 nm.

[0216] (11) Forming a cathode pattern. In the exemplary embodiments, forming the cathode pattern can include forming a cathode 26 pattern on the substrate on which the aforementioned patterns are formed by an evaporation method, as shown in FIG. 6B. Figure 21

[0217] In the exemplary embodiments, the cathode 26 can be formed only in the display area and the circuit area 210, and can be an integral structure connected together. The cathode 26 of the driving area 120 is connected to the organic light emitting layer 25, and the cathode 26 of the circuit area 210 is connected to the organic light emitting layer 25 on one side and connected to the cathode overlap electrode 23 through the connection opening K on the other side. Since the cathode overlap electrode 23 of the circuit area 210 and the cathode overlap area 220 are an integral structure connected to each other, the cathode overlap electrode 23 of the cathode overlap area 220 is overlapped with the second cathode electrode 52, the second cathode electrode 52 is overlapped with the first cathode electrode 51, and the first cathode electrode 51 is overlapped with the power supply line 50, so that the cathode 26 is connected to the power supply line 50 through the cathode overlap electrode 23, the second cathode electrode 52, and the first cathode electrode 51, and the low-level voltage signal is provided to the cathode 26 from the power supply line 50. The present disclosure forms the multi-layer power supply line in parallel structure in the frame area by disposing the power supply line 50, the first cathode electrode 51, and the second cathode electrode 52 in the cathode overlap area 220, which can reduce the resistance of the power supply line, maximally reduces the voltage drop of the voltage signal, improves the display brightness uniformity of the display area, and improves the display quality.

[0218] In the exemplary embodiments, the cathode can employ any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above-mentioned metals.

[0219] ​In the exemplary embodiments, after the cathode is formed, a pattern of an optical coupling layer can be formed on the cathode to improve the coupling-out efficiency of light inside the light-emitting device and facilitate the light-emitting characteristics of the light-emitting device.

[0220] At this point, the first light-emitting structure layer in the display area 100 and the second light-emitting structure layer in the circuit area 210 are prepared. The first light-emitting structure layer can include a plurality of first light-emitting devices, which can include a first anode 21, an organic light-emitting layer 25, and a cathode 26, the organic light-emitting layer 25 being disposed between the first anode 21 and the cathode 26, and the first anode 21 being connected to the first pixel driving circuit in the combined driving area 120. The second light-emitting structure layer can include a plurality of second light-emitting devices and a cathode overlap electrode 23, the second light-emitting devices can include a second anode 22, an organic light-emitting layer 25, and a cathode 26, the organic light-emitting layer 25 being disposed between the second anode 22 and the cathode 26, the second anode 22 being connected to the second pixel driving circuit in the combined driving area 120, and the cathode 26 being connected to the cathode overlap electrode 23.

[0221] (12) Forming a pattern of an encapsulation structure layer. In the exemplary embodiments, forming the pattern of the encapsulation structure layer can include: using an open mask plate to deposit a first encapsulation thin film by a deposition method on the substrate on which the aforementioned patterns are formed, to form a first encapsulation layer 31 in the combined driving area 120, the circuit area 210, the cathode overlap area 220, the partition area 230, and the cutting area 240. Subsequently, using an inkjet printing process to print a second encapsulation thin film, to form a second encapsulation layer 32 in the combined driving area 120, the circuit area 210, and part of the cathode overlap area 220. Subsequently, using an open mask plate to deposit a third encapsulation thin film by a deposition method, to form a third encapsulation layer 33 in the combined driving area 120, the circuit area 210, the cathode overlap area 220, the partition area 230, and the cutting area 240, as shown in FIG. 6. Figure 22

[0222] In the exemplary embodiments, the first encapsulation layer and the third encapsulation layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer, to ensure that water and oxygen from the outside cannot enter the light-emitting structure layer. The second encapsulation layer can be made of a resin material to encapsulate various film layers of the display substrate, to improve the structural stability and flatness.

[0223] ​In the example embodiment, the first encapsulation layer 31 combining the driving region 120 and the circuit region 210 is disposed on the cathode 26, the first encapsulation layer 31 of the cathode overlap region 220 completely covers the isolation dam 90 and the first partition structure 91, the first encapsulation layer 31 of the partition region 230 completely covers the second partition structure 92, and the first encapsulation layer 31 of the cutting region 240 completely covers the third partition structure 93. In the example embodiment, the first encapsulation layer 31 completely covering the isolation dam 90 means that the first encapsulation layer 31 covers all surfaces of the isolation dam 90, and the first encapsulation layer 31 completely covering the first partition structure 91, the second partition structure 92 and the third partition structure 93 means that the first encapsulation layer 31 covers all surfaces exposed by the "T" shaped column.

[0224] In the example embodiment, the second encapsulation layer 32 is disposed on the first encapsulation layer 31 of the driving region 120, the circuit region 210 and part of the cathode overlap region 220 on the side of the isolation dam 90 close to the display region, and fills the partition groove of the first partition structure 91.

[0225] In the example embodiment, on the side of the isolation dam 90 close to the display region, the third encapsulation layer 33 is disposed on the second encapsulation layer 32 to form an inorganic material / organic material / inorganic material laminated structure, which can ensure effective encapsulation. On the side of the isolation dam 90 away from the display region, the third encapsulation layer 33 is disposed on the first encapsulation layer 31 to form an inorganic material / inorganic material laminated structure, which can ensure encapsulation integrity.

[0226] The present disclosure completely covers the isolation dam 90, the first partition structure 91, the second partition structure 92 and the third partition structure 93 by the first encapsulation layer, which not only ensures encapsulation integrity, but also effectively isolates water and oxygen from the cutting region, forms a pinning point for the encapsulation layer, avoids affecting the film layer structure of the circuit region during the cutting process, prevents film layer peeling failure, and can cut off the crack transmission to the circuit region.

[0227] In the example embodiment, after the encapsulation structure layer is prepared, a touch structure layer (TSP) can be formed on the encapsulation structure layer. The touch structure layer can include a touch electrode layer, or include a touch electrode layer and a touch insulating layer, which are not limited in the present disclosure.

[0228] The structure of the substrate and the preparation process thereof in the present disclosure are only exemplary descriptions. In the example embodiment, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. For example, the anode connecting line can be disposed only in the second source / drain metal layer, or the anode connecting line can be disposed only in the third source / drain metal layer, which are not limited in the present disclosure.

[0229] As can be seen from the structure and preparation process of the display substrate according to the exemplary embodiments of the present disclosure, the exemplary embodiments of the present disclosure effectively increase the display area of the display device by arranging the light emitting device in the frame area, correspondingly reduce the area of the non-display area of the display device, and minimize the frame width of the display device, which can be reduced to about 0.3-0.4 mm, thereby realizing narrow frame of the display device.

[0230] The present disclosure sets the second light emitting structure layer in the circuit area of the frame area, the second light emitting structure layer includes a plurality of second light emitting devices, and sets the combined driving area in the display area, the combined driving area sets the second pixel driving circuit for driving the plurality of second light emitting devices, which can realize display in the frame area and avoid the influence of the second light emitting device on the structure of the gate driving circuit in the circuit area, and has the characteristics of simple structure and reasonable layout.

[0231] The present disclosure sets the anode connecting line to realize the connection between the second light emitting device in the circuit area and the pixel driving circuit in the combined driving area, and the plurality of anode connecting lines can be arranged in the two conductive layers, which can not only increase the number of anode connecting lines, but also reduce the arrangement pressure of the anode connecting lines.

[0232] The present disclosure sets the cathode overlap electrode with a larger area in the circuit area, and the whole surface structure of the cathode overlap electrode is a hollow structure, and the second anode is arranged in the hollow area, which not only realizes the light emission of the light emitting device in the circuit area, but also increases the area of the cathode overlap electrode and improves the reliability of the cathode overlap.

[0233] The present disclosure forms the partition structure of the “T” shaped column in the cathode overlap area, the partition area and the cutting area 240, which can not only effectively block the water and oxygen from the cutting area, but also can avoid affecting the film structure of the circuit area in the cutting process, can reduce the stress of the circuit area, can cut off the crack transmission to the circuit area, and can reduce the overall width of the frame area due to the improved packaging reliability, which is beneficial to realize narrow frame.

[0234] The present disclosure sets the stacked power lines, the first cathode electrode and the second cathode electrode in the frame area, forms the parallel structure of the multi-layer power lines in the frame area, which can reduce the resistance of the power lines, maximally reduces the voltage drop of the voltage signal, improves the display brightness uniformity of the display area, and improves the display quality.

[0235] The preparation process of the display substrate according to the exemplary embodiments of the present disclosure has good process compatibility, simple process implementation, high production efficiency, low production cost and high yield.

[0236] The exemplary embodiments of the present disclosure also provide a preparation method of a display substrate for preparing the aforementioned display substrate. In the exemplary embodiments, the display substrate comprises a display area and a frame area located at at least one side of the display area, and the preparation method can comprise:

[0237] forming a driving structure layer and a circuit structure layer in the display area and the frame area respectively; the driving structure layer comprises a plurality of circuit units, and at least one circuit unit comprises a first pixel driving circuit and a second pixel driving circuit;

[0238] forming a first light-emitting structure layer and a second light-emitting structure layer in the display area and the frame area respectively; the first light-emitting structure layer comprises a plurality of first light-emitting devices, and the second light-emitting structure layer comprises a plurality of second light-emitting devices; the first light-emitting devices are connected with the first pixel driving circuit, and the second light-emitting devices are connected with the second pixel driving circuit.

[0239] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiments. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0240] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized by, The display region and the frame region located at least one side of the display region; In a plane perpendicular to the display substrate, the display region comprises a driving structure layer disposed on a substrate and a first light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, and the first light-emitting structure layer comprises a plurality of first light-emitting devices; The frame region comprises a circuit structure layer disposed on a substrate and a second light-emitting structure layer disposed on a side of the circuit structure layer away from the substrate, and the second light-emitting structure layer comprises a plurality of second light-emitting devices; The driving structure layer comprises a plurality of circuit units, at least one circuit unit comprises a first pixel driving circuit and a second pixel driving circuit, the first light-emitting device is connected with the first pixel driving circuit, and the second light-emitting device of the frame region is connected with the second pixel driving circuit of the display region; In a plane perpendicular to the display substrate, the display region comprises a driving structure layer disposed on a substrate and a first light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, and the first light-emitting structure layer comprises a plurality of first light-emitting devices; 2. The display substrate of claim 1, wherein, The display region comprises a normal driving area and a combined driving area, the combined driving area is arranged between the normal driving area and the frame region, the circuit unit of the normal driving area comprises a first pixel driving circuit, and the circuit unit of the combined driving area comprises a first pixel driving circuit and a second pixel driving circuit.

3. The display substrate of claim 1, wherein, The first light-emitting device comprises a first pixel opening defining a light-emitting region, and the second light-emitting device comprises a second pixel opening defining a light-emitting region; the distance between adjacent second pixel openings in the frame region is greater than or equal to the distance between adjacent first pixel openings in the display region, and the distance is the distance between the geometric centers of the pixel openings.

4. The display substrate of claim 3, wherein, In the frame region, the distance between adjacent second pixel openings gradually increases in a direction away from the display region.

5. The display substrate of claim 1, wherein, The first light-emitting device comprises a first pixel opening defining a light-emitting region, and the second light-emitting device comprises a second pixel opening defining a light-emitting region; the area of the second pixel opening in the frame region is less than or equal to the area of the first pixel opening in the display region. 6.The display substrate of claim 5, wherein, In the frame region, the area of the second pixel opening gradually decreases in a direction away from the display region.

7. The display substrate according to any one of claims 1 to 6, characterized in that, The second light-emitting device of the frame region is connected with the second pixel driving circuit of the display region through an anode connection line. 8.The display substrate of claim 7, wherein, The circuit structure layer of the frame region comprises at least a first source-drain metal layer and a second source-drain metal layer, and the anode connection line is disposed in the second source-drain metal layer. 9.The display substrate of claim 7, wherein, The circuit structure layer of the frame region comprises at least a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer, and the anode connection line is disposed in the third source-drain metal layer. 10.The display substrate of claim 7, wherein, The circuit structure layer of the frame area at least includes a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer, the anode connecting line includes a first anode connecting line and a second anode connecting line, the first anode connecting line is arranged in the second source-drain metal layer, and the second anode connecting line is arranged in the third source-drain metal layer. 11.The display substrate according to any one of claims 1 to 6, characterized in that, The second light-emitting structure layer of the frame area includes, in sequence on the circuit structure layer, an anode conductive layer, a pixel definition layer, an organic light-emitting layer and a cathode; the anode conductive layer includes a cathode overlap electrode and at least one second anode, the cathode overlap electrode is provided with a hollow area, and at least one second anode is arranged in the hollow area; The pixel definition layer is provided with a second pixel opening and a connecting opening, the second pixel opening exposes the second anode, and the connecting opening exposes the cathode overlap electrode; the organic light-emitting layer is connected with the second anode through the second pixel opening, the cathode is connected with the organic light-emitting layer, and the cathode is connected with the cathode overlap electrode through the connecting opening.

12. A display device comprising the display substrate according to any one of claims 1 to 11.

13. A method for manufacturing a display substrate, the display substrate comprising a display area and a frame area located at least one side of the display area; the method comprising: forming a driving structure layer and a circuit structure layer in the display area and the frame area respectively; the driving structure layer comprises a plurality of circuit units, and at least one circuit unit comprises a first pixel driving circuit and a second pixel driving circuit; forming a first light-emitting structure layer and a second light-emitting structure layer in the display area and the frame area respectively; the first light-emitting structure layer comprises a plurality of first light-emitting devices, and the second light-emitting structure layer comprises a plurality of second light-emitting devices, the first light-emitting devices are connected with the first pixel driving circuit, and the second light-emitting devices in the frame area are connected with the second pixel driving circuit in the display area; wherein, along a direction away from the display area, the frame area comprises, in sequence, a circuit area, a cathode overlap area, a partition area and a cutting area, the circuit area comprises a gate driving circuit and the plurality of second light-emitting devices; the cathode overlap area comprises a power line, an isolation dam and a first partition structure; the partition area comprises a second partition structure; and the cutting area comprises a third partition structure.

Images