A Low Dropout Linear Regulator and Its Error Amplifier

Abstract

The present application provides a low dropout linear regulator and its error amplifier. The error amplifier includes an input stage and an output stage connected to the input stage. Among them, the input stage adopts a push-pull output architecture, which is used to output a push-pull voltage according to the reference voltage, feedback voltage and output voltage of the low dropout linear regulator received. The output stage adopts a common-drain architecture, and the current source in the output stage is in the nanoampere level, which is used to output an error amplified voltage according to the received push-pull voltage. That is to say, the input stage in the error amplifier of the low dropout linear regulator provided by the present application adopts a push-pull output architecture, which can meet the high breakdown voltage requirement; while the output stage adopts a common-drain architecture, and the current source in the output stage is in the nanoampere level, which can achieve low static power consumption, solving the problem that the existing low dropout linear regulator cannot reduce the static power consumption while having a high breakdown voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and particularly to a low dropout regulator and its error amplifier. Background Art

[0002] As is well known, a low dropout regulator (LDO) is a very important type in the power management product category. Such products are widely used in electronic products such as mobile phones, computers, and tablets. Due to its advantages of small ripple and low noise, it is widely used for power supply in circuits with high requirements for noise and interference.

[0003] The design requirements of a low dropout regulator are to be stable within the full load range, and at the same time, specific requirements include high PSRR (Power Supply Rejection Ratio), low-noise output, and fast transient response, etc. Therefore, the low dropout regulator has been making trade-offs among these parameter performances.

[0004] As the requirements for static power consumption of electronic products are getting lower and lower, extremely low power consumption has increasingly become one of the key parameters considered in the design of low dropout regulators. At the same time, applications in fields such as household appliances, industrial control, and automotive electronics also have requirements for the withstand voltage of the input power supply. How to achieve high withstand voltage while reducing static power consumption is an urgent problem to be solved by current low dropout regulators. Summary of the Invention

[0005] In view of this, the present application provides a low dropout regulator and its error amplifier to solve the problem that the existing low dropout regulator cannot reduce static power consumption while achieving high withstand voltage.

[0006] To achieve the above object, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of the present invention discloses an error amplifier of a low dropout regulator, including: an input stage and an output stage connected to the input stage; wherein:

[0008] The input stage adopts a push-pull output architecture and is used to output a push-pull voltage according to the reference voltage, feedback voltage, and output voltage of the low dropout regulator received.

[0009] The output stage adopts a common-drain architecture, and the current source in the output stage is in the nanoampere level and is used to output an error amplification voltage according to the received push-pull voltage.

[0010] Optionally, in the error amplifier of the above low dropout linear regulator, the input stage includes: a first current source, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a first capacitor, a first high-voltage switching transistor, and a second high-voltage switching transistor; where:

[0011] The control terminal of the first switching transistor serves as the first input terminal of the input stage and receives the reference voltage of the low dropout linear regulator; the first terminal of the first switching transistor is respectively connected to the first terminal of the second switching transistor and one end of the first current source; the second terminal of the first switching transistor is respectively connected to the control terminal of the fifth switching transistor, the second terminal of the fifth switching transistor, and the control terminal of the sixth switching transistor;

[0012] The control terminal of the second switching transistor serves as the second input terminal of the input stage and receives the feedback voltage of the low dropout linear regulator; the first terminal of the second switching transistor is respectively connected to the control terminal of the seventh switching transistor, the second terminal of the seventh switching transistor, and the control terminal of the eighth switching transistor;

[0013] The first terminals of the fifth switching transistor, the sixth switching transistor, the seventh switching transistor, and the eighth switching transistor are connected together and grounded;

[0014] The second terminal of the sixth switching transistor is connected to the first terminal of the first high-voltage switching transistor, and the control terminals of the first high-voltage switching transistor and the second high-voltage switching transistor are connected;

[0015] The second terminal of the first high-voltage switching transistor is respectively connected to the control terminal and the second terminal of the third switching transistor;

[0016] The first terminal of the third switching transistor is respectively connected to the other end of the first current source and the first terminal of the fourth switching transistor;

[0017] The second terminal of the fourth switching transistor is connected to the second terminal of the second high-voltage switching transistor, and the connection point serves as the output terminal of the input stage to output the push-pull voltage;

[0018] The first terminal of the second high-voltage switching transistor is respectively connected to the second terminal of the eighth switching transistor and one end of the first capacitor, and the other end of the first capacitor serves as the third input terminal of the input stage to receive the output voltage of the low dropout linear regulator.

[0019] Optionally, in the error amplifier of the above low dropout linear regulator, the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all PMOS transistors;

[0020] The fifth switching transistor, the sixth switching transistor, the seventh switching transistor, and the eighth switching transistor are all NMOS transistors.

[0021] Optionally, in the error amplifier of the above low dropout linear regulator, the output stage includes: a second current source, a third current source, and a third high-voltage switching transistor; where:

[0022] The control terminal of the third high-voltage switching transistor serves as the input terminal of the output stage and receives the push-pull voltage;

[0023] The first terminal of the third high-voltage switching transistor is connected to one end of the second current source, and the connection point serves as the output terminal of the output stage to output an error amplification voltage;

[0024] The other end of the second current source is connected to the first terminal of the fourth switching transistor;

[0025] The second terminal of the third high-voltage switching transistor is grounded through the third current source.

[0026] Optionally, in the error amplifier of the above low dropout linear regulator, the first current source and the second current source are at the nanoampere level.

[0027] Optionally, in the error amplifier of the above low dropout linear regulator, the output stage further includes: a super follower circuit;

[0028] The super follower circuit is based on the common-drain stage architecture and is used to improve the slew rate of the error amplification voltage output by the output stage.

[0029] Optionally, in the error amplifier of the above low dropout linear regulator, the super follower circuit includes: a fourth high-voltage switching transistor, a ninth switching transistor, a tenth switching transistor, a first resistor, and a second capacitor; where:

[0030] The control terminal of the ninth switching transistor is respectively connected to one end of the second current source, the first terminal of the third high-voltage switching transistor, the second terminal of the ninth switching transistor, and the second terminal of the fourth high-voltage switching transistor;

[0031] The first terminal of the ninth switching transistor is connected to the other end of the second current source;

[0032] The first terminal of the fourth high-voltage switching transistor is connected to the second terminal of the tenth switching transistor. The control terminal of the tenth switching transistor is respectively connected to the second terminal of the third high-voltage switching transistor, one end of the third current source, and one end of the first resistor; the first terminal of the tenth switching transistor is grounded;

[0033] The other end of the first resistor is grounded through the second capacitor.

[0034] Optionally, in the error amplifier of the low dropout linear regulator described above, the ninth switching transistor is a PMOS transistor, and the tenth switching transistor is an NMOS transistor.

[0035] Optionally, in the error amplifier of the low dropout linear regulator described above, it further includes: an input stage withstand voltage circuit for performing withstand voltage protection on the input stage.

[0036] Optionally, in the error amplifier of the low dropout linear regulator described above, the input stage withstand voltage circuit includes: a zener diode;

[0037] Wherein, the anode of the zener diode is connected to the output terminal of the input stage, and the cathode of the zener diode is connected to the first terminal of the fourth switching transistor in the input stage.

[0038] Optionally, in the error amplifier of the low dropout linear regulator described above, it further includes: a phase margin optimization circuit for adjusting the phase margin of the error amplifier according to the load change.

[0039] Optionally, in the error amplifier of the low dropout linear regulator described above, the phase margin optimization circuit includes: a third capacitor, a fourth capacitor and a variable resistor; wherein:

[0040] One end of the third capacitor is connected to one end of the variable resistor, and the connection point is connected to the first terminal of the fourth switching transistor in the input stage;

[0041] The other end of the variable resistor is connected to one end of the fourth capacitor;

[0042] The other end of the fourth capacitor is connected to the other end of the third capacitor, and the connection point is connected to the output terminal of the input stage.

[0043] The second aspect of the present invention discloses a low dropout linear regulator, including: a feedback circuit, a power stage, and an error amplifier of the low dropout linear regulator according to any one of the first aspect; wherein:

[0044] The power stage is used to output a regulated voltage signal to supply power to the load according to the error amplified voltage output by the error amplifier and the power supply, and output the regulated voltage signal to the error amplifier;

[0045] The feedback circuit is used to sample the regulated voltage signal output by the power stage and output the sampled feedback voltage to the error amplifier;

[0046] The error amplifier is used to generate the error amplified voltage according to the received reference voltage, the feedback voltage and the regulated voltage signal.

[0047] Optionally, in the above-mentioned low-dropout linear regulator, it further includes: a zero-point compensation circuit for performing zero-point compensation on the low-dropout linear regulator.

[0048] Optionally, in the above-mentioned low-dropout linear regulator, the zero-point compensation circuit includes: a capacitor and a resistor; wherein:

[0049] One end of the resistor is connected to the output end of the power stage, and the other end of the resistor is grounded through the capacitor.

[0050] The error amplifier of the low-dropout linear regulator provided by the present invention includes: an input stage and an output stage connected to the input stage; wherein, the input stage adopts a push-pull output architecture for outputting a push-pull voltage according to the reference voltage, feedback voltage and output voltage of the received low-dropout linear regulator; the output stage adopts a common-drain architecture, and the current source in the output stage is in the nanoampere level for outputting an error amplification voltage according to the received push-pull voltage; that is, the input stage in the error amplifier of the low-dropout linear regulator provided by the present application adopts a push-pull output architecture, which can meet the high breakdown voltage requirement; while the output stage adopts a common-drain architecture, and the current source in the output stage is in the nanoampere level, which can achieve low static power consumption, solving the problem that the existing low-dropout linear regulator cannot reduce the static power consumption while having a high breakdown voltage. Description of the Drawings

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0052] Figure 1 It is a schematic structural diagram of an error amplifier of a low-dropout linear regulator provided by an embodiment of the present application;

[0053] Figure 2 and Figure 3 It is a circuit diagram of two error amplifiers of a low-dropout linear regulator provided by an embodiment of the present application;

[0054] Figure 4 and Figure 5 It is a schematic structural diagram of a low-dropout linear regulator provided by an embodiment of the present application;

[0055] Figure 6 It is a schematic structural diagram of an existing low-dropout linear regulator provided by an embodiment of the present application. Detailed Embodiments

[0056] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0057] First of all, it should be noted that the error amplifier in the low dropout linear regulator determines the performance parameters of the low dropout linear regulator and is a crucial device in the low dropout linear regulator. Through research by the inventor, it is found that if one wants to improve the high-voltage resistance performance of the low dropout linear regulator and reduce power consumption, it is necessary to first improve the high-voltage resistance performance of the error amplifier in the low dropout linear regulator and reduce the power consumption of the error amplifier.

[0058] In this regard, the embodiments of the present application provide an error amplifier for a low dropout linear regulator to solve the problem that the existing low dropout linear regulator cannot reduce the static power consumption while having high voltage resistance.

[0059] Please refer to Figure 1 , the error amplifier of the low dropout linear regulator mainly includes: an input stage 101 and an output stage 102 connected to the input stage 101. Among them:

[0060] The input stage 101 adopts a push-pull output (Push-Pull) architecture and is used to output a push-pull voltage according to the reference voltage ( Figures 1 to 6 VREF in Figures 1 to 6 ), feedback voltage ( Figures 1 to 6 VFB in

[0061] ), and output voltage (

[0062] VC in Figure 2 or Figure 3 ) received by the low dropout linear regulator.

[0063] The control terminal of the first switching transistor MP1 serves as the first input terminal of the input stage 101 and receives the reference voltage of the low dropout linear regulator; the first terminal of the first switching transistor MP1 is connected to the first terminal of the second switching transistor MP2 and one end of the first current source I1 respectively; the second terminal of the first switching transistor MP1 is connected to the control terminal of the fifth switching transistor MN1, the second terminal of the fifth switching transistor MN1 and the control terminal of the sixth switching transistor MN2 respectively.

[0064] The control terminal of the second switching transistor MP2 serves as the second input terminal of the input stage 101 and receives the feedback voltage of the low dropout linear regulator; the second terminal of the second switching transistor MP2 is connected to the control terminal of the seventh switching transistor MN3, the second terminal of the seventh switching transistor MN3 and the control terminal of the eighth switching transistor MN4 respectively.

[0065] The first terminals of the fifth switching transistor MN1, the sixth switching transistor MN2, the seventh switching transistor MN3 and the eighth switching transistor MN4 are connected together and grounded.

[0066] The second terminal of the sixth switching transistor MN2 is connected to the first terminal of the first high-voltage switching transistor MNH1, and the control terminals of the first high-voltage switching transistor MNH1 and the second high-voltage switching transistor MNH2 are connected together.

[0067] The second terminal of the first high-voltage switching transistor MNH1 is connected to the control terminal of the third switching transistor MP3, the second terminal of the third switching transistor MP3 and the control terminal of the fourth switching transistor MP4 respectively.

[0068] The first terminal of the third switching transistor MP3 is connected to the other end of the first current source I1 and the first terminal of the fourth switching transistor MP4 respectively.

[0069] The second terminal of the fourth switching transistor MP4 is connected to the second terminal of the second high-voltage switching transistor MNH2, and the connection point serves as the output terminal of the input stage 101 to output the push-pull voltage.

[0070] The first terminal of the second high-voltage switching transistor MNH2 is connected to the second terminal of the eighth switching transistor MN4 and one end of the first capacitor Cc respectively, and the other end of the first capacitor Cc serves as the third input terminal of the input stage 101 to receive the output voltage of the low dropout linear regulator.

[0071] In practical applications, the first switching transistor MP1, the second switching transistor MP2, the third switching transistor MP3 and the fourth switching transistor MP4 are all PMOS transistors.

[0072] The fifth switching transistor MN1, the sixth switching transistor MN2, the seventh switching transistor MN3, the eighth switching transistor MN4 are all NMOS transistors.

[0073] It should be noted that Figure 2 or Figure 3One end of the switching transistor in [description] with an arrow is the source electrode, and the end without an arrow is the drain electrode; in the embodiment, the first end is the source electrode, the second end is the drain electrode, and the control end is the gate electrode.

[0074] It should be noted that the first current source I1 is set to operate in the low-voltage power supply domain, and the generation of the low-voltage input power supply received by the first current source I1 depends on the conversion circuit of the external high-voltage to low-voltage domain VPRE voltage (the voltage at the control ends of the first high-voltage switching transistor MNH1 and the second high-voltage switching transistor MNH2). The input stage 101 of the error amplifier operates in the low-voltage domain, and each device in the input stage 101 has no withstand voltage problem. The first switching transistor MP1 and the second switching transistor MP2 are used as input pair transistors, and generally adopt a common PMOS structure.

[0075] In practical applications, when the error amplifier is powered on, after the reference voltage of the low-dropout linear regulator is powered on and established, the PMOS input pair transistors ( Figure 2 or Figure 3 the first switching transistor MP1 and the second switching transistor MP2 in [description]) in [description] will follow the establishment of the reference voltage, and at the same time, the VPRE voltage will also follow the establishment of the reference voltage. Since the first high-voltage switching transistor MNH1 and the second high-voltage switching transistor MNH2 are high-voltage withstand NMOS transistors, when applying the push-pull output architecture, the high voltage completely depends on the first high-voltage switching transistor MNH1 and the second high-voltage switching transistor MNH2. Since the voltages of the seventh switching transistor MN3 and the eighth switching transistor MN4 will be clamped by the VPRE voltage, the seventh switching transistor MN3 and the eighth switching transistor MN4 have no withstand voltage requirements. Similarly, the third switching transistor MP3, due to the connection method of diode (the gate is connected to the source), its gate-source voltage VGS is also high-voltage withstand.

[0076] It should be noted that both the first high-voltage switching transistor MNH1 and the second high-voltage switching transistor MNH2 are high-voltage withstand NMOS transistors. Among them, the first end of the first high-voltage switching transistor MNH1 represents the source electrode, that is, the end with an arrow in the figure; the second end of the second high-voltage switching transistor MNH1 represents the drain electrode, that is, the end without an arrow in the figure; the control end of the first high-voltage switching transistor MNH1 represents the gate electrode. The first end of the second high-voltage switching transistor MNH2 represents the source electrode, that is, the end with an arrow in the figure; the second end of the second high-voltage switching transistor MNH2 represents its drain electrode, that is, the end without an arrow in the figure; the control end of the second high-voltage switching transistor MNH2 represents the gate electrode.

[0077] It should also be noted that in practical applications, in order to provide withstand voltage protection for the input stage 101, the error amplifier of this low-dropout linear regulator further includes: an input stage withstand voltage circuit for providing withstand voltage protection for the input stage 101.

[0078] Such as Figure 2 or Figure 3As shown, the input-stage withstand-voltage circuit includes: a zener diode. Among them, the anode of the zener diode is connected to the output terminal of the input stage 101, and the cathode of the zener diode is connected to the fourth switching transistor MP3 in the input stage 101.

[0079] It can be understood that the zener diode clamps the drain-source voltage VDS of the fourth switching transistor MP4 in the input stage 101, improving the withstand voltage of the fourth switching transistor MP4.

[0080] The output stage 102 adopts a common-drain (Common-drai) architecture, and the current source in the output stage is at the nanoampere (nA) level, and is used to output an error amplification voltage according to the received push-pull voltage.

[0081] It should be noted that the output stage 102 can also be referred to as the second stage of the error amplifier, and adopts a common-drain architecture as a buffer (buffer) stage output.

[0082] In practical applications, combined with Figure 2 or Figure 3 , the output stage 102 mainly includes: a second current source I2, a third current source I3, and a third high-voltage switching transistor MPH1. Among them:

[0083] The control terminal of the third high-voltage switching transistor MPH1 serves as the input terminal of the output stage 102 to receive the push-pull voltage.

[0084] The first terminal of the third high-voltage switching transistor MPH1 is connected to one end of the second current source I2, and the connection point serves as the output terminal of the output stage 102 to output an error amplification voltage. The other end of the second current source I2 is connected to the first terminal of the fourth switching transistor MP4.

[0085] The second terminal of the third high-voltage switching transistor MPH1 is grounded through the third current source I3.

[0086] It should be noted that the third high-voltage switching transistor MPH1 is a high-voltage-resistant PMOS transistor. Among them, the first terminal of the third high-voltage switching transistor MPH1 represents the source electrode, that is, the end with an arrow in the figure; the second terminal of the third high-voltage switching transistor MPH1 represents the drain electrode, that is, the end without an arrow in the figure; the control terminal of the third high-voltage switching transistor MPH1 represents the gate electrode.

[0087] The input stage 101 outputs a push-pull voltage to the gate of the third high-voltage switching transistor MPH1, and the third high-voltage switching transistor MPH1 itself operates in a high-voltage domain and has a high withstand voltage.

[0088] In practical applications, the error amplification voltage output by the output stage 102 will raise the push-pull voltage output by the input stage 101 by the gate-source voltage VGS corresponding to the third high-voltage switching transistor MPH1, thereby driving the gate of the power stage in the low-dropout linear regulator.

[0089] It should also be noted that, in order to reduce the static power consumption of the error amplifier, the first current source I1 and the second current source I2 are generally set to the nanoampere level.

[0090] Based on the above principle, the error amplifier of the low dropout linear regulator provided in this embodiment includes: an input stage and an output stage connected to the input stage; wherein, the input stage adopts a push-pull output architecture and is used to output a push-pull voltage according to the reference voltage, feedback voltage and output voltage of the low dropout linear regulator received; the output stage adopts a common-drain architecture, and the current source in the output stage is at the nanoampere level and is used to output an error amplified voltage according to the received push-pull voltage; that is, the input stage in the error amplifier of the low dropout linear regulator provided in this application adopts a push-pull output architecture, which can meet the high breakdown voltage requirement; while the output stage adopts a common-drain architecture, and the current source in the output stage is at the nanoampere level, which can achieve low static power consumption, solving the problem that the existing low dropout linear regulator cannot reduce the static power consumption while having a high breakdown voltage.

[0091] Moreover, in the actual application process, the first capacitor Cc can be used as a compensation capacitor. Since its capacitance value is small, it can save area.

[0092] Optionally, in the error amplifier of the low dropout linear regulator provided in this application, it further includes: a phase margin optimization circuit, which is used to adjust the phase margin of the error amplifier according to the load change.

[0093] Please refer to Figure 2 or Figure 3 , the phase margin optimization circuit mainly includes: a third capacitor C1, a fourth capacitor C2 and a variable resistor R1. Among them:

[0094] One end of the third capacitor C1 is connected to one end of the variable resistor R1, and the connection point is connected to the first end of the fourth switching transistor MP4 in the input stage 101.

[0095] The other end of the variable resistor R1 is connected to one end of the fourth capacitor C2.

[0096] The other end of the fourth capacitor C2 is connected to the other end of the third capacitor C1, and the connection point is connected to the output end of the input stage 101.

[0097] It should be noted that, in the actual application, the compensation network in this low dropout linear regulator adopts a dynamic NULL resistor compensation method, that is, the error amplifier uses the variable resistor R1 for compensation, and adjusts the variable resistor R1 according to the load change to optimize the phase margin.

[0098] It should also be noted that the specific method of adjusting the optimized phase margin of the adjustable resistor R1 according to the load change is determined according to the specific application environment and user requirements, and is not specifically limited in this application, and all belong to the protection scope of this application.

[0099] In practical applications, since the power stage of the low-dropout linear regulator is generally composed of a large-area PMOS array, the large-area power stage will cause a relatively large parasitic capacitance, seriously affecting the slew rate of the low-dropout linear regulator. Therefore, it also limits the static operating currents of the first current source and the second current source, resulting in poor transient response performance of the low-dropout linear regulator; moreover, due to the need to perform low-power design, the values of the first current source and the second current source are both in the nanoampere level, which will also result in the sacrifice of transient response characteristics.

[0100] In this regard, on the basis of Figure 2 , please refer to Figure 3 , the output stage provided by this application further includes: a super follower circuit; wherein, the super follower circuit is based on a common-drain stage architecture and is used to improve the slew rate of the error amplification voltage output by the output stage.

[0101] As Figure 3 shown, the super follower circuit mainly includes: a fourth high-voltage switching transistor MNH3, a ninth switching transistor MP5, a tenth switching transistor MN5, a first resistor R2, and a second capacitor C3. Among them:

[0102] The control terminal of the ninth switching transistor MP5 is respectively connected to one end of the second current source I2, the first end of the third high-voltage switching transistor MNH1, the second end of the ninth switching transistor MP5, and the second end of the fourth high-voltage switching transistor MNH3.

[0103] The first end of the ninth switching transistor MP5 is connected to the other end of the second current source I2.

[0104] The first end of the fourth high-voltage switching transistor MNH3 is connected to the second end of the tenth switching transistor MN5. The control terminal of the tenth switching transistor MN5 is respectively connected to the second end of the third high-voltage switching transistor MNH1, one end of the third current source I3, and one end of the first resistor R2; the first end of the tenth switching transistor MN5 is grounded.

[0105] The other end of the first resistor R1 is grounded through the second capacitor C3.

[0106] In practical applications, the fourth high-voltage switching transistor MNH3 in the super follower circuit generally uses a high-voltage-resistant NMOS transistor, which has good high-voltage resistance performance. The tenth switching transistor MN5 and the fourth high-voltage switching transistor MNH3 serve as a feedback introduction branch; the ninth switching transistor MP5 is used to detect the load current and dynamically adjust the current flowing into the tenth switching transistor MN5.

[0107] It should be noted that in practical applications, the ninth switching transistor MP5 is a PMOS transistor, and the tenth switching transistor MN5 is an NMOS transistor. Among them, the first end of the ninth switching transistor MP5 is the source electrode, that is, the end with an arrow in the figure; the second end of the ninth switching transistor MP5 is the drain electrode, that is, the end without an arrow in the figure; the control end of the ninth switching transistor MP5 is the gate electrode. The first end of the tenth switching transistor MN5 is the source electrode, that is, the end with an arrow in the figure; the second end of the tenth switching transistor MN5 is the drain electrode, that is, the end without an arrow in the figure; the control end of the tenth switching transistor MN5 is the gate electrode.

[0108] Combined with Figure 3 , after adding a super follower circuit to the output stage 102, the working principle of the super follower circuit is as follows:

[0109] The current flowing through the third high-voltage switching transistor MNH1 is determined by the third current source I3. The current flowing through the tenth switching transistor MN5 is the sum of the second current source I2 and the current flowing through the ninth switching transistor MP5 minus the third current source I3, and its mathematical expression can be: IN5 = I2 - I3 + IP5; where, IN5 represents the current flowing through the tenth switching transistor MN5, I2 represents the second current source I2, I3 represents the third current source I3, and IP5 represents the current flowing through the ninth switching transistor MP5.

[0110] It should be noted that when the low-dropout linear regulator operates in the no-load mode, that is, when IL = 0, the signal sampled by the current flowing through the ninth switching transistor MP5 is almost 0. At this time, the current of the error amplifier is determined by the sum of the second current source I2 and the third current source I3, so as to achieve low power consumption under no load.

[0111] When the low-dropout linear regulator operates in the heavy-load mode, for example, when IL = 300 mA, the current flowing through the ninth switching transistor MP5 will increase, and the increased current signal is beneficial to improving the transient response slew rate. Moreover, the super follower circuit also introduces a first resistor R2 and a second capacitor C3 as a zero-pole pair, which will compensate the small loop of the super follower circuit and reduce the impact on the transient response.

[0112] Based on the above principle, after adding a super follower circuit to the output stage 102, the index of the load transient response of the low-dropout linear regulator can be greatly improved by using the dynamic current biasing principle of the super follower circuit; in addition, the low-dropout linear regulator provided in this application can also take into account performance index parameters such as PSRR and noise performance at the same time.

[0113] Optionally, another embodiment of this application also provides a low-dropout linear regulator, please refer to Figure 4 , the low-dropout linear regulator mainly includes: a feedback circuit, a power stage ( Figure 4MP1) in it and the error amplifier of the low dropout linear regulator as described in any of the above embodiments Figure 4 ERRAMP) in it; wherein:

[0114] The power stage is used to output a regulated signal to supply power to the load according to the error amplified voltage output by the error amplifier and the power supply, and output the regulated signal to the error amplifier.

[0115] In practical applications, the power stage is generally composed of a PMOS array with a large area size, and its main function is to output a stable signal to supply power to the load. Figure 4 Only one PMOS transistor is taken as an example. It should be noted that the source of the PMOS transistor is connected to the power supply, the gate of the PMOS transistor receives the error amplified voltage output by the error amplifier, and the drain of the PMOS transistor is used as the output terminal of the power stage to output the regulated signal.

[0116] The feedback circuit is used to sample the regulated signal output by the power stage and output the sampled feedback voltage to the error amplifier.

[0117] In practical applications, similarly as Figure 4 or Figure 5 shown, the feedback circuit mainly includes: a first feedback resistor RF1 and a second feedback resistor RF2; wherein, one end of the first feedback resistor RF1 receives the regulated signal; the other end of the first feedback resistor RF1 is connected to one end of the second feedback resistor RF2, and the connection point is used as the output terminal of the feedback circuit to output the feedback voltage Figure 4 or Figure 5 VFB) in it; the other end of the second feedback resistor RF2 is grounded.

[0118] It should be noted that the feedback resistor is determined by the first feedback resistor RF1 and the second feedback resistor RF2. Its main function is to collect the voltage of the regulated signal and generate a feedback voltage through the voltage division ratio for the error amplifier to compare with the reference voltage, so as to adjust the magnitude of the error amplified signal input to the power stage, adjust the output current of the power stage, and play the role of a negative feedback network.

[0119] The error amplifier is used to generate and output an error amplified voltage to the power stage according to the received reference voltage Figure 4 VREF) in it, the feedback voltage Figure 4 VFB) in it, and the regulated signal Figure 4 VC) in it.

[0120] In practical applications, in combination with Figures 1 to 4 , the port of the error amplifier receiving the reference voltage is the inverting input terminal, and the ports receiving the feedback voltage and the regulated signal are both non-inverting input terminals.

[0121] In practical applications, feeding back the regulated signal output by the power stage to the error amplifier can play a role in frequency compensation, further improving the stability of the loop of the entire low-dropout linear regulator.

[0122] It should be noted that for the related descriptions of the low-dropout linear regulator, reference can also be made to the prior art, which will not be elaborated in this application and all fall within the protection scope of this application. For the related descriptions of the error amplifier, refer to Figures 1 to 3 the corresponding embodiments, and will not be elaborated here.

[0123] Optionally, on the basis of Figure 4 , please refer to Figure 5 , the low-dropout linear regulator further includes: a current limiting circuit (CURRENT LIMIT in Figure 5 ) connected to both the error amplifier and the power stage, configured to collect the regulated signal output by the power stage and clamp the error amplified voltage output by the error amplifier when the regulated signal is greater than a preset current limit value.

[0124] Combined with Figure 5 , it can be understood that the current limiting circuit can take effect after the load current is greater than the preset current limit value, limiting the error amplified voltage output by the error amplifier, so that the gate-source voltage VGS of the power stage is clamped at a fixed value, achieving the effect of current limiting.

[0125] Optionally, the low-dropout linear regulator provided in the embodiment of this application further includes: a zero point compensation circuit for performing zero point compensation on the low-dropout linear regulator.

[0126] Similarly, please refer to Figure 4 or Figure 5 , the zero point compensation circuit mainly includes: a capacitor CL and a resistor Resr; where: one end of the resistor Resr is connected to the output end of the power stage, and the other end of the resistor Resr is grounded through the capacitor CL.

[0127] In practical applications, the capacitor CL can be an external capacitor, which generally uses a ceramic capacitor; of course, it is not limited thereto, and can also be determined according to the specific application environment and user requirements, and this application does not make specific limitations, all of which fall within the protection scope of this application.

[0128] The resistor Resr can be an equivalent series resistance, and the variation range of the resistor Resr can be in the range of 10 mΩ to 2 Ω. When the resistor Resr is relatively large, it provides a compensation zero point for the loop of the low-dropout linear regulator.

[0129] Finally, it is worth noting that there is also a type of low-dropout linear regulator existing in the prior art, such as Figure 6As shown. The low-dropout linear regulator uses devices Q1 and Q2 with high-voltage-tolerant gates. Although high-voltage tolerance is achieved, there are usage limitations on the process; while the low-dropout linear regulator provided by this application can achieve high-voltage tolerance without restricting the usage process.

[0130] The features described in each of the embodiments in this specification can be replaced or combined with each other. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for a system or a system embodiment, since it is basically similar to a method embodiment, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiment. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative efforts.

[0131] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0132] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0133] It should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

Claims

1. An error amplifier for a low dropout linear regulator, characterized in that, Comprising: An input stage and an output stage connected to the input stage; wherein: the input stage adopts a push-pull output architecture and is used to output a push-pull voltage according to the reference voltage, feedback voltage and output voltage of the low-dropout linear regulator received; the output stage adopts a common-drain stage architecture, and the current source in the output stage is in the nanoampere level and is used to output an error amplification voltage according to the received push-pull voltage; The input stage includes: a first current source, a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a first capacitor, a first high-voltage switching transistor and a second high-voltage switching transistor; wherein: the control terminal of the first switching transistor serves as the first input terminal of the input stage and receives the reference voltage of the low-dropout linear regulator; the first terminal of the first switching transistor is respectively connected to the first terminal of the second switching transistor and one end of the first current source; the second terminal of the first switching transistor is respectively connected to the control terminal of the fifth switching transistor, the second terminal of the fifth switching transistor and the control terminal of the sixth switching transistor; the control terminal of the second switching transistor serves as the second input terminal of the input stage and receives the feedback voltage of the low-dropout linear regulator; the second terminal of the second switching transistor is respectively connected to the control terminal of the seventh switching transistor, the second terminal of the seventh switching transistor and the control terminal of the eighth switching transistor; the first terminals of the fifth switching transistor, the sixth switching transistor, the seventh switching transistor and the eighth switching transistor are connected and grounded; the second terminal of the sixth switching transistor is connected to the first terminal of the first high-voltage switching transistor, and the control terminal of the first high-voltage switching transistor is connected to the control terminal of the second high-voltage switching transistor; the second terminal of the first high-voltage switching transistor is respectively connected to the control terminal of the third switching transistor, the second terminal of the third switching transistor and the control terminal of the fourth switching transistor; the first terminal of the third switching transistor is respectively connected to the other end of the first current source and the first terminal of the fourth switching transistor; the second terminal of the fourth switching transistor is connected to the second terminal of the second high-voltage switching transistor, and the connection point serves as the output terminal of the input stage to output the push-pull voltage; the first terminal of the second high-voltage switching transistor is respectively connected to the second terminal of the eighth switching transistor and one end of the first capacitor, and the other end of the first capacitor serves as the third input terminal of the input stage to receive the output voltage of the low-dropout linear regulator; The output stage includes: a second current source, a third current source and a third high-voltage switching transistor; wherein: the control terminal of the third high-voltage switching transistor serves as the input terminal of the output stage and receives the push-pull voltage; the first terminal of the third high-voltage switching transistor is connected to one end of the second current source, and the connection point serves as the output terminal of the output stage to output an error amplification voltage; the other end of the second current source is connected to the first terminal of the fourth switching transistor; the second terminal of the third high-voltage switching transistor is grounded through the third current source.

2. The error amplifier for a low dropout linear regulator according to claim 1, characterized in that, The first switching transistor, the second switching transistor, the third switching transistor and the fourth switching transistor are all PMOS transistors; The fifth switching transistor, the sixth switching transistor, the seventh switching transistor, and the eighth switching transistor are all NMOS transistors.

3. The error amplifier for a low dropout linear regulator according to claim 1, characterized in that, The first current source and the second current source are at the nanoampere level.

4. The error amplifier for a low dropout linear regulator according to claim 1, characterized in that, The output stage further includes: a super follower circuit; The super follower circuit is based on the common-drain stage architecture and is used to improve the slew rate of the error amplification voltage output by the output stage.

5. The error amplifier for a low dropout linear regulator according to claim 4, characterized in that, The super follower circuit includes: a fourth high-voltage switching transistor, a ninth switching transistor, a tenth switching transistor, a first resistor, and a second capacitor; wherein: The control terminal of the ninth switching transistor is respectively connected to one end of the second current source, the first end of the third high-voltage switching transistor, the second end of the ninth switching transistor, and the second end of the fourth high-voltage switching transistor; The first end of the ninth switching transistor is connected to the other end of the second current source; The first end of the fourth high-voltage switching transistor is connected to the second end of the tenth switching transistor. The control terminal of the tenth switching transistor is respectively connected to the second end of the third high-voltage switching transistor, one end of the third current source, and one end of the first resistor; the first end of the tenth switching transistor is grounded; The other end of the first resistor is grounded through the second capacitor; The control terminal of the fourth high-voltage switching transistor is connected to the VPRE voltage in the external high-voltage to low-voltage domain.

6. The error amplifier for a low dropout linear regulator according to claim 5, characterized in that, The ninth switching transistor is a PMOS transistor, and the tenth switching transistor is an NMOS transistor.

7. The error amplifier for a low dropout linear regulator according to any one of claims 1-3, characterized in that, It further includes: An input stage withstand voltage circuit for providing withstand voltage protection to the input stage.

8. The error amplifier for a low dropout linear regulator according to claim 7, characterized in that, The input stage withstand voltage circuit includes: a zener diode; Wherein, the anode of the zener diode is connected to the output terminal of the input stage, and the cathode of the zener diode is connected to the first end of the fourth switching transistor in the input stage.

9. The error amplifier for a low dropout linear regulator according to any one of claims 1-3, characterized in that, It further includes: A phase margin optimization circuit for adjusting the phase margin of the error amplifier according to the load change.

10. The error amplifier for a low dropout linear regulator according to claim 9, characterized in that, The phase margin optimization circuit includes: a third capacitor, a fourth capacitor, and a variable resistor; wherein: One end of the third capacitor is connected to one end of the variable resistor, and the connection point is connected to the first end of the fourth switching transistor in the input stage; The other end of the variable resistor is connected to one end of the fourth capacitor; The other end of the fourth capacitor is connected to the other end of the third capacitor, and the connection point is connected to the output terminal of the input stage.

11. A low dropout linear regulator, characterized in that,It includes: A feedback circuit, a power stage, and an error amplifier of the low dropout linear regulator according to any one of claims 1-10; wherein: The power stage is used to output a regulated voltage signal to supply power to the load according to the error amplification voltage output by the error amplifier and the power supply, and output the regulated voltage signal to the error amplifier; The feedback circuit is used to sample the regulated voltage signal output by the power stage and output the sampled feedback voltage to the error amplifier; The error amplifier is used to generate the error amplification voltage according to the received reference voltage, the feedback voltage, and the regulated voltage signal.

12. The low dropout linear regulator according to claim 11, wherein, It further includes: A zero-point compensation circuit for performing zero-point compensation on the low dropout linear regulator.

13. The low dropout linear regulator according to claim 12, wherein, The zero-point compensation circuit includes: a capacitor and a resistor; wherein: One end of the resistor of the zero-point compensation circuit is connected to the output end of the power stage, and the other end of the resistor of the zero-point compensation circuit is grounded through the capacitor; The first end of the power stage is connected to the power supply, the control end of the power stage is connected to the output stage of the error amplifier, the second end of the power stage is connected to the load, the input stage of the error amplifier, and one end of the feedback circuit, and the other end of the feedback circuit is connected to the input stage of the error amplifier and grounded.

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