Write cache circuit, data write method, and memory

Abstract

The application relates to the field of semiconductor circuit design, in particular to a write cache circuit, a data write method and a memory, which comprise a control module, a first cache module and a second cache module; the control module generates a first write pointer and a to-be-positioned pointer based on a mask write instruction, generates a second write pointer based on a write command, generates a first output pointer based on a mask write shift instruction, and generates a second output pointer based on a write shift instruction; the first cache module caches the to-be-positioned pointer based on the first write pointer and outputs a positioned pointer based on the first output pointer; the positioned pointer is used for indicating the second cache module to output a write address written by the second write pointer generated according to the mask write instruction; the second cache module caches the write address based on the second write pointer and outputs the cached write address based on the second output pointer or the positioned pointer; the write address storage space required by the write operation and the mask write operation is integrated, so that the layout area of the write circuit in actual application is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor circuit design, in particular to a write cache circuit, a data write method and a memory. BACKGROUND

[0002] In the process of data writing of the memory, the timing of the obtained write address and the write operation needs to be consistent, so as to realize the data write operation. Generally, the obtained write address is stored in a storage unit, and then the timing of obtaining the write address from the storage unit is set to be consistent with the timing of the write operation, so as to ensure the timing consistency of the obtained write address and the write operation.

[0003] However, the data writing of the memory includes various write modes, such as direct write operation and mask write operation. The direct write operation is to write sequentially according to the write address, and the mask write operation is to select write according to the write address, and the address not selected does not write data.

[0004] For different write modes, different storage units are used to store write addresses to ensure that different write modes run independently and do not affect each other. However, different write modes need to set different storage units, which greatly increases the area of the memory write circuit and does not meet the current development trend of the memory. SUMMARY

[0005] Embodiments of the present application provide a write cache circuit, a data write method and a memory, which are used to integrate the write address storage space required by the write operation and the mask write operation, so as to reduce the layout area of the write circuit in actual application.

[0006] The embodiment of the present application provides a write cache circuit, which comprises a control module configured to generate a first write pointer and a to-be-positioned pointer based on a mask write instruction, generate a second write pointer based on a write command, generate a first output pointer based on a mask write shift instruction, and generate a second output pointer based on a write shift instruction; wherein the write command is one of a write instruction and a mask write instruction, the to-be-positioned pointer and the second write pointer generated based on the mask write instruction correspond to the same write address; a first cache module configured to cache data in the form of a queue, cache the to-be-positioned pointer based on the first write pointer, and output a positioned pointer based on the first output pointer; wherein the positioned pointer is the to-be-positioned pointer cached by the first cache module, and is used to indicate the write address written by the second write pointer generated based on the mask write instruction; and a second cache module configured to cache data in the form of a queue, cache the write address based on the second write pointer, and output the cached write address based on the second output pointer or the positioned pointer.

[0007] For both the write operation and the mask write operation, the required cache address is stored in the second cache module, and the first cache module is used to store the address of the mask write operation in the second cache module. Compared with the manner that the write operation is independent of the mask write operation, the write cache circuit provided in the application stores the data of the write operation and the mask write operation in one storage space, thereby saving one storage space. In addition, a new position storage space is added for storing the address corresponding to the mask write operation, and the number of data stored in the position storage space is not greater than the number of data stored in the address storage space (because the data stored in the address storage space includes the write data and the mask write data, and for an extreme case, the write data is all mask write data, and at this time, the number of data stored in the position storage space is equal to the number of data stored in the address storage space). That is, the capacity of the new storage space is less than the capacity of the saved storage space, thereby reducing the layout area of the write cache circuit in actual application.

[0008] In addition, the depth of the first cache module is less than the depth of the second cache module. By setting the number of data stored in the position storage space to be less than the number of data stored in the address storage space, the layout area of the write cache circuit in actual application is reduced.

[0009] In addition, the control module includes: a first control submodule configured to generate a first write pointer based on a mask write instruction and generate a first output pointer based on a mask write shift instruction; and a second control submodule configured to generate a second write pointer based on a write instruction, generate a second output pointer based on a write shift instruction, and generate a to-be-positioned pointer based on the mask write instruction.

[0010] In addition, the first control submodule includes: a first input control unit configured to receive the mask write instruction and generate the first write pointer according to the mask write instruction; and a first output control unit configured to receive the mask write shift instruction and generate the first output pointer according to the mask write shift instruction.

[0011] In addition, the first input control unit includes: a first data receiving subunit configured to receive the mask write instruction and generate a first pointer generation instruction when the mask write instruction is received; and a first write pointer generation subunit configured to receive the first pointer generation instruction and generate the first write pointer based on the first pointer generation instruction, the first write pointer being used to indicate that the to-be-positioned pointer is stored in the first cache module.

[0012] In addition, the first output control unit comprises a second data receiving subunit configured to receive a mask write shift instruction, and configured to generate a first pointer output command when the mask write shift instruction is received; and a first output pointer generating subunit configured to receive the first pointer output command, and configured to generate a first output pointer based on the first pointer output command, wherein the first output pointer is used to indicate a first cache module to output a positioning pointer.

[0013] In addition, the second control sub-module comprises a second input control unit configured to receive a write command, and configured to generate a second write pointer based on the write command, wherein the second write pointer is used to indicate a second cache module to store a write address; and a second output control unit configured to receive a write shift instruction, and configured to generate a second output pointer based on the write shift instruction, wherein the second output pointer is used to indicate the second cache module to output the write address.

[0014] In addition, the second input control unit comprises a third data receiving subunit configured to receive the write command, and configured to generate a second pointer generating command when the write command is received; a second write pointer generating subunit configured to receive the second pointer generating command, and configured to generate the second write pointer based on the second pointer generating command, wherein the second write pointer is used to indicate the second cache module to store the write address; and a data obtaining subunit configured to receive a mask write instruction, and configured to generate the positioning pointer based on the mask write instruction.

[0015] In addition, the second output control unit comprises a fourth data receiving subunit configured to receive the write shift instruction, and configured to generate a second pointer output command when the write shift instruction is received; and a second output pointer generating subunit configured to receive the second pointer output command, and configured to generate the second output pointer based on the second pointer output command, wherein the second output pointer is used to indicate the second cache module to output the write address.

[0016] In addition, the second cache module comprises a first cache unit configured to store the write address; a first driving unit connected to the first cache unit, and configured to receive the second output pointer, and configured to be turned on based on the second output pointer, so as to sequentially output the write address stored in the first cache unit; a second driving unit connected to the first cache unit, and configured to receive the positioning pointer, and configured to be turned on based on the positioning pointer, so as to select the write address stored in the first cache unit; and a first latch unit connected to the first driving unit and the second driving unit, and configured to maintain an output voltage of the first driving unit or an output level of the second driving unit.

[0017] In addition, the first cache unit comprises a plurality of first D flip-flops, and each first D flip-flop is configured to store a write address with a preset width.

[0018] In addition, the first driving unit comprises: a first driver, an input end of which is connected to the first buffer unit, and an output end of which is connected to the first latch unit; and a receiving sub-unit, which is connected to the control module and is configured to receive the second output pointer and turn on the first driver based on the second output pointer.

[0019] In addition, the first latch unit comprises: a first inverter and a second inverter, wherein an output end of the first inverter is connected to an input end of the second inverter, and an output end of the second inverter is connected to an input end of the first inverter.

[0020] In addition, the first buffer module comprises: a second buffer unit, configured to buffer a to-be-positioned pointer; a third driving unit, connected to the second buffer unit, configured to receive the first output pointer and turn on according to the first output pointer, so as to output the to-be-positioned pointer buffered by the second buffer unit; and a second latch unit, connected to the third driving unit, configured to maintain an output level of the third driving unit.

[0021] In addition, the second buffer unit comprises: a plurality of second D flip-flops, each of which is configured to store an output pointer of a preset width.

[0022] Embodiments of the present application provide a data writing method, applied to the writing buffer circuit, comprising: based on a write command, writing a write address corresponding to the write command into the second buffer module, the write command being one of a write instruction and a mask write instruction; based on the mask write instruction, writing a to-be-positioned pointer into the first buffer module, the to-be-positioned pointer being used to indicate the write address written into the second buffer module based on the mask write instruction; based on a write shift instruction, sequentially reading out the write addresses stored in the second buffer module, or based on a mask write shift instruction, selecting and reading out the write addresses stored in the second buffer module through the to-be-positioned pointer in the first buffer module.

[0023] In addition, based on the write shift instruction, sequentially reading out the write addresses stored in the second buffer module, comprises: based on the write shift instruction, obtaining a second output pointer, and based on the second output pointer, sequentially reading out the write addresses stored in the second buffer module.

[0024] In addition, based on the mask write shift instruction, selecting and reading out the write addresses stored in the second buffer module through the to-be-positioned pointer in the first buffer module, comprises: based on the mask write shift instruction, obtaining a first output pointer, based on the first output pointer, sequentially reading out a positioning pointer, the positioning pointer being the to-be-positioned pointer stored in the first buffer module, and based on the positioning pointer, selecting and reading out the write addresses stored in the second buffer module.

[0025] Embodiments of the present application provide a memory, comprising the writing buffer circuit. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1-3A structure diagram of a write cache circuit provided by an embodiment of the present application is provided.

[0027] Figure 4 A receiving diagram of a second cache module provided by an embodiment of the present application is provided.

[0028] Figure 5 A receiving diagram of a first cache module provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0029] For different write modes, different storage units are used to store write addresses, so as to ensure independent operation of different write modes and no mutual influence. However, different write modes need to set different storage units, which greatly increases the area of the memory write circuit and does not conform to the development trend of the current memory.

[0030] An embodiment of the present application provides a write cache circuit, which is used for integrating write address storage spaces required by write operation and mask write operation, so as to reduce the layout area of the write circuit in actual application.

[0031] Those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0032] Figures 1-3 A structure diagram of a write cache circuit provided by the embodiment is provided, Figure 4 A receiving diagram of a second cache module provided by the embodiment is provided, Figure 5 A receiving diagram of a first cache module provided by the embodiment is provided, and the write cache circuit provided by the embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0033] Reference Figure 1 The write cache circuit 100 comprises a first cache module 101, a second cache module 102 and a control module 103, wherein the second cache module 102 is used for storing data addresses, and the first cache module 101 is used for storing pointers.

[0034] The control module 103 is configured to generate a first write pointer CntIn1 based on a mask write instruction MaskWrite <c:0>and the pending pointer Cnt <e:0>, a second write pointer Cntln2 is generated based on the write command <a:0>, a first output pointer FifoOut1 is generated based on a mask write shift instruction MaskWriteShift <d:0>, a second output pointer FifoOut2 is generated based on a write shift instruction WriteShift <b:0>.

[0035] wherein the write command is one of a write instruction Write and a mask write instruction MaskWrite, i.e. the write command comprises either the write instruction Write and the mask write instruction MaskWrite, i.e. whether the write instruction Write is received or the mask write instruction MaskWrite is received, the control module 103 generates a second write pointer Cntln2 <a:0>, the pending pointer Cnt <e:0>CntIn2 = CntIn1 + 1 <a:0>corresponding to the same write address Address.

[0036] For each feature mentioned above, wherein the write instruction Write and the mask write instruction MaskWrite are used to cache the corresponding write address Address, and the write shift instruction WriteShift and the mask write shift instruction MaskWriteShift are used to output the cached write address Address, so that the memory completes the write of data based on the write address Address.

[0037] the second write pointer CntIn2 <a:0>for indicating the memory space of the write address Address required for the write of the write instruction Write and the mask write instruction MaskWrite, the second output pointer FifoOut2 <b:0>for indicating the storage space of the write address Address required by the write shift instruction WriteShift to output, the first write pointer CntIn1 <c:0>for indicating the storage space required for the write pointer of the mask write instruction MaskWrite, the first output pointer FifoOutl <d:0>for indicating the storage space of the output pointer required by the mask write shift instruction MaskWriteShift, the first write pointer CntIn1 <c:0>The pointer written, i.e. the pointer to be positioned, Cnt <e:0>, first output pointer FifoOut1 <d:0>The output pointer, i.e. the positioning pointer Out0 <f:0>, the pending pointer Cnt <e:0>a storage space for indicating a write address Address required for a mask write instruction MaskWrite to write, an orientation pointer Out0 <f:0>The storage space of the write address Address indicated by the mask write shift instruction MaskWriteShift output.

[0038] The first cache module 101 is configured to cache data in the form of a queue, specifically a first-in-first-out queue, and based on a first write pointer CntIn1 <c:0>Buffer pending pointer Cnt <e:0>and based on the first output pointer FifoOut1 <d:0>Output location pointer Out0 <f:0>.

[0039] where the positioning pointer Out0 <f:0>Pending pointer Cnt for the first cache module 101 <e:0>i.e. the positioning pointer Out0 <f:0>data of the corresponding pending pointer Cnt <e:0>the data of the same; the positioning pointer Out0 <f:0>for instructing the second cache module 102 to output a second write pointer Cntln2 generated according to the mask write instruction <a:0>The write address Address of the write.

[0040] The second cache module 102 is configured to cache data in the form of a queue, specifically a first-in-first-out queue, and based on a second write pointer CntIn2 <a:0>Cache a write address Address, and based on a second output pointer FifoOut2 <b:0>or the positioning pointer Out0 <f:0>The write address Address of the output buffer.

[0041] The address output based on the write shift instruction WriteShift is the real write address WriteAddress, and the address output based on the mask write shift instruction MaskWriteShift is the real mask write address MaskWriteAddress. The real write address WriteAddress and the real mask write address MaskWriteAddress are used to indicate the write address of the memory.

[0042] It should be noted that the above "A", "B", "C", "D", "E" and "F" are used to represent the binary positions corresponding to each pointer, which can be set according to the type of memory applied in specific applications, and the present embodiment does not constitute a limitation on this data.

[0043] Suppose that the write instruction and the mask write instruction are input into the control module 103 at the same time, and the second write pointer CntIn2 is generated <a:0>, the second cache module writes in sequence 8 address data, which are data 1, data 2, data 3, data 4, data 5, data 6, data 7 and data 8 respectively; continuing to assume that data 1, data 3 and data 5 need to be written as mask, at this time, the second write pointer CntIn2 <a:0>for writing data 1 to data 8 into the second cache module 102, and generating a second write pointer Cntln2 <a:0>Pending pointer Cnt indicating same storage space <e:0>, first write pointer CntIn1 <c:0>for positioning the pointer Cnt <e:0>Write to first cache module 101.

[0044] When reading out based on a write shift instruction WriteShift, based on the second output pointer FifoOut2 <b:0>The data cached in the second cache module 102 is read out in sequence, i.e. data 1~data 8; when reading out based on the mask write shift instruction MaskWriteShift, the first output pointer FifoOut1 <d:0>Read Once Positioning Pointer Out0 <f:0>According to the positioning pointer, data 1, data 3 and data 5 are read out.

[0045] According to the above analysis, for both the write operation and the mask write operation, the required cache addresses are stored in the second cache module 102, and the first cache module 101 is used to store the addresses of the mask write operation in the second cache module 102. Compared with the mode in which the write operation is independent of the mask write operation, the write cache circuit provided by the present application stores the data of the write operation and the mask write operation in one storage space, thereby saving one storage space.

[0046] In addition, a position storage space for storing the addresses corresponding to the mask write operation is added, and the number of data stored in the position storage space is not greater than the number of data stored in the address storage space (because the data stored in the address storage space includes write data and mask write data, for an extreme case, the write data is all mask write data, and at this time, the number of data stored in the position storage space is equal to the number of data stored in the address storage space, and for normal mask write operation, the number of mask write data is less than the number of write data, that is, the required position storage space is less than the required data storage space). That is, the capacity of the added storage space is less than the capacity of the saved storage space, thereby reducing the layout area of the write cache circuit in actual application.

[0047] In one example, the depth of the first cache module 101 is less than the depth of the second cache module 102, and the number of data stored in the position storage space is less than the number of data stored in the address storage space, so as to reduce the layout area of the write cache circuit in actual application.

[0048] Reference Figure 2 and combination Figure 1 In some embodiments, the control module 103 (reference Figure 1 ) includes a first control submodule 113 and a second control submodule 123.

[0049] The first control submodule 113 is configured to generate the first write pointer CntIn1 based on the mask write instruction MaskWrite <c:0>and generate a first output pointer FifoOutl based on the mask write shift instruction WriteShift <d:0>; second control submodule 123 configured to generate a second write pointer CntIn2 based on a write command <a:0>and generating a second output pointer FifoOut2 based on a write shift instruction WriteShift <b:0>Cnt = MaskWrite <e:0>. That is, the first control submodule 113 is configured to control the first cache module 101 to store the pending positioning pointer Cnt <e:0>and control the first cache module 101 to output the positioning pointer Out0 <f:0>The second control submodule 123 is configured to control the second cache module 102 to store the write address Address, and control the second cache module 102 to output the real write address WriteAddress or the real mask write address MaskWriteAddress.

[0050] With reference to Figure 1 And in combination Figure 3 In some embodiments, the first control submodule 113 includes a first input control unit 201 and a first output control unit 301.

[0051] The first input control unit 201 is configured to receive a mask write instruction MaskWrite, and generate a first write pointer CntIn1 according to the mask write instruction MaskWrite. <c:0>; first output control unit 301, configured to receive a mask write shift instruction MaskWriteShift, and generate a first output pointer FifoOut1 according to the mask write shift instruction MaskWriteShift <d:0>.

[0052] Further, referring to Figure 2 , the first input control unit 201 comprises a first data receiving subunit 202 and a first write pointer generating subunit 203.

[0053] The first data receiving subunit 202 is configured to receive a mask write instruction MaskWrite, and when receiving the mask write instruction MaskWrite, the first data receiving subunit 202 is configured to generate a first pointer generating command; the first write pointer generating subunit 203 is configured to receive the first pointer generating command and generate a first write pointer CntIn1 based on the first pointer generating command. <c:0>, first write pointer CntIn1 <c:0>for indicating that the pointer Cnt <e:0>The first cache module 101 is stored.

[0054] Further, referring to Figure 3 The first output control unit 301 comprises a second data receiving subunit 302 and a first output pointer generating subunit 303.

[0055] The second data receiving subunit 302 is configured to receive a mask write shift instruction MaskWriteShift, and when receiving the mask write shift instruction MaskWriteShift, the second data receiving subunit 302 is configured to generate a first pointer output command; the first output pointer generating subunit 303 is configured to receive the first pointer output command and generate a first output pointer FifoOut1 based on the first pointer output command. <d:0>, first output pointer FifoOut1 <d:0>for indicating the first cache module 101 to output the positioning pointer Out0 <f:0>.

[0056] Reference Figure 3 and in conjunction with Figure 3 In some embodiments, the second control submodule 123 comprises a second input control unit 401 and a second output control unit 501.

[0057] The second output control unit 301 is configured to receive a write command and generate a second write pointer CntIn2 according to the write command. <a:0>When the write command is a mask write instruction MaskWrite, the second input control unit 301 generates a pending pointer Cnt based on the mask write instruction MaskWrite <e:0>; second output control unit 401, configured to receive a write shift instruction WriteShift and generate a second output pointer FifoOut2 according to the write shift instruction WriteShift <b:0>Since the write command includes the write instruction Write and the mask write instruction MaskWrite, the second output control unit 301 needs to generate the second write pointer CntIn2 regardless of whether the write instruction Write or the mask write instruction MaskWrite is received <a:0>In some embodiments, the write instruction Write and the mask write instruction MaskWrite can be received by a logical OR gate, and an output of the logical OR gate is an output of the write instruction.

[0058] Further, referring to Figure 2 The second input control unit 401 comprises a third data receiving subunit 402, a second write pointer generating subunit 403, and a data obtaining subunit 404.

[0059] The third data receiving subunit 402 is configured to receive a write instruction, and when the write instruction is received, the third data receiving subunit 402 is configured to generate a second pointer generating instruction; the second write pointer generating subunit 403 is configured to receive the second pointer generating instruction and generate a second write pointer CntIn2 based on the second pointer generating instruction. <a:0>, second write pointer CntIn2 <a:0>The second cache module is used for storing the address Address to be written into the second cache module; the data acquisition subunit 404 is used for receiving the mask write instruction MaskWrite and generating the to-be-positioned pointer Cnt based on the mask write instruction MaskWrite <e:0>.

[0060] Further, referring to Figure 3 , the second output control unit 501 comprises a fourth data receiving subunit 502 and a second output pointer generating subunit 503.

[0061] The fourth data receiving subunit 502 is configured to receive a write shift instruction WriteShift, and when receiving the write shift instruction WriteShift, the fourth data receiving subunit 502 is configured to generate a second pointer output command; the second output pointer generating subunit 503 is configured to receive the second pointer output command and generate a second output pointer FifoOut2 based on the second pointer output command. <b:0>, second output pointer FifoOut2 <b:0>The second cache module 102 is used for outputting the write address Address.

[0062] The first data receiving subunit 202, the second data receiving subunit 302, the third data receiving subunit 402 and the fourth data receiving subunit 502 are provided with counters with the same driving clock frequency, which are used for keeping the transmission rate of the input data and the output data of the second cache module 102 consistent and realizing the first-in first-out of the data.

[0063] Reference Figure 3 and in combination Figure 4 , the second cache module 102 (reference Figures 1-3 ) comprises a first cache unit 601, a first driving unit 602, a second driving unit 603 and a first latching unit 604.

[0064] The first cache unit 601 is used for caching the write address Address; the first driving unit 602 is connected with the first cache unit 601 and is used for receiving the second output pointer FifoOut2 <b:0>and according to the second output pointer FifoOut2 <b:0>The first driving unit 601 is connected to the first cache unit 602, and is used for outputting the write address Address cached by the first cache unit 601 once. <f:0>and according to the positioning pointer Out0 <f:0>The first cache unit 601 is turned on to select the write address cached by the first cache unit 601; the first latch unit 604, connected to the first drive unit 602 and the second drive unit 603, is used to maintain the output voltage of the first drive unit 602 or the output voltage of the second drive unit 603. Combined with the above, the second cache module 102 (reference) Figure 1 As can be seen from the description, the first driving unit 602 is used to respond to the output of the write shift instruction WriteShift, and the second driving unit 603 is used to respond to the output of the mask write shift instruction MaskWriteShift.

[0065] In one example, the first cache unit 601 includes a plurality of first D flip-flops, each of which is used to store a write address of a preset width. The width of the write address is limited according to the required address width. This embodiment does not constitute a limitation on the storage width of the first D flip-flops.

[0066] In some embodiments, each first D flip-flop includes a preset number of sub-flip-flops, wherein each sub-flip-flop is used to store 1 bit of data.

[0067] In one example, the first driving unit 602 includes: a first driver, with its input terminal connected to the output terminal of the first buffer unit 601 and its output terminal connected to the first latch unit 604; and a first receiving subunit connected to the control module 103 (see reference). Figure 1 ), used to receive the second output pointer FifoOut2 <b:0>and based on the second output pointer FifoOut2 <b:0>The first driver is turned on, and the first driver is in the second output pointer FIFOOut2 <b:0>The second driving unit 603 is connected to the first cache unit 601 and the first latch unit 604.

[0068] In one example, the second driving unit 603 includes a second driver, the input end of which is connected to the output end of the first cache unit 601, and the output end of which is connected to the input end of the first latch unit 604; and a second receiving sub-unit, which is connected to the control module 103 (refer to Figure 1 ), and is configured to receive the positioning pointer Out0 <f:0>and based on the positioning pointer Out0 <f:0>The second driver is turned on, and the second driver is turned off when the positioning pointer Out0 <f:0>The first driving unit 602 drives the output of the storage data in the first cache unit 601.

[0069] The first latch unit 604 is used for buffering the data output by the first driving unit 602 and the second driving unit 603. In an example, the first latch unit 604 includes a first inverter and a second inverter, wherein the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the input end of the first inverter, i.e., the two-stage inverters are connected in a head-to-tail manner to form a latch. In other embodiments, other latches can also be used as the first latch unit.

[0070] Reference is made to Figure 1 in combination with Figure 5 , the first cache module 101 (reference Figures 1-3 ) includes a second cache unit 701, a third driving unit 702, and a second latch unit 703.

[0071] The second cache unit 701 is used for buffering the to-be-positioned pointer Cnt <e:0>; the third driving unit 702 is connected with the output end of the second buffer unit 701, for receiving the first output pointer FifoOutl <d:0>and for outputting the first output pointer FifoOutl <d:0>is turned on to output the pending positioning pointer Cnt cached by the second cache unit 701 <e:0>; a second latch unit 703 connected to the third driving unit 702, for holding the output level of the third driving unit 702. In combination with the above description of the first cache module 101 (refer to Figure 1 ), the third driving unit 702 is used to output the positioning pointer Out0 <f:0>The second cache module 102 is controlled to output a real mask write address MaskWriteAddress.

[0072] In one example, the second cache unit 701 includes a plurality of second D flip-flops, each of which is configured to store a write address Address of a preset width, wherein the width of the write address Address is defined according to the width of the address to be stored, and the embodiments of the present application do not constitute a limitation on the storage width of the second D flip-flop; further, each of the second D flip-flops includes a plurality of sub-flip-flops of a preset width, each of which is configured to store 1 bit of data.

[0073] In one example, the third driving unit 702 includes: a third driver, an input end of which is connected to an output end of the second cache unit 701, and an output end of which is connected to the second latch unit 703; and a third receiving sub-unit, which is connected to the control module 103 (refer to Figure 1 Figure 1 ), and is configured to receive a first output pointer FifoOut1 <d:0>and based on the first output pointer FifoOut1 <d:0>The third driver is turned on.

[0074] The second latch unit 703 is used for buffering the data output by the third driving unit 702. In an example, the second latch unit 703 includes a third inverter and a fourth inverter, wherein an output terminal of the third inverter is connected to an input terminal of the fourth inverter, and an output terminal of the fourth inverter is connected to an input terminal of the third inverter, i.e., the two inverters are connected in a head-to-tail manner to form a latch. In other embodiments, other latches can also be used as the second latch unit.

[0075] The write cache circuit provided in the application saves one storage space by storing the data of the write operation and the mask write operation in one storage space. In addition, a position storage space for storing the address corresponding to the mask write operation is newly added, and the number of data stored in the position storage space is not greater than the number of data stored in the address storage space (because the data stored in the address storage space includes the write data and the mask write data, and for an extreme case, the write data is all mask write data, and at this time, the number of data stored in the position storage space is equal to the number of data stored in the address storage space). That is, the capacity of the newly added storage space is less than the capacity of the saved storage space, thereby reducing the layout area of the write cache circuit in actual application.

[0076] Based on the write cache circuit provided in the above embodiment, another embodiment of the application provides a data write method, mainly including the following steps:

[0077] Based on the write command, the write address corresponding to the write command is written into the second cache module, and the write command is one of a write instruction and a mask write instruction.

[0078] Based on the mask write instruction, the to-be-positioned pointer is written into the first cache module, and the to-be-positioned pointer is used to indicate the write address written into the second cache module based on the mask write instruction.

[0079] Based on the write shift instruction, the write addresses stored in the second cache module are read out in sequence, or based on the mask write shift instruction, the write addresses stored in the second cache module are read out through the to-be-positioned pointer in the first cache module.

[0080] In some embodiments, based on the write shift instruction, the write addresses stored in the second cache module are read out in sequence, including: based on the write shift instruction, the second output pointer is obtained, and based on the second output pointer, the write addresses stored in the second cache module are read out in sequence.

[0081] In some embodiments, based on the mask write shift instruction, the readout of the write address stored in the second cache module is selected by the to-be-positioned pointer in the first cache module, comprising: obtaining the first output pointer based on the mask write shift instruction, and sequentially reading out the positioning pointer based on the first output pointer, the positioning pointer being the to-be-positioned pointer stored in the first cache module, and selecting the readout of the write address stored in the second cache module based on the positioning pointer.

[0082] It should be noted that the above description of the data write method is similar to the description of the write cache circuit embodiment, and has similar beneficial effects as the write cache circuit embodiment, and therefore will not be described again. For technical details not disclosed in the data write method of the embodiments of the present application, please refer to the description of the write cache circuit in the embodiments of the present application.

[0083] Another embodiment of the present application also provides a memory comprising the write cache circuit provided by the above-mentioned embodiments. The memory referred to in the present application includes but is not limited to dynamic random access memory and the like. The memory adopts the write cache circuit provided by the above-mentioned embodiments to reduce the layout area of the write circuit in actual application.

[0084] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip conforms to the DDR2 memory specification.

[0085] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip conforms to the DDR3 memory specification.

[0086] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip conforms to the DDR4 memory specification.

[0087] In some embodiments, the memory is a dynamic random access memory (DRAM) chip, wherein the memory of the dynamic random access memory (DRAM) chip conforms to the DDR5 memory specification.

[0088] It should be noted that the features disclosed in the write cache circuit provided by the above-mentioned embodiments can be combined arbitrarily without conflict, and a new circuit embodiment can be obtained. The methods disclosed in the data write method provided by the above-mentioned embodiments can be combined arbitrarily without conflict, and a new method embodiment can be obtained.

[0089] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A write cache circuit, comprising: The application relates to a data processing method and device. The control module is configured to generate a first write pointer and a to-be-positioned pointer based on a mask write instruction, generate a second write pointer based on a write instruction, generate a first output pointer based on a mask write shift instruction, and generate a second output pointer based on a write shift instruction; wherein the write instruction is one of the write instruction and the mask write instruction, and the to-be-positioned pointer corresponds to the same write address as the second write pointer generated based on the mask write instruction; The first cache module is configured to cache data in the form of a queue, cache the to-be-positioned pointer based on the first write pointer, and output a positioned pointer based on the first output pointer; wherein the positioned pointer is the to-be-positioned pointer cached by the first cache module, and is used to indicate that the second cache module outputs the write address written by the second write pointer generated based on the mask write instruction; The second cache module is configured to cache data in the form of a queue, cache the write address based on the second write pointer, and output the cached write address based on the second output pointer or the positioned pointer.

2. The write cache circuit of claim 1, wherein, The depth of the first cache module is less than the depth of the second cache module.

3. The write cache circuit of claim 1, wherein, The control module comprises: The first control submodule is configured to generate the first write pointer based on the mask write instruction and generate the first output pointer based on the mask write shift instruction; The second control submodule is configured to generate the second write pointer based on the write instruction, generate the second output pointer based on the write shift instruction, and generate the to-be-positioned pointer based on the mask write instruction.

4. The write cache circuit of claim 3, wherein, The first control submodule comprises: The first input control unit is used for receiving the mask write instruction and generating the first write pointer according to the mask write instruction; The first output control unit is used for receiving the mask write shift instruction and generating the first output pointer according to the mask write shift instruction.

5. The write cache circuit of claim 4, wherein, The first input control unit comprises: The first data receiving subunit is used for receiving the mask write instruction, and when the mask write instruction is received, the first data receiving subunit is used for generating a first pointer generation instruction; The first write pointer generation subunit is used for receiving the first pointer generation instruction and generating the first write pointer based on the first pointer generation instruction, wherein the first write pointer is used to indicate that the to-be-positioned pointer is stored into the first cache module.

6. The write cache circuit of claim 4, wherein, The first output control unit comprises: The second data receiving subunit is used for receiving the mask write shift instruction, and when the mask write shift instruction is received, the second data receiving subunit is used for generating a first pointer output instruction; The first output pointer generation subunit is used for receiving the first pointer output instruction and generating the first output pointer based on the first pointer output instruction, wherein the first output pointer is used to indicate that the first cache module outputs the positioned pointer.

7. The write cache circuit of claim 3, wherein, The second control submodule comprises: The second input control unit is configured to receive the write command and generate the second write pointer according to the write command, and when the write command is the mask write instruction, the second input control unit generates the to-be-positioned pointer according to the mask write instruction. The second output control unit is configured to receive the write shift instruction and generate the second output pointer according to the write shift instruction.

8. The write cache circuit of claim 7, wherein, The second input control unit comprises: The third data receiving subunit is configured to receive the write command and generate a second pointer generation command when the write command is received. The second write pointer generation subunit is configured to receive the second pointer generation command and generate the second write pointer based on the second pointer generation command, where the second write pointer is used to indicate that the write address is stored in the second cache module. The data acquisition subunit is configured to receive the mask write instruction and generate the to-be-positioned pointer based on the mask write instruction.

9. The write cache circuit of claim 7, wherein, The second output control unit comprises: The fourth data receiving subunit is configured to receive the write shift instruction and generate a second pointer output command when the write shift instruction is received. The second output pointer generation subunit is configured to receive the second pointer output command and generate the second output pointer based on the second pointer output command, where the second output pointer is used to indicate that the second cache module outputs the write address.

10. The write cache circuit of claim 1, wherein, The second cache module comprises: The first cache unit is configured to cache the write address. The first driving unit is connected to the first cache unit and is configured to receive the second output pointer and turn on according to the second output pointer, so as to sequentially output the write address cached by the first cache unit. The second driving unit is connected to the first cache unit and is configured to receive the positioning pointer and turn on according to the positioning pointer, so as to select and output the write address cached by the first cache unit. The first latch unit is connected to the first driving unit and the second driving unit and is configured to maintain the output voltage of the first driving unit or the output level of the second driving unit.

11. The write cache circuit of claim 10, wherein, The first cache unit comprises a plurality of first D flip-flops, and each first D flip-flop is configured to store the write address with a preset width.

12. The write cache circuit of claim 10, wherein, The first driving unit comprises: The first driver has an input end connected to the first cache unit and an output end connected to the first latch unit. The receiving subunit is connected to the control module and is configured to receive the second output pointer and turn on the first driver based on the second output pointer.

13. The write cache circuit of claim 10, wherein, The first latch unit comprises a first inverter and a second inverter, where an output end of the first inverter is connected to an input end of the second inverter, and an output end of the second inverter is connected to an input end of the first inverter.

14. The write cache circuit of claim 1, wherein, The first cache module comprises: The second cache unit is configured to cache the to-be-positioned pointer. A third driving unit is connected to the second cache unit and configured to receive the first output pointer and to be turned on according to the first output pointer to output the pending pointer cached in the second cache unit. A second latch unit is connected to the third driving unit and configured to maintain the output level of the third driving unit.

15. The write cache circuit of claim 14, wherein, The second cache unit includes a plurality of second D flip-flops, each of which is configured to store the output pointer with a preset width.

16. A data writing method, characterized by, The write cache circuit is applied to any one of claims 1-15. Based on a write command, a write address corresponding to the write command is written into the second cache module, the write command being one of a write instruction and a mask write instruction. Based on the mask write instruction, a pending pointer is written into the first cache module, the pending pointer being used to indicate the write address written into the second cache module based on the mask write instruction. Based on a write shift instruction, the write addresses stored in the second cache module are sequentially read out, or based on a mask write shift instruction, the write addresses stored in the second cache module are selected and read out through the pending pointer in the first cache module.

17. The data write method of claim 16, wherein, The second output pointer is obtained based on the write shift instruction, and the write addresses stored in the second cache module are sequentially read out based on the second output pointer.

18. The data write method of claim 16, wherein, The first output pointer is obtained based on the mask write shift instruction, the positioning pointer is sequentially read out based on the first output pointer, the positioning pointer being the pending pointer stored in the first cache module, and the write addresses stored in the second cache module are selected and read out based on the positioning pointer.

19. A memory, comprising: The write cache circuit is applied to any one of claims 1-15.

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