Controller for flyback power converter and method of operation thereof

Abstract

A controller applied to a flyback power converter and an operating method thereof are disclosed. The controller includes a sample-and-hold circuit and a shutdown circuit. The sample-and-hold circuit samples a feedback voltage to generate a sample voltage, wherein the controller generates a compensation voltage according to the sample voltage, and an output voltage of a secondary side of the flyback power converter is related to the compensation voltage. The shutdown circuit shuts down a sample signal according to a peak value of an input voltage, the sample voltage and a detection voltage to make the sample-and-hold circuit stop sampling the feedback voltage. Therefore, compared with prior art, the controller can detect a load variation of the secondary side of the flyback power converter through the peak value of the detection voltage, can avoid an error of the sample signal, and can effectively reduce a shutdown interval of the sample signal to optimize the shutdown interval of the sample signal.

Description

Technical Field

[0001] This invention relates to a controller and its operating method for a flyback power converter, and more particularly to a controller and its operating method that can simultaneously shut down the sampling signal based on the peak values ​​of the input voltage, the sampled voltage, and the detected voltage. Background Technology

[0002] In the prior art, a controller applied to the primary side of a single-stage flyback power factor correction (PFC) power converter receives an input voltage (wherein the input voltage is related to a DC voltage, and the DC voltage is generated by rectifying an AC voltage through a bridge rectifier included in the single-stage flyback PFC power converter), and compares the input voltage with a threshold voltage. When the input voltage is lower than the threshold voltage, the sampling signal input to the sample-and-hold circuit within the controller is turned off. Thus, the sample-and-hold circuit stops sampling a feedback voltage to generate a sampling voltage until the sampling signal is re-enabled. Additionally, the controller can generate a compensation voltage based on the sampling voltage, and adjust the frequency variation curve of a gate control signal (controlling a power switch included in the single-stage flyback PFC power converter) based on the compensation voltage to control the output voltage on the secondary side of the single-stage flyback PFC power converter.

[0003] However, because the sample-and-hold circuit stops sampling the feedback voltage to generate the sampled voltage during the off-range of the sampling signal, the sampled voltage generated by the sample-and-hold circuit no longer changes. If the load coupled to the single-stage flyback power factor correction converter changes or the input voltage changes at this time, the compensation voltage related to the sampled voltage cannot reflect the change in load or input voltage in a timely manner because the sampled voltage no longer changes, resulting in overshoot / undershoot of the output voltage. Because in existing technology, the critical voltage is a fixed value, if the critical voltage is too high, the off-range of the sampling signal becomes too long. This leads to more severe overshoot / undershoot of the output voltage when the load or input voltage changes, potentially exceeding the range of the single-stage flyback power factor correction converter's output voltage adjustment. Conversely, if the critical voltage is too low, the magnetizing current on the primary side of the single-stage flyback power factor correction converter is too small, resulting in a low reflected voltage on the secondary side, causing an incorrect (low) sampling voltage. Consequently, the output voltage becomes high, and the single-stage flyback power factor correction converter may even oscillate.

[0004] Therefore, how to solve the problem caused by the aforementioned fixed critical voltage has become an important issue for the designers of the controller. Summary of the Invention

[0005] One embodiment of the present invention discloses a controller for a flyback power converter, wherein the controller has a new feedback detection function. The controller includes a sample-and-hold circuit and a shutdown circuit. The sample-and-hold circuit samples a feedback voltage to generate a sampled voltage, wherein the controller generates a compensation voltage based on the sampled voltage, and the output voltage on the secondary side of the flyback power converter is related to the compensation voltage. The shutdown circuit is used to shut down a sampling signal based on an input voltage, the sampled voltage, and the peak value of a detection voltage, so that the sample-and-hold circuit stops sampling the feedback voltage.

[0006] Another embodiment of the present invention discloses an operation method for a controller applied to a flyback power converter, wherein the controller has a new feedback detection function, and the controller includes a sample-and-hold circuit and a shutdown circuit. The operation method includes the shutdown circuit determining whether to shut down a sampling signal based on the peak values ​​of an input voltage, a sample voltage, and a detection voltage; and when the shutdown circuit shuts down the sampling signal, the sample-and-hold circuit stops sampling a feedback voltage to generate the sample voltage until the sampling signal is re-enabled.

[0007] This invention discloses a controller for a flyback power converter, wherein the controller has a new feedback detection function. Because the new feedback detection function allows the controller to simultaneously shut down a sampling signal based on the peak values ​​of an input voltage, a sampled voltage, and a detected voltage, this invention has the following advantages compared to the prior art: First, because the peak value of the detected voltage changes with the load on the secondary side of the flyback power converter, the controller can detect the load change on the secondary side of the flyback power converter through the peak value of the detected voltage; Second, because the sampled voltage changes with the output voltage on the secondary side of the flyback power converter, the controller can avoid errors in the sampled signal; Third, under the premise that the controller can avoid errors in the sampled signal, the controller detects the load on the secondary side of the flyback power converter and the input voltage, which can effectively reduce the shutdown range of the sampled signal to optimize the shutdown range of the sampled signal. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a controller for a flyback power converter disclosed in the first embodiment of the present invention.

[0009] Figure 2 This is a timing diagram illustrating how the shut-off circuit shuts off the sampling signal based on the peak values ​​of the input voltage, sampling voltage, and detection voltage.

[0010] Figure 3 This is a flowchart of an operation method of a controller applied to a flyback power converter, as disclosed in the second embodiment of the present invention.

[0011] The reference numerals in the attached figures are explained as follows: Detailed Implementation

[0012] Please refer to Figure 1 , Figure 1This is a schematic diagram of a controller 200 applied to a flyback power converter 100, as disclosed in the first embodiment of the present invention. The controller 200 has a new feedback detection function and is applied to the primary side PRI of the flyback power converter 100. The flyback power converter 100 is a single-stage flyback power factor correction (PFC) power converter. Furthermore, Figure 1 The flyback power converter 100 and controller 200 are shown only for elements relevant to this invention, and the ground level GND1 of the primary side PRI of the flyback power converter 100 and the ground level GND2 of the secondary side SEC of the flyback power converter 100 may be the same or different. Figure 1 As shown, the controller 200 includes a sample-and-hold circuit 202 and a shutdown circuit 204. The sample-and-hold circuit 202 receives a feedback voltage VFB through pin FB of the controller 200 and samples the feedback voltage VFB to generate a sample voltage VFBSH. Additionally, as... Figure 1 As shown, the feedback voltage VFB is generated by a first voltage divider circuit 102 through the auxiliary voltage VAUX on the auxiliary winding NAUX of the flyback power converter 100. After the sample voltage VFBSH is generated by the sample-and-hold circuit 202, the relevant circuits in the controller 200 can generate a compensation voltage VCOMP (that is, the voltage on the COMP pin of the controller 200) according to the sample voltage VFBSH, and adjust the frequency variation curve of the gate control signal GCS according to the compensation voltage VCOMP to control the output voltage VOUT of the secondary side SEC of the flyback power converter 100. That is, the output voltage VOUT of the secondary side SEC of the flyback power converter 100 is related to the compensation voltage VCOMP. In addition, the gate control signal GCS is input to a power switch 103 included in the flyback power converter 100 through the GATE pin of the controller 200, where the gate control signal GCS is used to control the opening and closing of the power switch 103, and the flyback power converter 100 operates in a quasi-resonate mode. In addition, as Figure 1 As shown, the auxiliary voltage VAUX can be input to the controller 200 through the VCC pin of the controller 200 and serve as the power supply voltage for the controller 200, and the ground level GND1 can be received through the GND pin of the controller 200.

[0013] like Figure 1As shown, the shutdown circuit 204 includes a first comparator 2042, a peak generator 2044, a second comparator 2046, a third comparator 2048, a NAND gate 2050, and an AND gate 2052. The first comparator 2042 receives an input voltage VIN through the controller 200's pin IN and generates a first comparison signal FCS (i.e., a first high-level signal) when the input voltage VIN is less than a first threshold voltage VTH1. The first comparator 2042 also has a hysteresis function. Additionally, as... Figure 1 As shown, the DC voltage VBRI is generated by rectifying an AC voltage VAC through a bridge rectifier 104 included in the flyback power converter 100, and the input voltage VIN is generated by the DC voltage VBRI through a second voltage divider circuit 106. The peak generator 2044 receives a detection voltage VCS through pin CS of the controller 200 and generates the peak value VP of the detection voltage VCS accordingly. The second comparator 2046 receives the peak value VP and generates a second comparison signal SCS (i.e., a second high-level signal) when the peak value VP is less than a second threshold voltage VTH2. The third comparator 2048 receives a sampled voltage VFBSH and generates a third comparison signal TCS (i.e., a third high-level signal) when the sampled voltage VFBSH is less than a third threshold voltage VTH3. The NAND gate 2050 receives the first comparison signal FCS, the second comparison signal SCS, and the third comparison signal TCS, and generates an output signal OS (i.e., a first low-level signal) accordingly. Because the output signal OS is the first low-level signal, AND gate 2052 can disable the sampling signal VTRI based on the output signal OS. That is, when AND gate 2052 receives the output signal OS, the sampling signal VTRI will not pass through AND gate 2052 to the sample-and-hold circuit 202 (at this time, the output of AND gate 2052 is at a low level). When the sample-and-hold circuit 202 does not receive the sampling signal VTRI, it will stop sampling the feedback voltage VFB. At this time, the sample-and-hold circuit 202 will maintain the previously generated sampling voltage VFBSH until the off-range of the sampling signal VTRI ends. Furthermore, this invention is not limited to the first comparison signal FCS being the first high-level signal, the second comparison signal SCS being the second high-level signal, the third comparison signal TCS being the third high-level signal, the output signal OS being the first low-level signal, the NAND gate 2050, and the AND gate 2052. In other words, as long as the shutdown circuit 204 can utilize the input voltage VIN, the sampling voltage VFBSH, the peak value VP of the detection voltage VCS, and the logic gate shutdown sampling signal VTRI, it falls within the scope of this invention.

[0014] Additionally, please refer to Figure 2 , Figure 2This is a timing diagram illustrating how the shut-off circuit 204 shuts off the sampling signal VTRI based on the peak value VP of the input voltage VIN, the sampling voltage VFBSH, and the detection voltage VCS. (See diagram for example.) Figure 2 As shown, between time T0 and time T1, between time T2 and time T3, and between time T4 and time T5, the input voltage VIN is less than the first critical voltage VTH1 (where VTH1H is the upper bound of the hysteresis interval corresponding to the first critical voltage VTH1 and VTH1L is the lower bound of the hysteresis interval corresponding to the first critical voltage VTH1). Similarly, between time T0 and time T1, between time T2 and time T3, and between time T4 and time T5, the peak value VP is also less than the second critical voltage VTH2. Furthermore, between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, the sampled voltage VFBSH is less than the third critical voltage VTH3. Figure 2 As shown, the input voltage VIN will only be less than the first critical voltage VTH1, the peak value VP will only be less than the second critical voltage VTH2, and the sampled voltage VFBSH will only be less than the third critical voltage VTH3 between times T0 and T6, T7 and T8, and T9 and T5. In other words, the first comparator 2042, the second comparator 2046, and the third comparator 2048 will only simultaneously generate the first high-level signal, the second high-level signal, and the third high-level signal, respectively, between times T0 and T6, T7 and T8, and T9 and T5. Due to the characteristics of the NAND gate 2050, the NAND gate 2050 will only generate the output signal OS (i.e., the first low-level signal) between times T0 and T6, T7 and T8, and T9 and T5. Therefore, since NAND gate 2050 only generates the output signal OS (i.e., the first low-level signal) between times T0 and T6, T7 and T8, and T9 and T5, the shutdown circuit 204 will only shut down the sampling signal VTRI through AND gate 2052 and the output signal OS between times T0 and T6, T7 and T8, and T9 and T5. In other words, the sample-and-hold circuit 202 will stop sampling the feedback voltage VFB between times T0 and T6, T7 and T8, and T9 and T5, and maintain the current sampling voltage VFBSH. The time intervals between times T0 and T6, T7 and T8, and T9 and T5 constitute the shutdown interval of the sampling signal VTRI. Furthermore, as... Figure 2As shown, the sample-and-hold circuit 202 can still sample and feed back the voltage VFB between time T6 and time T1, between time T2 and time T7, between time T8 and time T3, and between time T4 and time T9.

[0015] Because the shutdown circuit 204 can simultaneously shut down the sampling signal VTRI based on the input voltage VIN, the sampling voltage VFBSH, and the peak value VP of the detection voltage VCS, the present invention has the following advantages compared to the prior art: First, because when the load of the secondary side SEC of the flyback power converter 100 (not shown) Figure 1 When the voltage VCS changes, the peak value VP of the detection voltage VCS also changes accordingly. Therefore, the shutdown circuit 204 can detect the load change of the secondary side SEC of the flyback power converter 100 by detecting the peak value VP of the detection voltage VCS. Secondly, because the sampling voltage VFBSH can change with the output voltage VOUT, the shutdown circuit 204 can avoid errors in the sampling signal VTRI. Thirdly, under the premise that the shutdown circuit 204 can avoid errors in the sampling signal VTRI, detecting the load of the secondary side SEC of the flyback power converter 100 and the input voltage VIN can effectively reduce the shutdown range of the sampling signal VTRI to optimize the shutdown range of the sampling signal VTRI. Therefore, compared with the prior art, the present invention can simultaneously achieve the specifications of voltage regulation rate <±5% and dynamic rate of load of the secondary side SEC <±13%.

[0016] Please refer to Figure 1-3 , Figure 3 This is a flowchart of an operation method of a controller applied to a flyback power converter, as disclosed in the second embodiment of the present invention. Figure 3 The operation method is to use Figure 1 The power converter 100 and controller 200 are described in detail below: Step 300: Begin; Step 302: Does the shutdown circuit 204 shut down the sampling signal VTRI? If yes, proceed to step 304; if no, proceed to step 302. Step 304: The sample-and-hold circuit 202 stops sampling the feedback voltage VFB to generate the sampling voltage VFBSH until the sampling signal VTRI is re-enabled, then jumps back to step 302.

[0017] In step 302, when the shutdown circuit 204 does not shut down the sampling signal VTRI, the sample-and-hold circuit 202 can sample the feedback voltage VFB to generate the sampling voltage VFBSH. Additionally, as... Figure 2As shown, the input voltage VIN will be less than the first critical voltage VTH1, the peak value VP will be less than the second critical voltage VTH2, and the sampled voltage VFBSH will be less than the third critical voltage VTH3 only simultaneously between times T0 and T6, between times T7 and T8, and between times T9 and T5. In other words, the first comparator 2042, the second comparator 2046, and the third comparator 2048 will simultaneously generate the first high-level signal, the second high-level signal, and the third high-level signal, respectively, only between times T0 and T6, between times T7 and T8, and between times T9 and T5. That is, the NAND gate 2050 will only generate the output signal OS (i.e., the first low-level signal) between times T0 and T6, between times T7 and T8, and between times T9 and T5. Therefore, since NAND gate 2050 only generates the output signal OS (that is, the first low-level signal) between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5, the shutdown circuit 204 will only shut down the sampling signal VTRI through AND gate 2052 and the output signal OS between time T0 and time T6, between time T7 and time T8, and between time T9 and time T5.

[0018] In step 304, the sample-and-hold circuit 202 will stop sampling the feedback voltage VFB between times T0 and T6, between times T7 and T8, and between times T9 and T5, and maintain the current sampling voltage VFBSH until the sampling signal VTRI is reactivated. Additionally, as... Figure 2 As shown, the sample-and-hold circuit 202 can still sample and feed back the voltage VFB between time T6 and time T1, between time T2 and time T7, between time T8 and time T3, and between time T4 and time T9.

[0019] In summary, the controller disclosed in this invention has a new feedback detection function. Because this new feedback detection function enables the shutdown circuit within the controller to simultaneously shut down the sampling signal based on the peak values ​​of the input voltage, the sampling voltage, and the detection voltage, this invention has the following advantages compared to the prior art: First, because the peak value of the detection voltage changes with the load on the secondary side of the flyback power converter, the controller can detect the load change on the secondary side of the flyback power converter through the peak value of the detection voltage; Second, because the sampling voltage changes with the output voltage on the secondary side of the flyback power converter, the controller can avoid errors in the sampling signal; Third, under the premise that the controller can avoid errors in the sampling signal, the controller detects the load on the secondary side of the flyback power converter and the input voltage, which can effectively reduce the shutdown range of the sampling signal to optimize the shutdown range of the sampling signal.

[0020] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A controller for use in a flyback power converter, wherein the controller has a new feedback detection function, characterized in that Include: A sample-and-hold circuit is used to sample a feedback voltage to generate a sampled voltage, wherein the controller generates a compensation voltage based on the sampled voltage, and the output voltage on the secondary side of the flyback power converter is related to the compensation voltage; and A shutdown circuit is provided to shut down a sampling signal based on an input voltage, the sampling voltage, and the peak value of a detection voltage, so that the sample-and-hold circuit stops sampling the feedback voltage.

2. The controller of claim 1, wherein The controller is applied to the primary side of the flyback power converter, and the flyback power converter is a single-stage flyback power factor correction power converter.

3. The controller of claim 1, wherein The feedback voltage is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter.

4. The controller of claim 1, wherein The power supply voltage of the controller is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter.

5. The controller of claim 1, wherein The input voltage is related to the DC voltage, and the DC voltage is generated by rectifying an AC voltage through a bridge rectifier included in the flyback power converter.

6. The controller of claim 1, wherein The shutdown circuit includes: A first comparator is configured to receive the input voltage and generate a first comparison signal when the input voltage is less than a first threshold voltage, wherein the first comparator has a hysteresis function. A peak generator is used to receive a detection voltage and generate a peak value of the detection voltage accordingly; a second comparator is used to receive the peak value of the detection voltage and generate a second comparison signal when the peak value of the detection voltage is less than a second threshold voltage. A third comparator is used to receive the sampled voltage and generate a third comparison signal when the sampled voltage is less than a third threshold voltage; A NAND gate is used to receive the first comparison signal, the second comparison signal, and the third comparison signal, and to generate an output signal accordingly; and An AND gate is used to turn off the sampling signal based on the output signal.

7. A method of operating a controller for a flyback power converter, wherein the controller has a new feedback detection function, and the controller includes a sample-and-hold circuit and a shutdown circuit, characterized in that... Include: The shutdown circuit determines whether to shut down a sampling signal based on the peak values ​​of an input voltage, a sampled voltage, and a detected voltage; and When the shutdown circuit shuts down the sampling signal, the sample-and-hold circuit stops sampling a feedback voltage to generate the sampling voltage until the sampling signal is reactivated.

8. The operating method as described in claim 7, characterized in that... The controller generates a compensation voltage based on the sampled voltage, and the output voltage on the secondary side of the flyback power converter is related to the compensation voltage.

9. The operating method as described in claim 7, characterized in that... The controller is applied to the primary side of the flyback power converter.

10. The operating method as described in claim 7, characterized in that... The feedback voltage is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter.

11. The operating method as described in claim 7, characterized in that... The power supply voltage of the controller is related to the auxiliary voltage on the auxiliary winding included in the flyback power converter.

12. The operating method as described in claim 7, characterized in that... The input voltage is related to the DC voltage, and the DC voltage is generated by rectifying an AC voltage through a bridge rectifier included in the flyback power converter.

13. The operating method as described in claim 7, characterized in that... The shutdown circuit determines whether to shut down the sampling signal based on the peak values ​​of the input voltage, the sampling voltage, and the detection voltage, including: When the input voltage is less than a first threshold voltage, a first comparison signal is generated; When the peak value of a detection voltage is less than a second threshold voltage, a second comparison signal is generated. When the sampling voltage is less than a third threshold voltage, a third comparison signal is generated; An output signal is generated based on the first comparison signal, the second comparison signal, and the third comparison signal; and The sampling signal is turned off based on the output signal.

Images