An enable circuit

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to an enabling circuit. The application provides an enabling circuit which can consider two forms of enabling. The rising edge of an enabling signal is detected first, and a chip is directly controlled to start. At the same time, an external enabling signal is detected. If the detection is a level signal, the chip is closed after the enabling signal is invalid. If the detection is a pulse signal, the chip is still kept open after the enabling is invalid, and the chip is closed until the next pulse of the enabling signal is detected.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to an enable circuit. Background Technology

[0002] Enable control signals are crucial in almost all chip applications. Typically, an external enable signal is provided to the chip, and the internal enable circuit processes this signal to control the overall chip operation. Traditional enable circuits usually only process level signals: a high external enable signal powers the chip on, and a low external enable signal powers it off. However, in some applications, a continuous level enable signal cannot be generated externally; only a pulse signal can be used. Therefore, traditional enable circuits are unsuitable for these applications. Furthermore, if only a flip-flop is used to detect the rising (or falling) edge of the external enable signal, it's difficult to guarantee that the system will shut down correctly after the enable signal transitions from an active to an inactive level in level-enabled applications. In conclusion, traditional enable circuits cannot accommodate both level-enabled and pulse-enabled applications, limiting their application scope. Summary of the Invention

[0003] To address the limitation of traditional enable circuits in handling both level-based and pulse-based enable applications, this invention proposes an enable circuit that can accommodate both types of enable. By first detecting the rising edge of the enable signal to directly control chip startup, and simultaneously detecting an external enable signal, if a level signal is detected, the chip is turned off after the enable signal becomes invalid; if a pulse signal is detected, the chip remains on even after the enable is invalidated, until the next enable signal pulse is detected, at which point the chip is turned off.

[0004] The technical solution of this invention is as follows:

[0005] An enabling circuit includes a first NMOS transistor MN1, a first current source IB1, a second current source IB2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first Schmitt trigger SMIT1, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first OR gate OR1, a second OR gate OR2, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a comparator CMP, and a first NAND gate NAN. D1, RAMP module, first T flip-flop, and second T flip-flop; wherein, the gate of the first NMOS transistor MN1 is connected to the enable signal, its drain is connected to one end of the first current source IB1, one end of the first capacitor C1, and the input of the first Schmitt trigger SMIT1, the source of the first NMOS transistor MN1 is connected to one end of the second current source IB2, the other end of the first current source IB1 is connected to the power supply, and the other end of the second current source IB2 and the other end of the first capacitor C1 are grounded; the output of the first Schmitt trigger SMIT1 is connected to the input of the first inverter INV1, the output of the first inverter INV1 is connected to one input of the first OR gate OR1, the input of the eighth inverter INV8, and one input of the RAMP module; the first OR gate... The other input of OR1 is connected to the reset signal. The output of the first OR gate OR1 is connected to one input of the first NOR gate NOR1, the input of the second inverter INV2, and the first input of the first NAND gate NAND1. The output of the second inverter INV2 is connected to one end of the second capacitor C2 and the input of the third inverter INV3. The output of the third inverter INV3 is connected to one end of the third capacitor C3 and the input of the fourth inverter INV4. The output of the fourth inverter INV4 is connected to the other input of the first NOR gate NOR1 and the second input of the first NAND gate NAND1. The other ends of the second capacitor C2 and the third capacitor C3 are grounded. The output of the first NOR gate NOR1 is connected to the clock signal of the first T flip-flop. The input terminals are as follows: the set signal terminal of the first T flip-flop is connected to the output terminal of the fifth NOR gate NOR5; the inverted output terminal of the first T flip-flop is connected to one input terminal of the second NOR gate NOR2; the other input terminal of the second NOR gate NOR2 is connected to the output terminal of the third NOR gate NOR3; the output terminal of the first NAND gate NAND1 is connected to the clock signal terminal of the second T flip-flop; the set signal terminal of the second T flip-flop is connected to the output terminal of the fifth NOR gate NOR5; the inverted output terminal of the second T flip-flop is connected to the first input terminal of the third NOR gate NOR3; the second input terminal of the third NOR gate NOR3 is connected to the reset signal; the third input terminal of the third NOR gate NOR3 is connected to the output terminal of the second NOR gate NOR2; and the output terminal of the third NOR gate NOR3 is the output terminal of the enable circuit.The first T flip-flop is active on the rising edge, and the second T flip-flop is active on the falling edge. The output of the eighth inverter INV8 is connected to one input of the second OR gate OR2, the other input of the second OR gate OR2 is connected to the output of the comparator, and the output of the second OR gate OR2 is connected to the third input of the first NAND gate NAND1. The other input of the RAMP module is connected to the output of the third NOR gate NOR3. The output of the RAMP module outputs the VRAMP voltage to the positive input of the comparator, and the negative input of the comparator is connected to the reference voltage. The input of the fifth inverter INV5 is connected to the output of the third NOR gate NOR3. The output of inverter INV5 is connected to one end of the fourth capacitor C4 and the input of the sixth inverter INV6. The output of the sixth inverter INV6 is connected to one end of the fifth capacitor C5 and the input of the seventh inverter INV7. The output of the seventh inverter INV7 is connected to one input of the fourth NOR gate NOR4. The other ends of the fourth capacitor C4 and the fifth capacitor C5 are grounded. The other input of the fourth NOR gate NOR4 is connected to the output of the triple NOR gate NOR3. The output of the fourth NOR gate NOR4 is connected to one input of the fifth NOR gate NOR5. The other input of the fifth NOR gate NOR5 is connected to the reset signal.

[0006] The beneficial effect of this invention is that it can detect whether the external enable signal is in level form or pulse form, thus taking into account both enable modes. Attached Figure Description

[0007] Figure 1 This is the enable circuit proposed in this invention. Detailed Implementation

[0008] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0009] like Figure 1The circuit shown is the proposed enable circuit. Before system enable, the power-on reset signal POR is high, providing the initial potential for the entire system. The output of the third NOR gate, i.e., the output signal START of the entire module, is low, ensuring that subsequent circuits are correctly shut down. The outputs of the fourth and fifth NOR gates are low. The set signals SET for the first and second flip-flops are initially low, setting the two flip-flops, and their inverted outputs OUT1 and OUT2 are both low, ensuring that the initial logic of the latch composed of the second and third NOR gates is not affected. Then, still before system enable, the POR signal changes from high to low. Since the START signal remains unchanged, the output of the fourth NOR gate is still low, causing the SET signal to go high, releasing the set of the first and second flip-flops; other signals remain unchanged. At this time, the external enable signal EN jumps high, controlling the first NMOS transistor to turn on. Since the second current source has a larger current capability than the first current source, after a certain delay, the output of the first inverter... When the EN_INT signal flips to a low level, it indicates that the external enable signal is currently considered valid. This delay prevents glitches in the EN signal from causing system malfunctions. After the EN_INT signal flips to a low level, the output of the fourth inverter will flip from its initial low level to a high level after a certain delay. This will generate a high-level pulse signal at the output of the first NOR gate. The rising edge of this pulse signal will trigger the first flip-flop, causing its inverted output signal OUT1 to flip from its initial low level to a high level. Since at least one input of the first NOR gate is low, its output remains high. The inverted output of the second flip-flop also remains low. Therefore, the output of the first flip-flop sets the latch composed of the second and third NOR gates, and the module's output signal START flips to a high level, turning on the control chip. After the START signal flips to a high level, it will control the output signal VRAMP of the RAMP module to begin rising at a certain slope. If the VRAMP signal rises to the VREF voltage... If EN_INT remains low, the external enable signal is considered to be level-controlled, and the output voltage of comparator CMP is high. If the EN_INT signal returns to high before the VRAMP signal rises to the VREF voltage, the enable signal is considered to be pulse-triggered, pulling the VRAMP signal low and the output voltage of comparator CMP is low.In the level-triggered case, once the !EN_INT signal flips high, it indicates a desire to shut down the system. This means the output of the first OR gate will flip high, as will the output of the second OR gate. This will generate a low-level pulse signal at the output of the first NAND gate. The second flip-flop, triggered by a falling edge, will have its negative output flip high, causing the START output signal to flip low and shutting down the entire chip. Simultaneously, a high-level pulse is generated at the output of the fourth NOR gate, resetting the first and second flip-flops to prepare for the next startup. The RAMP module pulls the VRAMP signal low. In the pulse-triggered case, if the !EN_INT signal initially flips high but the system still doesn't want to shut down, and the output of the comparator CMP is low, as is the output of the second OR gate, the output of the first NAND gate is locked high, preventing any action from the second flip-flop. Therefore, the START signal remains high to ensure normal system operation. After the system has been operating for a period of time, the external enable signal EN generates another pulse. It is assumed that the VRAMP signal has risen sufficiently above the VREF voltage during this time. Therefore, the output voltage of the comparator CMP is already high. The EN_INT signal then toggles low, generating a high-level pulse at the output of the first NOR gate. This causes the inverting output of the first flip-flop to change from high to low. When EN_INT toggles low again, similar to the first case, a low-level pulse is generated at the output of the first NAND gate, controlling the inverting output of the second flip-flop, OUT2, to toggle high, which in turn causes the START signal to toggle low, shutting down the chip.

[0010] Based on the above description of this enabling circuit, it can be seen that the present invention has a simple structure and can be applied to both pulse enabling and level enabling, making it more suitable for a wider range of application scenarios.

Claims

1. An enabling circuit, characterized in that, Includes a first NMOS transistor MN1, a first current source IB1, a second current source IB2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first Schmitt trigger SMIT1, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a first OR gate OR1, a second OR gate OR2, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a comparator CMP, a first NAND gate NAND1, and RA. The MP module comprises a first T flip-flop and a second T flip-flop. The gate of the first NMOS transistor MN1 is connected to an enable signal, and its drain is connected to one end of the first current source IB1, one end of the first capacitor C1, and the input of the first Schmitt trigger SMIT1. The source of the first NMOS transistor MN1 is connected to one end of the second current source IB2. The other end of the first current source IB1 is connected to a power supply, and the other ends of the second current source IB2 and the first capacitor C1 are grounded. The output of the first Schmitt trigger SMIT1 is connected to the input of the first inverter INV1. The output of the first inverter INV1 is connected to one input of the first OR gate OR1, one input of the eighth inverter INV8, and one input of the RAMP module. The first OR gate OR1... The other input is connected to the reset signal. The output of the first OR gate (OR1) is connected to one input of the first NOR gate (NOR1), the input of the second inverter (INV2), and the first input of the first NAND gate (NAND1). The output of the second inverter (INV2) is connected to one end of the second capacitor (C2) and the input of the third inverter (INV3). The output of the third inverter (INV3) is connected to one end of the third capacitor (C3) and the input of the fourth inverter (INV4). The output of the fourth inverter (INV4) is connected to the other input of the first NOR gate (NOR1) and the second input of the first NAND gate (NAND1). The other ends of the second capacitor (C2) and the third capacitor (C3) are grounded. The output of the first NOR gate (NOR1) is connected to the clock signal input of the first T flip-flop. The first T flip-flop's set signal is connected to the output of the fifth NOR5 gate; the first T flip-flop's inverted output is connected to one input of the second NOR2 gate; the second NOR2 gate's other input is connected to the output of the third NOR3 gate. The first NAND1 gate's output is connected to the clock signal of the second T flip-flop; the second T flip-flop's set signal is connected to the output of the fifth NOR5 gate; the second T flip-flop's inverted output is connected to the first input of the third NOR3 gate; the third NOR3 gate's second input is connected to the reset signal; the third NOR3 gate's third input is connected to the output of the second NOR2 gate; and the third NOR3 gate's output is the output of the enable circuit.The first T flip-flop is active on the rising edge, and the second T flip-flop is active on the falling edge. The output of the eighth inverter INV8 is connected to one input of the second OR gate OR2, the other input of the second OR gate OR2 is connected to the output of the comparator, and the output of the second OR gate OR2 is connected to the third input of the first NAND gate NAND1. The other input of the RAMP module is connected to the output of the third NOR gate NOR3. The output of the RAMP module outputs the VRAMP voltage to the positive input of the comparator, and the negative input of the comparator is connected to the reference voltage. The input of the fifth inverter INV5 is connected to the output of the third NOR gate NOR3. The output of inverter INV5 is connected to one end of the fourth capacitor C4 and the input of the sixth inverter INV6. The output of the sixth inverter INV6 is connected to one end of the fifth capacitor C5 and the input of the seventh inverter INV7. The output of the seventh inverter INV7 is connected to one input of the fourth NOR gate NOR4. The other ends of the fourth capacitor C4 and the fifth capacitor C5 are grounded. The other input of the fourth NOR gate NOR4 is connected to the output of the triple NOR gate NOR3. The output of the fourth NOR gate NOR4 is connected to one input of the fifth NOR gate NOR5. The other input of the fifth NOR gate NOR5 is connected to the reset signal.

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