3D-ic baseband chip, stacked chip, and data processing method

Abstract

The application discloses a 3D-IC baseband chip, a stacked chip and a data processing method. Network topology is constructed in a logic unit to connect each network node, so that communication between each network node no longer relies on bus arbitration, but utilizes node-to-node communication. Each network node can establish its own communication path in the network topology to access the storage array corresponding to other network nodes without interference and queuing, thereby improving data processing efficiency. In addition, the storage unit is integrated in the chip and divided into multiple storage arrays. The network node can directly access the corresponding storage array for access operation, thereby improving the efficiency of accessing data from the storage unit and the computing performance of the entire 3D-IC baseband chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to 3D-IC baseband chips, stacked chips, and data processing methods. Background Technology

[0002] In existing technologies, baseband chips are generally lumped-type baseband chips. For example... Figure 1 The chip internally interconnects computing units such as CPU110, soft core array 120, and accelerator 130 in a lumped manner using a bus, while externally, discrete memory (not shown in the figure) is used to store data.

[0003] Based on this structural design, if multiple on-chip computing units access off-chip memory simultaneously, they must queue at the bus and wait for bus arbitration before accessing the memory sequentially. This reduces the data processing efficiency of each computing unit, leading to poor baseband chip performance. Furthermore, using discrete off-chip memory results in low data access efficiency and high latency, further limiting the performance of the baseband chip. Summary of the Invention

[0004] This invention provides a 3D-IC baseband chip, a stacked chip, and a data processing method to solve the technical problem of poor performance of baseband chips in the prior art due to low data processing efficiency.

[0005] According to a first aspect of the present invention, a 3D-IC baseband chip is provided, comprising: a logic unit and a memory unit, wherein the memory unit comprises a plurality of memory arrays, and each memory array is provided with a bump array;

[0006] The logical unit includes multiple routing nodes and multiple network nodes. The multiple routing nodes are interconnected to form a network topology. Each routing node is connected to a corresponding network node. The network node is connected to the corresponding storage array through a corresponding convex array.

[0007] According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the logic unit further includes a storage controller for controlling at least a portion of the storage array of the storage unit, the storage controller connecting at least a portion of the routing nodes and / or at least a portion of the network nodes, and at least a portion of the network nodes sharing the same storage controller for storing access to at least a portion of the storage array.

[0008] According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the logic unit further includes a plurality of storage controllers, each of the routing nodes and / or each of the network nodes is connected to a storage controller, and the network nodes respectively use their respective storage controllers to access the storage array controlled by the storage controller.

[0009] According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the logic unit further includes: a buffer, the buffer being connected to the memory unit via a corresponding bump array, the buffer being used to convert the voltage of the memory unit into the voltage of the logic unit; or to convert the voltage of the logic unit into the voltage of the memory unit.

[0010] According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the network node is one of the following: a soft core, an accelerator, a soft core cluster, or an accelerator cluster.

[0011] According to a preferred embodiment of the 3D-IC baseband chip of the present invention, any one of the network nodes accesses the storage array corresponding to the other network nodes through the routing nodes it is connected to and the routing nodes connected to the other network nodes; or

[0012] Any of the network nodes can access at least one of the soft cores, accelerators, soft core clusters, and accelerator clusters corresponding to the other network nodes through the routing nodes it connects to and the routing nodes connected to the other network nodes.

[0013] According to a preferred embodiment of the 3D-IC baseband chip of the present invention, the storage unit includes: a DRAM unit and an NVM unit;

[0014] The network node is connected to the storage array corresponding to the DRAM unit through a first bump array, and the network node is connected to the storage array corresponding to the NVM unit through a second bump array.

[0015] The storage controller includes a DRAM controller and an NVM controller. The DRAM controller controls the storage array corresponding to the DRAM unit, and the NVM controller controls the storage array corresponding to the NVM unit.

[0016] According to a preferred embodiment of the 3D-IC baseband chip of the present invention,

[0017] The network node uses the corresponding DRAM controller to access the storage array in the DRAM cell controlled by the DRAM controller;

[0018] The network node uses the corresponding NVM controller to access the storage array in the NVM unit controlled by the NVM controller.

[0019] A second aspect of the present invention provides a stacked chip, comprising a 3D-IC baseband chip of any of the above-described embodiments;

[0020] The processor is connected to the 3D-IC baseband chip of any of the above schemes in a three-dimensional stack.

[0021] A third aspect of the present invention provides a data processing method, which is applied to a 3D-IC baseband chip according to any of the above-described schemes, the data processing method comprising:

[0022] Each network node receives its own data processing request;

[0023] Each network node accesses its corresponding storage array through its corresponding convex array based on its respective data processing request; and / or

[0024] Each network node establishes its own communication path in the network topology based on its own data processing request to access the storage array corresponding to its data processing request.

[0025] According to a preferred embodiment of the data processing method of the present invention, if at least some of the network nodes are connected to the same storage controller, the method further includes:

[0026] At least some of the network nodes arrive at the same storage controller through their respective communication paths based on their respective data processing requests, and queue up to access the storage array corresponding to their respective data processing requests using the same storage controller.

[0027] According to a preferred embodiment of the data processing method of the present invention, if each network node is connected to its respective storage controller, the method further includes:

[0028] Each network node, based on its own data processing request, reaches the storage controller corresponding to its own data processing request through its own communication path, and accesses the storage array corresponding to its own data processing request using the storage controller corresponding to its own data processing request.

[0029] According to a preferred embodiment of the data processing method of the present invention, the method further includes:

[0030] If the storage array corresponding to the data processing request belongs to a DRAM cell, each network node, driven by the DRAM controller, accesses the storage array corresponding to the data processing request in the DRAM cell through the first bump array.

[0031] If the storage array corresponding to the data processing request belongs to an NVM unit, each network node, driven by the NVM controller, accesses the storage array corresponding to its respective data processing request in the NVM unit through the second convex array.

[0032] Through one or more technical solutions of the present invention, the present invention has the following beneficial effects or advantages:

[0033] This invention provides a 3D-IC baseband chip, stacked chips, and a data processing method. By constructing a network topology within the logic unit to connect network nodes, communication between network nodes no longer relies on bus arbitration but instead utilizes node-to-node communication. Each network node can establish its own communication path in parallel within the network topology to access the memory arrays of other network nodes without interference or queuing, thus improving data processing efficiency. Furthermore, by integrating the memory units on-chip and dividing them into multiple memory arrays, network nodes can directly access their corresponding memory arrays through the corresponding bump arrays, thereby improving the efficiency of data access from memory units and ultimately enhancing the overall computing performance of the 3D-IC baseband chip.

[0034] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0036] Figure 1 This diagram illustrates the structure of a lumped baseband chip in the prior art.

[0037] Figure 2A This invention illustrates a structure of a 3D-IC baseband chip in an embodiment of the present invention;

[0038] Figure 2B This illustrates another structure of the 3D-IC baseband chip in an embodiment of the present invention;

[0039] Figure 3A The network topology in the logic unit of this embodiment is shown;

[0040] Figure 3B This illustrates one combination of network nodes in a network topology according to an embodiment of the present invention;

[0041] Figure 3C This illustrates another combination of network nodes in the network topology in an embodiment of the present invention;

[0042] Figure 4A The following is an illustration of a logic unit in an embodiment of the present invention. Figure 3A A structure based on the network topology;

[0043] Figure 4B The following is an illustration of a logic unit in an embodiment of the present invention. Figure 3A Another structure based on the network topology;

[0044] Figure 4C This invention illustrates a connection structure for different types of memory controllers in a logic unit according to an embodiment of the invention.

[0045] Figure 4D The following is an illustration of a logic unit in an embodiment of the present invention. Figure 3C A structure based on the network topology;

[0046] Figure 5 A flowchart of data processing in an embodiment of the present invention is shown.

[0047] Explanation of reference numerals in the attached figures: CPU 110, soft core array 120, accelerator 130, substrate 200, logic unit 210, routing node 2101, network node 2102, soft core 21021, soft core cluster 21022, accelerator cluster 21023, memory controller 2103, DRAM controller 21031, NVM controller 20132, buffer 2104, memory unit 220, DRAM unit 2201, NVM unit 2202. Detailed Implementation

[0048] To address the technical problem of low data processing efficiency in existing technologies, this invention provides a 3D-IC baseband chip, stacked chips, and a data processing method. Embodiments of the invention will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concept of the invention. Various structural schematic diagrams according to embodiments of the invention are shown in the accompanying drawings. These drawings are not drawn to scale, and some details are enlarged for clarity and may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual practices due to manufacturing tolerances or technical limitations. Those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if one layer / component is "above" another layer / component in one orientation, then when the orientation is reversed, that layer / component can be "below" that other layer / component.

[0049] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0050] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] This embodiment discloses a 3D-IC (three-dimensional integrated circuit) baseband chip with a processing bandwidth of over 1TB / s. The 3D-IC baseband chip includes a logic unit 210 and a storage unit 220; the logic unit 210 is used to access data from the storage unit 220. The storage unit 220 is used to store data. Figure 2A This illustration shows one structure of the 3D-IC baseband chip according to this embodiment. Figure 2A In this embodiment, logic unit 210 is packaged on substrate 200, and memory unit 220 is stacked vertically on top of logic unit 210. Logic unit 210 and memory unit 220 exist in the chip of this embodiment in the form of a "wafer". Furthermore, logic unit 210 and memory unit 220 are integrated by bonding.

[0052] In this embodiment, the storage unit 220 includes multiple storage arrays, such as two or more storage arrays. Each storage array is provided with a bump array. It is worth noting that the descriptions of quantities in the following embodiments of this application all use two or more as examples. The logic unit 210 includes multiple routing nodes 2101 and multiple network nodes 2102. The multiple routing nodes 2101 are interconnected to form a network topology. Each routing node 2101 is connected to a corresponding network node 2102. The network node 2102 is connected to the corresponding storage array through the corresponding bump array. The network topology in the logic unit 210 is shown below. Figures 3A-3C This will not be elaborated upon here. Since the storage unit 220 allocates a corresponding storage array on-chip for each network node 2102, the network node 2102 no longer needs to access data through off-chip memory. Any network node 2102 can directly access its corresponding storage array through the corresponding bump array to perform data access operations, improving data access efficiency. Furthermore, based on the network topology in the logic unit 210 of this embodiment, when any network node 2102 accesses a storage array other than its own, it can access the storage arrays corresponding to the other network nodes 2102 through the routing nodes 2101 connected to it and the routing nodes 2101 connected to the other network nodes 2102 within the network topology. As can be seen, in the 3D-IC baseband chip of this embodiment, each network node 2102 can directly access its own corresponding storage array through the corresponding bump array, or it can establish its own communication path in parallel in the network topology to access the storage arrays of other nodes. The access between each network node 2102 does not interfere with each other and there is no need to queue. Compared with the prior art, the 3D-IC baseband chip of this embodiment improves the efficiency of data processing, thereby improving the computing performance of the 3D-IC baseband chip.

[0053] As an optional embodiment, the memory unit 220 in the 3D-IC baseband chip includes multiple memory types. Figure 2B Another structure of a 3D-IC baseband chip is shown. Figure 2BIn this configuration, storage cell 220 includes DRAM (Dynamic Random Access Memory) cells 2201 and NVM (Non-Volatile Memory) cells 2202, but these do not constitute a limitation on their type or quantity. DRAM cells 2201 and NVM cells 2202 are stacked vertically in the logic cell 210. The NVM cells 2202 pass through the DRAM cells 2201 and are bonded to the logic cell 210 via TSV (Through Silicon Via) technology. Specifically, the DRAM cells 2201 include multiple corresponding memory arrays, each with a first bump array. Correspondingly, the NVM cells 2202 include multiple corresponding memory arrays, each with a second bump array. Based on this structure, the DRAM cells 2201 and NVM cells 2202 each allocate a corresponding memory array to each network node 2102. Therefore, network node 2102 connects to the memory array corresponding to DRAM cell 2201 through the first bump array, and can directly access its corresponding memory array in DRAM cell 2201 for data access operations through the first bump array. Correspondingly, network node 2102 connects to the memory array corresponding to NVM cell 2202 through the second bump array, and can directly access its corresponding memory array in NVM cell 2202 for data access operations through the second bump array. When network node 2102 accesses the memory arrays corresponding to the remaining network nodes 2102, please refer to the relevant descriptions in the foregoing embodiments, which will not be repeated here.

[0054] The above embodiments describe the specific structure of the storage unit 220. The following embodiments specifically describe the logic unit 210.

[0055] Figure 3A The network topology in logic unit 210 is shown. This topology is formed by interconnecting multiple routing nodes 2101, and each routing node 2101 is connected to a network node 2102. Since each network node 2102 can be one of the following: a soft core 21021, an accelerator 130, a soft core cluster 21022, or an accelerator cluster 21023, the network nodes 2102 in the network topology can have various combinations, and can be any combination of soft core 21021, accelerator 130, soft core cluster 21022, or accelerator cluster 21023. During communication, any network node 2102 stores and accesses at least one of the soft core 21021, accelerator 130, soft core cluster 21022, or accelerator cluster 21023 corresponding to the other network nodes 2102 through the routing nodes 2101 it is connected to and the routing nodes 2101 to which the other network nodes 2102 are connected. Figure 3BThis diagram illustrates one possible combination of network nodes 2102 in a network topology, but it is not intended to be limiting. In the first direction of this network topology, of two adjacent routing nodes 2101, one routing node 2101 is connected to a soft core 21021, and the other routing node 2101 is connected to an accelerator 130. The soft cores 21021 and accelerators 130 are spaced apart in the first direction. Based on this structure, any soft core 21021 (or any accelerator 130) can directly access its corresponding storage array, or it can access the storage arrays corresponding to other soft cores 21021 (or other accelerators 130) through its own routing node 2101 and the routing nodes 2101 of other soft cores 21021 (or other accelerators 130). Of course, there are other possible combinations of network nodes 2102 in the network topology. For example, all routing nodes 2101 may be connected to their respective soft cores 21021; or each routing node 2101 may be randomly connected to a soft core 21021 or an accelerator 130, etc. The combination of network nodes 2102 in the network topology of this embodiment is flexible and can be selected according to the actual situation. Figure 3C Another combination of network nodes 2102 in the network topology is shown, but it is not a limitation. In the first direction of this network topology, among two adjacent routing nodes 2101, one routing node 2101 is connected to a soft core cluster 21022, and the other routing node 2101 is connected to an accelerator cluster 21023. The soft core cluster 21022 and the accelerator cluster 21023 are spaced apart in the first direction. Preferably, the soft cores 21021 in each soft core cluster 21022 are interconnected via a first bus, and the soft cores 21021 in each soft core cluster 21022 can access each other's memory arrays via the first bus. Similarly, the accelerators 130 in each accelerator cluster 21023 are interconnected via a second bus, and the accelerators 130 in each accelerator cluster 21023 can access each other's memory arrays via the second bus. Since each soft core 21021 (or each accelerator 130) under the soft core cluster 21022 (or accelerator cluster 21023) is a small-scale, short-distance communication node, a bus can ensure communication efficiency. Therefore, this network topology combined with a bus provides flexible and diverse communication methods while ensuring communication efficiency. Of course, network nodes 2102 can also have other combinations in the network topology. For example, all routing nodes 2101 can be connected to their respective soft core clusters 21022; or, in two adjacent routing nodes 2101, one routing node 2101 connects to the soft core cluster 21022, and the other routing node 2101 connects to either the soft core 21021 or the accelerator 130. It should be noted that any combination of network nodes 2102 in the network topology should be included within the scope of protection of this invention.

[0056] The logic unit 210 also includes a storage controller 2103 and a buffer 2104.

[0057] Storage controller 2103 is the "middleware" for network node 2102 to access the storage array. Storage controller 2103 controls at least a portion of the storage array in storage unit 220. Alternatively, when logic unit 210 includes multiple storage controllers 2103, each routing node 2101 and / or each network node 2102 has a corresponding storage controller 2103, and the network node 2102 uses the storage controller 2103 to access the corresponding storage array. In this embodiment, the relationship between storage controller 2103 and network node 2102 can be either one-to-many or one-to-one. The relationship between storage controller 2103 and routing node 2101 is similar to that described above.

[0058] When the storage controller 2103 corresponds to at least some of the routing nodes 2101 and / or at least some of the network nodes 2102, the storage controller 2103 is used to control at least a portion of the storage array of the storage cell 220. Specifically, the storage controller 2103 connects to at least some of the routing nodes 2101 and / or at least some of the network nodes 2102. This structural design can reduce the pressure of placement and routing while ensuring chip computing performance. When accessing the storage array, at least some of the network nodes 2102 share the same storage controller 2103 to access at least a portion of the storage array. Figure 4A The logic unit 210 is shown in Figure 3A It is a structure based on the network topology, but it does not constitute a limitation. Figure 3A The following explanation uses the routing node 2101 in the last row, which connects to each network node 2102, as an example. In this structure, the network nodes 2102 connected to the routing node 2101 in the last row are all connected to a storage controller 2103. The storage controller 2103 is connected to the buffer 2104 corresponding to each network node 2102, and the buffer 2104 corresponding to each network node 2102 is connected to its corresponding storage array in the storage unit 220 through a bump array.

[0059] When the storage controller 2103 corresponds one-to-one with the routing node 2101 and / or the network node 2102, specifically, each routing node 2101 and / or each network node 2102 is connected to a storage controller 2103. Therefore, when the network node 2102 accesses the storage array, it uses its corresponding storage controller 2103 to access the storage array controlled by the storage controller 2103. Figure 4B The logic unit 210 is shown in Figure 3A It is another structure based on the network topology, but it does not constitute a limitation. Figure 3AThe following explanation uses the routing node 2101 in the last row, which connects to each network node 2102, as an example. In this structure, each network node 2102 connected to the routing node 2101 in the last row is connected to a storage controller 2103. The storage controller 2103 is connected to the buffer 2104 corresponding to each network node 2102, and the buffer 2104 corresponding to each network node 2102 is connected to its corresponding storage array in the storage unit 220 through a bump array.

[0060] It is worth noting that different types of storage units 220 correspond to different types of storage controllers 2103. See also Figure 4C This diagram illustrates a connection structure for different types of memory controllers 2103 within logic unit 210. Based on the structure of memory unit 220 including DRAM unit 2201 and NVM unit 2202, memory controller 2103 includes: DRAM controller 21031 and NVM controller 20132. DRAM controller 21031 controls the memory array corresponding to DRAM unit 2201, and NVM controller 20132 controls the memory array corresponding to NVM unit 2202.

[0061] Furthermore, since different types of storage cells 220 correspond to different types of storage controllers 2103, network node 2102 utilizes the corresponding storage controller 2103 when accessing different types of storage cells 220. Specifically, network node 2102 accesses the storage array in the DRAM cell 2201 controlled by DRAM controller 21031. Network node 2102 also accesses the storage array in the NVM cell 2202 controlled by NVM controller 20132 using the corresponding NVM controller 20132. Therefore, since network node 2102 does not interfere with each other when accessing storage cells 220, it can access each storage cell 220 in parallel to process data, thereby improving data processing efficiency.

[0062] Because the logic unit 210 also contains a communication method combining network topology and bus, Figure 4D The logic unit 210 is shown in Figure 3C It is a structure based on the network topology, but it does not constitute a limitation. Figure 3CTaking the routing node 2101 in the last row as an example, connecting to any one of the soft core clusters 21022, the explanation is similar for other soft core clusters 21022 or accelerator clusters 21023. In this structure, each soft core cluster 21022 contains three soft cores 21021, and each soft core 21021 corresponds to one memory controller 2103. The router corresponding to the soft core cluster 21022, the three soft cores 21021 in the soft core cluster 21022, and the memory controllers 2103 corresponding to each of the three soft cores 21021 are interconnected through a first bus. Since the memory controller 2103 includes a DRAM controller 21031 and an NVM controller 20132, each soft core 21021 is connected to one DRAM controller 21031 and one NVM controller 20132 respectively. The DRAM controller 21031 is connected to the corresponding buffer 2104, and the buffer 2104 is connected to the memory array corresponding to the DRAM cell 2201 through the corresponding first bump array. The NVM controller 20132 is connected to the corresponding buffer 2104, and the buffer 2104 is connected to the storage array corresponding to the NVM cell 2202 through the corresponding second bump array.

[0063] Buffer 2104 is connected between storage controller 2103 and storage cell 220. See also Figures 4A-4D Specifically, buffer 2104 is connected to the memory array in memory cell 220 via a corresponding bump array. One buffer 2104 is connected to one memory array via a corresponding bump array. Specifically, based on the structure of memory cell 220 including DRAM cell 2201 and NVM cell 2202, buffer 2104 is connected to the memory array corresponding to DRAM cell 2201 via a first bump array, and buffer 2104 is connected to the memory array corresponding to DRAM cell 2201 via a second bump array. Since the required voltages of memory cell 220 and logic cell 210 may differ, buffer 2104 has a voltage coordination function. For example, it converts the voltage of memory cell 220 to the voltage of logic cell 210; or it converts the voltage of logic cell 210 to the voltage of memory cell 220. Buffer 2104 adapts the voltages of memory cell 220 and logic cell 210 to each other, reducing the risk of baseband chip burnout.

[0064] The above is a detailed structural description of the logic unit 210. In this embodiment, a network topology is constructed within the logic unit 210 to connect each network node 2102, enabling communication between network nodes 2102 to bypass bus arbitration and instead utilize inter-node communication. Therefore, upon receiving their respective data processing requests, each network node 2102 can independently and in parallel construct its own communication path within the network topology to access the storage array corresponding to its data processing request. Furthermore, since the storage controller 2103 and the network nodes 2102 have a one-to-one correspondence, each network node 2102 can independently and in parallel access the corresponding storage array using its corresponding storage controller 2103 when accessing the storage array corresponding to its data processing request, improving data processing efficiency and thus enhancing the computing performance of the 3D-IC baseband chip.

[0065] Based on the same inventive concept as one or more of the above embodiments, this embodiment also provides a stacked chip, including a 3D-IC baseband chip and a processor as described in any of the above embodiments. The processor is three-dimensionally stacked and connected to the 3D-IC baseband chip described in any of the above embodiments.

[0066] Based on the same inventive concept as one or more of the above embodiments, this embodiment also provides a data processing method, which is applied to the 3D-IC baseband chip described in any of the above embodiments. See also Figure 5 The method specifically includes the following steps:

[0067] Step 501: Each network node 2102 receives its own data processing request.

[0068] Specifically, the data processing request is either a request to perform read / write operations on the storage array corresponding to network node 2102 itself, or a request to perform read / write operations on the storage arrays corresponding to other network nodes 2102. Each network node 2102 has different access methods depending on the different data processing requests. Further, if all data processing requests in each network node 2102 are requests to perform read / write operations on its own corresponding storage array, then step 502 is executed. If all data processing requests in each network node 2102 are requests to perform read / write operations on the storage arrays corresponding to other network nodes 2102, then step 503 is executed. Of course, if some data processing requests in each network node 2102 are requests to perform read / write operations on the storage array corresponding to itself, and some are requests to perform read / write operations on the storage arrays corresponding to other network nodes 2102, then steps 502 and 503 are executed in parallel.

[0069] In step 502, each network node 2102 accesses its corresponding storage array through its own convex dot array based on its respective data processing request. As can be seen, since the storage unit allocates a corresponding storage array to each network node 2102 on-chip, the convex dot array of each network node 2102 directly accesses its own storage array for access operations, improving the efficiency of data access from the storage unit and thus improving the overall computing performance of the 3D-IC baseband chip.

[0070] In step 503, each network node 2102 establishes its own communication path within the network topology to access the storage array corresponding to its respective data processing request, based on its own data processing request. Because the network topology changes the communication method between network nodes 2102, communication between them no longer relies on bus arbitration but instead utilizes inter-node communication. Therefore, each network node 2102 can independently and in parallel establish its own communication path within the network topology to access the storage array corresponding to its own data processing request, based on its own data processing request. Access between network nodes 2102 does not interfere with each other and there is no need to queue, thereby improving data processing efficiency and further enhancing the computing performance of the 3D-IC baseband chip.

[0071] In this embodiment, the 3D-IC baseband chip's storage unit 220 includes a DRAM unit 2201 and an NVM unit 2202. Each network node 2102 is allocated a corresponding storage array for each DRAM unit 2201 and NVM unit 2202. Accessing the storage arrays corresponding to different storage units 220 requires utilizing their respective storage controllers 2103. The DRAM unit 2201 corresponds to the DRAM controller 21031, and the NVM unit 2202 corresponds to the NVM controller 20132. Therefore, if the storage array corresponding to the data processing request belongs to the DRAM unit 2201, each network node 2102, driven by the DRAM controller 21031, accesses the storage array corresponding to its respective data processing request in the DRAM unit 2201 through the first bump array; if the storage array corresponding to the data processing request belongs to the NVM unit 2202, each network node 2102, driven by the NVM controller 21032, accesses the storage array corresponding to its respective data processing request in the NVM unit 2202 through the second bump array. As can be seen, since the network nodes 2102 do not interfere with each other when accessing each storage unit 220, they can access each storage unit 220 in parallel to process data, thereby improving the efficiency of data processing.

[0072] As an optional embodiment, in the 3D-IC baseband chip, the storage controller 2103 and network node 2102 can have a "one-to-many" or "one-to-one" correspondence. The correspondence between the storage controller 2103 and the routing node 2101 is similar to that described above.

[0073] When the storage controller 2103 and network nodes 2102 have a one-to-many correspondence, if at least some network nodes 2102 are connected to the same storage controller 2103, then, based on this structure, since the same storage controller 2103 needs to respond to the data processing requests of at least some of the network nodes 2012, if the storage controller 2103 is busy, these network nodes 2102 need to queue up when using the storage controller 2103. In specific implementation, at least some network nodes 2102 reach the same storage controller 2103 directly and / or through their respective communication paths based on their respective data processing requests, and queue up to access the storage array corresponding to their respective data processing requests using the same storage controller 2103.

[0074] When the storage controller 2103 and network node 2102 have a one-to-one correspondence, each network node 2102 is connected to its respective storage controller 2103. Based on this structure, since the storage controller 2103 and network node 2102 are in a one-to-one correspondence, each network node 2102, based on its own data processing request, directly and / or through its own communication path, reaches the storage controller 2103 corresponding to its respective data processing request, and independently and in parallel accesses the storage array corresponding to its data processing request using its respective storage controller 2103. Therefore, in this embodiment, in addition to establishing their own communication paths in parallel, each network node 2102 can also access the relevant storage array using its corresponding storage controller 2103. Thus, the 3D-IC baseband chip in this embodiment can support parallel data processing by each network node 2102, thereby improving the data processing efficiency of each network node 2102 and further improving the computing performance of the 3D-IC baseband chip.

[0075] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0076] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A 3D-IC baseband chip, characterized in that, include: The system comprises a logic unit and a storage unit. The storage unit includes multiple storage arrays, each of which has a bump array. The logic unit also includes a storage controller and a buffer. The logic unit is packaged on a substrate. Storage units are stacked vertically in the logic unit. Each network node is allocated a corresponding storage array on-chip. The network node no longer needs to access external memory to access data. Any network node can directly access its corresponding storage array through the corresponding bump array to perform data access operations. The storage controller is connected to the buffer corresponding to each network node. The buffer corresponding to each network node is connected to its corresponding storage array in the storage unit through the bump array. The logical unit includes multiple routing nodes and multiple network nodes. The multiple routing nodes are interconnected to form a network topology. Each routing node is connected to a corresponding network node. The network node is connected to the corresponding storage array through a corresponding convex array.

2. The 3D-IC baseband chip according to claim 1, characterized in that, The logic unit further includes a storage controller for controlling at least a portion of the storage array of the storage unit. The storage controller connects at least a portion of the routing nodes and / or at least a portion of the network nodes, and at least a portion of the network nodes share the same storage controller to access at least a portion of the storage array.

3. The 3D-IC baseband chip according to claim 2, characterized in that, The logic unit further includes multiple storage controllers, with each routing node and / or each network node connected to a storage controller, and each network node accessing the storage array controlled by the storage controller using its respective storage controller.

4. The 3D-IC baseband chip according to claim 2 or 3, characterized in that, The logic unit further includes a buffer, which is connected to the memory unit via a corresponding bump array. The buffer is used to convert the voltage of the memory unit into the voltage of the logic unit; or to convert the voltage of the logic unit into the voltage of the memory unit.

5. The 3D-IC baseband chip according to claim 4, characterized in that, The network node is one of the following: a soft core, an accelerator, a soft core cluster, or an accelerator cluster.

6. The 3D-IC baseband chip according to claim 5, characterized in that, Any of the network nodes can access the storage arrays corresponding to the other network nodes through the routing nodes it connects to and the routing nodes to which the other network nodes are connected. or Any of the network nodes can access at least one of the soft cores, accelerators, soft core clusters, and accelerator clusters corresponding to the other network nodes through the routing nodes it connects to and the routing nodes connected to the other network nodes.

7. The 3D-IC baseband chip according to claim 6, characterized in that, The storage unit includes: a DRAM unit and an NVM unit; The network node is connected to the storage array corresponding to the DRAM unit through a first bump array, and the network node is connected to the storage array corresponding to the NVM unit through a second bump array. The storage controller includes a DRAM controller and an NVM controller. The DRAM controller controls the storage array corresponding to the DRAM unit, and the NVM controller controls the storage array corresponding to the NVM unit.

8. The 3D-IC baseband chip according to claim 7, characterized in that, The network node uses the corresponding DRAM controller to access the storage array in the DRAM cell controlled by the DRAM controller; The network node uses the corresponding NVM controller to access the storage array in the NVM unit controlled by the NVM controller.

9. A stacked chip, characterized in that, Including a 3D-IC baseband chip according to any one of claims 1-8; The processor is three-dimensionally stacked and connected to the 3D-IC baseband chip of any one of claims 1-8.

10. A data processing method, characterized in that, The data processing method is applied to the 3D-IC baseband chip according to any one of claims 1-8, and the data processing method includes: Each network node receives its own data processing request; Each network node accesses its corresponding storage array through its corresponding convex array based on its respective data processing request; and / or Each network node establishes its own communication path in the network topology based on its own data processing request to access the storage array corresponding to its data processing request.

11. The data processing method according to claim 10, characterized in that, If at least some of the network nodes are connected to the same storage controller, the method further includes: At least some of the network nodes arrive at the same storage controller through their respective communication paths based on their respective data processing requests, and queue up to access the storage array corresponding to their respective data processing requests using the same storage controller.

12. The data processing method according to claim 10 or 11, characterized in that, If each network node is connected to its respective storage controller, the method further includes: Each network node, based on its own data processing request, reaches the storage controller corresponding to its own data processing request through its own communication path, and accesses the storage array corresponding to its own data processing request using the storage controller corresponding to its own data processing request.

13. The data processing method according to claim 10, characterized in that, The method further includes: If the storage array corresponding to the data processing request belongs to a DRAM cell, each network node, driven by the DRAM controller, accesses the storage array corresponding to the data processing request in the DRAM cell through the first bump array. If the storage array corresponding to the data processing request belongs to an NVM unit, each network node, driven by the NVM controller, accesses the storage array corresponding to its respective data processing request in the NVM unit through the second convex array.

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