A real-time transmission protocol stack based on FPGA and its hardware implementation method

Abstract

The present invention belongs to the field of network communication technology, and relates to a real-time transmission protocol stack based on FPGA and a hardware implementation method thereof, which can be used to upload video data to a network in real time. The development of a real-time transmission protocol stack is realized in a pure hardware manner, and the protocol stack adopts pure hardware programming. The clock of each module or each execution step in the protocol stack can be precisely controlled to ensure that the protocol stack can achieve low latency, high precision and high reliability when data is transmitted in real time; a working mode similar to FIFO is adopted to update the cache table, which can effectively save clock and timer resources, and when used in a real-time transmission protocol stack with data transmission as the main task, the table lookup time can be effectively shortened and the transmission delay can be reduced; a priority setting strategy is adopted to solve the conflict problem that may occur when multiple RTP or RTCP data transmission modules are loaded, which can effectively save hardware resources compared to the traditional method of caching data.

Description

Technical Field

[0001] The present invention belongs to the technical field of network communication, and relates to a real-time transmission protocol stack based on FPGA and a hardware implementation method thereof, which can be used to upload video data to a network in real time. Background Art

[0002] With the rapid development of network equipment and the increasing popularity of Ethernet, the data transmitted on the network is no longer simple pictures and texts, but is transitioning to video and audio data. Due to the limitations of network bandwidth and storage space, some image acquisition devices find it difficult to collect a large amount of data and then transmit it to the network in the form of video data. The Real-time Transport Protocol (PRT) can upload data while displaying it at the receiving end, without the need to cache the entire video data before playing it as usual; it can also ensure that the signal source bandwidth matches the current network status, and it can also be used to achieve real-time data transmission in one-to-one, one-to-many, or even many-to-many network environments.

[0003] At present, most of the existing real-time data transmission systems use embedded systems with ARM as the core, and the internal network communication protocols are mostly programmed by software. This has the following disadvantages when transmitting video data: (1) The amount of video data is large and the transmission time is generally long. During the transmission process, it will seriously occupy the core controller resources and affect the scheduling and execution of other tasks. (2) If an additional dedicated Ethernet chip is used, the cost will increase and the overall complexity of the system will increase. (3) The software protocol stack used is mostly serial execution, and the execution efficiency is low.

[0004] The current real-time transmission hardware protocol stacks based on FPGA design have the following problems: (1) Some protocols only implement the protocol data receiving and sending functions of the network layer and protocol layer, but do not implement the functions of dynamically matching MAC addresses and IP addresses and establishing ARP cache tables, or the table lookup delay is large; (2) Early hardware protocol stacks are mostly used for 100M Ethernet, with relatively fixed and small input and output bit widths, and a long clock is required for internal data processing, making it difficult to give full play to the advantages of FPGA parallel processing; Summary of the invention

[0005] The purpose of the present invention is to provide a hardware implementation method of a real-time transport protocol stack based on FPGA in view of the above problems and shortcomings.

[0006] The technical solution of the present invention is as follows:

[0007] A real-time transmission protocol stack based on FPGA, comprising:

[0008] The RTP layer control module configures relevant register parameters and controls the data transmission and information interaction of each submodule belonging to the RTP layer;

[0009] The core function of the RTP session information table module is to maintain an RTP session information table for storing parameter information of each member in the RTP session, which is used by the RTP data sending module and the RTCP data sending module to generate data packets, and by the RTP data receiving module and the RTCP data receiving module to parse data packets;

[0010] RTP data transmission buffer module is used to buffer data packets transmitted from the upper layer network / user protocol;

[0011] The RTP data sending module is used to package the data output from the RTP data sending buffer module into an RTP packet format and send it to the UDP / IP layer network arbitration module;

[0012] RTP data receiving buffer module, used to store the data in the RTP packets that have been parsed;

[0013] RTP data receiving module, used to unpack the data packets sent from the UDP / IP layer network arbitration module and extract the upper layer network / user data;

[0014] RTCP data sending module, used for UDP / IP layer network arbitration module to send RTCP packets, which contain protocols and related parameters for controlling RTP communication quality;

[0015] RTCP data receiving module, used for UDP / IP layer network arbitration module to receive RTCP packets and unpack the control protocol and related parameters;

[0016] The UDP / IP layer network arbitration module configures the relevant register parameters to process when multiple RTP layer data sending modules simultaneously request to use the network to send data, and decide which data source has priority to send data; or to send the data packets parsed by the UDP / IP data receiving module to the corresponding RTP data receiving module and RTP data receiving module;

[0017] The UDP / IP data sending module is used to package the data packets outputted from the RTP data sending module and the RTCP data sending module into the corresponding UDP / IP packet format according to IPv4 and send it to the ARP layer protocol;

[0018] The UDP / IP data receiving module is used to decompress the UDP / IP packets obtained from the ARP layer, extract the corresponding RTP or RTCP data packets according to the decompressed packet type, IP address and port number, and send them to the UDP / IP layer network arbitration module;

[0019] The ARP layer control module is used to control the data transmission and information interaction of each submodule belonging to the ARP layer. At the same time, it verifies the MAC frame type unpacked by the MAC layer protocol to determine whether it is transmitted to the UDP / IP data receiving module or sent to the ARP packet receiving module;

[0020] ARP data sending module, used for sending ARP data packets to the MAC layer data sending module;

[0021] An ARP data transmission cache module is used to cache data packets when the ARP data transmission module queries the ARP table;

[0022] An ARP data receiving module is used to receive ARP data packets from a MAC layer data receiving module;

[0023] The MAC layer data transmission module is used to pack the data packets transmitted by the upper layer protocol into MAC frames and perform corresponding bit width conversion according to the input bandwidth of the MAC layer controller;

[0024] The MAC layer data receiving module performs corresponding bit width conversion according to the output bandwidth of the MAC layer controller, and is used to unpack and verify the MAC frame. After the verification is correct, the data is transmitted to the upper layer protocol module.

[0025] The RTP data sending buffer module and the RTP data receiving buffer module include an asynchronous clock FIFO, which is used to handle the problem of data misalignment caused by the user-side data sending clock being out of sync with the internal clock of the protocol stack; and a bit width adjustment module, which is used to handle the problem of the user-side input data bit width being different from the FIFO input bit width.

[0026] The ARP session information storage module includes an RTP sending member table, an RTP common member table, an X-bit pseudo-random number generation module and a Y-bit absolute time timer module. The RTP sending member table and the RTP common member table are used to record the number of session members and related parameters, and are used to adjust the packet sending speed and frequency. When the data in the RTP or RTCP packet is received, the parameters of the related members will be updated. The X-bit pseudo-random number generation module is used to generate the SSRC identity of the sender, which is globally unique. The Y-bit absolute time timer module is used to generate a timestamp for data synchronization.

[0027] The UDP / IP layer network arbitration module includes a network member table for storing network IP addresses, network port numbers and corresponding sending priorities.

[0028] The ARP layer control module includes an ARP cache table for storing MAC addresses and their corresponding IP addresses.

[0029] The RTP session information table and the ARP cache table include an X-bit register and a Y-bit lifetime counter. The register acts as a table carrier to store data entries. When the data in the entry is updated or used, the counter is cleared and restarted. When the lifetime is exceeded and the data in the entry is not updated or used, the entry is deleted from the table.

[0030] The data cache part in the RTP data sending cache module, the RTP data receiving cache module, and the ARP data sending cache module are composed of ordinary asynchronous FIFOs, including a write clock signal line, a read clock signal line, a write enable signal line, a read enable signal line, a group of write data lines, a group of read data lines, a FIFO empty flag signal line, a FIFO full flag signal line, a group of data number counting lines and a reset signal line.

[0031] The steps of the hardware implementation method of the real-time transmission protocol stack based on FPGA are as follows:

[0032] 1. Establish an RTP session:

[0033] (1.1) First, the external module inputs the local MAC address, IP address and IP port number, starts the RTP layer control module and goes to step (1.2);

[0034] (1.2) The RTP layer control module calls the RTP session information table module, first generating a series of parameters required for the local network communication. If the generation is successful, go to (1.3), otherwise go to (1.1);

[0035] (1.3) The destination IP address and destination port number are input from the external module and stored in the RTP session information table module and the UDP / IP network arbitration module, the corresponding priority is configured, and the process ends;

[0036] 2. Generate RTCP packets:

[0037] (2.1) It is detected that the local machine has generated a valid RTP session;

[0038] (2.2) The RTP session information table module will start to query the parameters in the RTP session table, output the current status of the local machine, and calculate the current RTCP transmission interval;

[0039] (2.3) The counter module starts counting according to the time interval. When the transmission time interval count is full, a corresponding RTCP compound packet is sent according to the member type and related parameters in the RTP session table;

[0040] 3. Send data frame:

[0041] (3.1) The RTP layer control module receives the upper layer network / user protocol start signal;

[0042] (3.2) The RTP sending module receives the start signal, packages the received data into the RTP packet format, sends the data packet header first, and if no blocking signal is received, sends the data from the RTP data buffer module;

[0043] (3.3) The UDP / IP layer network arbitration module sends the RTP data packets to the corresponding network addresses and ports in turn according to the corresponding priorities, and sends blocking signals to other upper layer ports;

[0044] (3.4) The UDP / IP data sending module encapsulates the received data packets into UDP\IP data packets according to the IP protocol rules and UDP protocol rules and sends them to the ARP layer control module;

[0045] (3.5) The ARP layer control module detects whether there is a MAC address matching the destination IP address in the ARP table cache. If yes, go to step (3.8), otherwise go to step (3.7);

[0046] (3.6) The ARP data sending module sends an ARP request packet and waits for a response packet. If a response packet is received within the specified time, it goes to step (3.8), otherwise the process ends;

[0047] (3.7) The MAC layer data transmission module encapsulates the data packets sent by the upper layer protocol into MAC frames, adds a frame header, adjusts the output bit width according to the lower layer MAC controller, and finally sends the MAC frame.

[0048] (3.8) The data transmission timeout occurs, the ARP layer related modules are reset, and the process ends.

[0049] 4. Receive data frame:

[0050] (4.1) Waiting for the data valid signal of the MAC controller;

[0051] (4.2) Unpack the received MAC frame data, extract the destination address, source address and frame type, and send it to the ARP layer control module if the destination address matches the local address, otherwise discard the data packet and end the process;

[0052] (4.3) The ARP layer control module goes to step (4.4) based on the parsed frame type if the protocol type is ARP type, and goes to step (4.5) if it is IP type;

[0053] (4.4) The ARP receiving module decompresses the packet according to the protocol. If the decompressed packet is a request packet, the ARP data sending module sends an ARP reply packet. Otherwise, the valid address information is extracted and stored in the ARP table cache, and the process ends.

[0054] (4.5) The UDP / IP layer receiving module unpacks the received data packet according to the IP protocol rules and the UDP protocol rules. If the IP address of the data packet is a local address, go to step (4.6); otherwise, discard the data packet and end the process;

[0055] (4.6) The UDP / IP layer network arbitration module searches the network member table according to the corresponding destination IP address and destination port. If the corresponding member is found, the remaining data packets are sent. Generally speaking, if the destination port is an odd number, go to step (4.7), and if it is an even number, go to step (4.8). Otherwise, the process ends.

[0056] (4.7) The RTCP receiving module unpacks the packet according to the relevant RTCP protocol. If it is a valid packet, it obtains the required data according to different protocol types and updates the relevant parameter data to the RTP session information table module. Otherwise, the process ends;

[0057] (4.8) The RTP data receiving module unpacks the data according to the RTP rules. If it is a valid packet, the RTP session information table module is updated according to the packet header parameter information, and the valid data in the packet is sent to the RTP receiving cache module, waiting for the upper-layer grid / user protocol to receive it; otherwise, the process ends.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] First, a real-time transmission protocol stack is developed in a pure hardware manner. Compared with the software protocol stack, the protocol stack of the present invention can run independently without relying on the CPU or other core controllers, saving controller resources; at the same time, the protocol stack adopts pure hardware programming, and the clock of each module or each execution step in the protocol stack can be precisely controlled to ensure that the protocol stack can achieve low latency, high precision and high reliability when data is transmitted in real time; at the same time, a bit width enable interface is added to the input and output interface to match a variety of upper user protocols and lower MAC controllers. When a large bit width is enabled, the advantages of FPGA parallel processing can be fully utilized, the number of clocks required for internal processing of data packets can be reduced, and the latency can be reduced;

[0060] Second, a new cache table entry update method is adopted, which uses a working mode similar to FIFO to update the cache table. This method does not need to set a lifetime for each table entry separately, which can effectively save clock and timer resources. When used in a real-time transmission protocol stack with data transmission as the main task, it can effectively shorten the table lookup time and reduce transmission delay.

[0061] Third, the strategy of setting priorities is used to solve the conflict problem that may occur when multiple RTP or RTCP data sending modules are loaded. Compared with the traditional method of caching data, it can effectively save hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is a protocol stack structure diagram of the present invention;

[0063] Figure 2 This is a flow chart of establishing a RTP session on the sending side;

[0064] Figure 3 This is a flow chart of RTCP packet generation;

[0065] Figure 4 This is a RTP data sending flow chart;

[0066] Figure 5 This is an RTP data receiving flow chart. DETAILED DESCRIPTION

[0067] The present invention will be further described below in conjunction with specific embodiments.

[0068] like Figure 1 As shown, the protocol stack of the present invention includes an RTP layer control module, an RTCP data sending module, an RTCP data receiving module, an RTP session information table module, an RTP data sending cache module, an RTP data sending module, an RTP data receiving cache module, an RTP data receiving module, a UDP / IP network arbitration module, a UDP / IP data sending module, a UDP / IP data receiving module, an ARP data sending cache module, an ARP data sending module, an ARP layer control module, an ARP data sending module, a MAC layer data sending module, and a MAC layer data receiving module.

[0069] The RTP layer control module is responsible for exchanging data with external protocols, starting the RTP session information table module, configuring relevant session parameters, and enabling the RTCP timing sending module;

[0070] The RTCP data sending module, when receiving the enable signal sent from the RTP session information table module, will send an RTCP data packet according to the current state and related parameters, and the packet can adjust the RTP session quality; the RTCP data receiving module can record the parameter changes of the session members and adjust the sending speed of the RTP data by receiving the RTCP packet.

[0071] The RTP data sending buffer module and the RTP data receiving buffer module cache data through FIFO, and have an interface bit width enabling function, so as to solve the problem of docking with the upper layer protocol interface;

[0072] The RTP data sending module can package the upper layer protocol data, add the RTP packet header, and provide the destination address and destination port according to the RTP session information table module; the RTP data receiving module can parse the RTP data packet and send the valid data to the upper layer network protocol or user module;

[0073] The UDP / IP network arbitration module can be used to solve the conflict problem caused by data transmission when there are multiple transmission destination ports, or solve the problem of port allocation after receiving data packets.

[0074] The UDP / IP data sending module can encapsulate the IP header and the UDP header, verify the header information to be encapsulated, and at the same time, the high-bit width data format can be adjusted internally to a data bit width format suitable for network transmission; the UDP / IP data receiving module can parse the IP header and the UDP header, verify the header information, and send the data packet to the corresponding destination address and destination port after the parsing is correct;

[0075] The ARP layer control module receives the data packet of the upper layer, caches the data to the ARP data cache module, and searches the ARP cache table at the same time. After matching the MAC address, the data packet is sent to the MAC layer data sending module through the ARP data sending module, otherwise the ARP data packet is sent;

[0076] The ARP layer control module receives the data frame parsed by the MAC layer data receiving module, and if it parses a common IPv4 data packet, it sends it to the UDP / IP data receiving module, and if it parses an ARP request data packet, it calls the ARP data sending module to ensure the response;

[0077] The MAC layer data sending module can be used to add a MAC frame header to the data packet of the upper layer protocol and adjust the corresponding output bit width; the MAC layer data receiving module can be used to parse the received MAC frame header to determine whether the destination address is the local address;

[0078] The RTP data transmission buffer module includes an asynchronous clock FIFO, which is used to handle the problem of data misalignment caused by the user-side data transmission clock being out of sync with the protocol stack internal clock; a bit width adjustment module, which is used to handle the problem of the user-side input data bit width being different from the FIFO input bit width;

[0079] The RTP session information table module includes an RTP sending member table; an RTP common member table; the UDP / IP layer network arbitration module includes a network member table, and the ARP layer control module includes an ARP cache table; the above basic table entry module includes an X-bit register and a Y-bit survival time counter.

[0080] Taking the ARP cache table as an example, it is assumed that a storage space that can store up to 10 entries is defined, and the content of each entry contains at least a globally unique identification information, such as address information, and a lifetime counter is initialized.

[0081] At the initial moment, assuming that the ARP cache table has stored 10 entries in table1, table2, ..., table10, and the counter value is zero, the table performs its functions in the following steps:

[0082] (1) If the count value is not full, execute step (2); otherwise, execute step (4);

[0083] (2) receiving a table entry update signal, refreshing the counter timing time, and updating the total number of table entry members;

[0084] (3) Compare the identification information of the new entry to see if it is the same as the identification information in table 1. If they are the same, discard the data packet. Otherwise, insert the entry into the storage address of table 1, store table 1 into the address of table 2, store table 2 into the address of table 3, and so on. Discard the entry in table 10.

[0085] (4) Delete the last entry and refresh the counter timer;

[0086] The initialization method of the hardware protocol stack is as follows:

[0087] After the protocol stack is powered on and reset, the registers in the UDP / IP network arbitration module as shown in Table 1 and the registers in the RTP session information table module as shown in Table 2 are set to zero initially. After that, the initial parameters can be written by the external module and the protocol stack can be started to start working. Subsequent modules read or update the relevant parameters in the two tables according to the operation status. The control contents of the registers in the UDP / IP network arbitration module and the registers in the RTP session information table module must be configured before the hardware protocol stack works. The data contents will be automatically added and deleted after the hardware protocol stack is running. The data address in this table only indicates the minimum memory address required to record the relevant parameters of a member. The data address in this table can be expanded according to actual needs.

[0088] Table 1 is the content format of the register in the UDP / IP network arbitration module

[0089]

[0090] Table 2 is the content format of the register in the RTP session information table module

[0091]

[0092] Figure 2 A flow chart of establishing a RTP session at a sending end of the present invention is shown in the following specific implementation steps:

[0093] (1) Waiting for the start signal;

[0094] (2) The upper protocol or user module writes the local MAC address, IP address and port number. If there is a conflict with the existing address, exit the process, otherwise proceed to the next step;

[0095] (3) Initialize an RTP session table, establish a local data sending member, write relevant configuration information, call the internal pseudo-random counter to generate an identity, start the lifetime counter module, and generate a configuration completion signal;

[0096] (4) The upper protocol or external module writes the destination address and destination port number;

[0097] (5) End the process.

[0098] Figure 3 A RTCP packet generation flow chart of the present invention is shown in the following specific implementation steps:

[0099] (1) Waiting for the start signal;

[0100] (2) Detecting that the local machine has generated a valid RTP session;

[0101] (3) The RTP session information table module will start to query the parameters in the RTP session table, output the current status of the local machine, and calculate the current RTCP transmission interval;

[0102] (4) When the transmission time interval is full, a full signal is input and the process goes to step (4); otherwise, it detects whether to terminate the session and executes step (5);

[0103] (5) The RTCP data sending module sends a mixed message of a sender report packet and a source description packet if it is a sender, and sends a mixed message of a receiver report packet and a source description packet if it is a receiver, according to the local state, to control the communication quality, and finally returns to step (2);

[0104] (6) If a session termination signal is detected, the RTCP data sending module will send a mixed message of a departure report packet and a source description packet;

[0105] (7) End the process.

[0106] Figure 4 It is an RTP data sending flow chart of the present invention, and the specific implementation steps are as follows:

[0107] (1) Waiting for the start signal;

[0108] (2) After receiving the send enable signal, an RTP data packet is generated and sent out;

[0109] (3) Check whether there is a network conflict. First, check whether other modules are occupying the network interface to send data; second, check whether other modules are requesting to use the network interface to send data at the same time. If the network interface is occupied or the priority of this module is low, go to step (2); otherwise, go to step (4);

[0110] (4) Outputting user data from the RTP data transmission buffer module and adding rtp_data_en and rtp_data_end signals to the data to control the transmission of data within the module;

[0111] (5) Add IPv4 format IP header and UDP header to the transmitted data, and send the packaged UDP / IP data packet. In this step, in order to give full play to the advantage of FPGA's ability to process data in parallel, a high-bit-width data transmission format is used internally; at the same time, in order for the data receiving end on the network to correctly process the received data, the internal storage format of the single-byte data is also adjusted accordingly in terms of high and low bits;

[0112] (6) The ARP layer control module matches the destination MAC address and the destination IP address of the transmitted data packet. If the match is successful, go to step (10); otherwise, go to step (7);

[0113] (7) Send an ARP request packet and temporarily store the data packet to be sent in the send buffer FIFO;

[0114] (8) A response timeout is set. After sending the ARP request packet, if an ARP response packet is received within the specified time, the MAC address matching the destination IP address is sent and the process goes to step (10). Otherwise, the process goes to step (9).

[0115] (9) If the match fails, the data in the send buffer FIFO is cleared and the process ends;

[0116] (10) Encapsulate the MAC frame header for the UDP / IP data packet, adjust the data output bit width according to the MAC layer controller, and send out the data frame;

[0117] (11)End the process.

[0118] Figure 5 It is an RTP data receiving flow chart of the present invention, and the specific implementation steps are as follows:

[0119] (1) Waiting for the start signal;

[0120] (2) After receiving the receive enable signal, it starts to receive and parse the MAC frame header. If the destination address is parsed as the local address or broadcast address, the remaining frame data is transmitted. The input interface part includes a bit width conversion module, which is used to merge the input low-bit width data into high-bit width data and then send it to other internal modules;

[0121] (3) Parse the received MAC frame and check the type of the received MAC frame. If it is of ARP type, go to step (4); otherwise, go to step (7);

[0122] (4) If the type of the ARP data packet is detected to be a request packet, go to step (6); otherwise, go to step (5);

[0123] (5) According to the ARP protocol, an ARP reply packet is encapsulated and sent;

[0124] (6) The sender's MAC address and IP address are stored in the ARP cache table, and the process ends;

[0125] (7) Unpacking the data packet according to the IPv4 format, extracting the packet header information and packet data information respectively, and immediately verifying the first extracted packet header information;

[0126] (8) First, perform IP header verification based on the checksum, then perform protocol matching. If it is UDP protocol, then perform IP address matching. If it is the local address, go to step (9), otherwise discard the remaining data and end the process. During the checksum matching operation, the IP data packet length information, IP data packet identification information, UDP length information, destination IP address and destination port number will be extracted;

[0127] (9) The remaining data stream, i.e., the UDP data packet data content, is transferred to the destination IP address and destination port number extracted in the previous step;

[0128] (10) If the destination port is an odd port, it is considered as an RTCP data packet and goes to step (11), otherwise go to step (14);

[0129] (11) Unpacking the received data packet according to the RTCP data packet format and extracting the corresponding control information;

[0130] (12) Update the relevant members and their parameters in the RTP session table according to the control information, and output the corresponding control information as required, and finally end the process;

[0131] (13) Unpacking the received data packet according to the RTP data packet format and extracting the source identifier and timestamp;

[0132] (14) Register a new sending member in the RTP session table, update its related parameters, send the user data content to the input buffer FIFO, and wait for the upper layer network protocol or user module to receive it;

[0133] (15)End the process.

Claims

1. A real-time transport protocol stack based on FPGA, characterized in that: The FPGA-based real-time transmission protocol stack includes: The RTP layer control module is responsible for exchanging data with external protocols, starting the RTP session information table module, configuring relevant session parameters, and enabling the RTCP timing sending module; An RTP session information table module is used to maintain an RTP session information table for storing parameter information of each member in the RTP session, for use by the RTP data sending module and the RTCP data sending module to generate data packets, and for use by the RTP data receiving module and the RTCP data receiving module to parse data packets; RTP data transmission buffer module, used to buffer data packets transmitted from upper layer network / user protocol; The RTP data sending module is used to package the data output from the RTP data sending buffer module into an RTP packet format and send it to the UDP / IP layer network arbitration module; RTP data receiving buffer module, used to store the data in the RTP packets that have been parsed; RTP data receiving module, used to unpack the data packets sent from the UDP / IP layer network arbitration module and extract the upper layer network / user data; RTCP data sending module, used to send RTCP packets to the UDP / IP layer network arbitration module, the packets contain protocols and related parameters for controlling RTP communication quality; RTCP data receiving module, used to receive RTCP packets from the UDP / IP layer network arbitration module and unpack the control protocol and related parameters; The UDP / IP layer network arbitration module is used to decide which data source has priority in sending data when multiple RTP layer data sending modules simultaneously request to use the network to send data; or to send the data packets parsed by the UDP / IP data receiving module to the corresponding RTP data receiving module and RTCP data receiving module; The UDP / IP data sending module is used to package the data packets outputted from the RTP data sending module and the RTCP data sending module into the corresponding UDP / IP packet format according to IPv4 and send it to the ARP layer protocol; The UDP / IP data receiving module is used to decompress the UDP / IP packets obtained from the ARP layer, extract the corresponding RTP or RTCP data packets according to the decompressed packet type, IP address and port number, and send them to the UDP / IP layer network arbitration module; The ARP layer control module receives the data packet from the upper layer, caches the data to the ARP data cache module, and searches the ARP cache table. After matching the MAC address, the data packet is sent to the MAC layer data sending module through the ARP data sending module, otherwise an ARP data packet is sent; ARP data sending module, used for sending ARP data packets to the MAC layer data sending module; An ARP data transmission cache module is used to cache data packets when the ARP data transmission module queries the ARP table; An ARP data receiving module is used to receive ARP data packets from a MAC layer data receiving module; The MAC layer data transmission module is used to pack the data packets transmitted by the upper layer protocol into a MAC frame header and perform corresponding bit width conversion according to the input bandwidth of the MAC layer controller; The MAC layer data receiving module performs corresponding bit width conversion according to the output bandwidth of the MAC layer controller, and is used to unpack and verify the MAC frame. After verification, the data is transmitted to the upper layer protocol module.

2. The real-time transport protocol stack based on FPGA according to claim 1, characterized in that: The RTP data sending buffer module and the RTP data receiving buffer module include an asynchronous clock FIFO for processing the problem of data misalignment caused by the user-side data sending clock being out of sync with the protocol stack internal clock; a bit width adjustment module for processing the problem of the user-side input data bit width being different from the FIFO input bit width; The RTP session information table module includes an RTP sending member table, an RTP common member table, an X-bit pseudo-random number generation module and a Y-bit absolute time timer module; The RTP sending member table and the RTP common member table are used to record the number of session members and related parameters, and are used to adjust the packet sending speed and frequency. When the data in the RTP or RTCP packet is received, the parameters of the relevant members will be updated. The X-bit pseudo-random number generation module is used to generate the sender's SSRC identity, which is globally unique. The Y-bit absolute time timer module is used to generate a timestamp for data synchronization; The UDP / IP layer network arbitration module includes a network member table for storing network IP addresses, network port numbers and corresponding sending priorities; The ARP layer control module includes an ARP cache table for storing MAC addresses and their corresponding IP addresses; The RTP session information table and the ARP cache table include an X-bit register and a Y-bit lifetime counter, the register acts as a table carrier to store data table items, and when the data in the table items is updated or used, the counter is cleared and restarted; When the expiration time has expired and the data in the entry has not been updated or used, the entry will be deleted from the table. The data cache part in the RTP data sending cache module, the RTP data receiving cache module, and the ARP data sending cache module are composed of ordinary asynchronous FIFOs, including a write clock signal line, a read clock signal line, a write enable signal line, a read enable signal line, a group of write data lines, a group of read data lines, a FIFO empty flag signal line, a FIFO full flag signal line, a group of data number counting lines and a reset signal line.

3. A method for hardware implementation of a real-time transport protocol stack based on FPGA according to claim 1 or 2, characterized in that: Here are the steps:

1. Establish an RTP session: (1.1) First, the external module inputs the local MAC address, IP address and IP port number, starts the RTP layer control module and goes to step (1.2); (1.2) The RTP layer control module calls the RTP session information table module, first generating a series of parameters required for the local network communication. If the generation is successful, it goes to (1.3), otherwise it goes to (1.1); (1.3) The destination IP address and destination port number are input from the external module and stored in the RTP session information table module and the UDP / IP network arbitration module, the corresponding priority is configured, and the process ends; 2. Generate RTCP packets: (2.1) It is detected that the local machine has generated a valid RTP session; (2.2) The RTP session information table module will start to query the parameters in the RTP session table, output the current status of the local machine, and calculate the current RTCP transmission interval; (2.3) The counter module starts counting according to the time interval. When the transmission time interval count is full, a corresponding RTCP compound packet will be sent according to the member type and related parameters in the RTP session table; 3. Send data frame: (3.1) The RTP layer control module receives the upper layer network / user protocol start signal; (3.2) The RTP sending module receives the start signal, packages the received data into the RTP packet format, and sends the data packet header first. If no blocking signal is received, the data is sent from the RTP data buffer module; (3.3) The UDP / IP layer network arbitration module sends the RTP data packets to the corresponding network addresses and ports in turn according to the corresponding priorities, and sends blocking signals to other upper layer ports; (3.4) The UDP / IP data sending module encapsulates the received data packets into UDP\IP data packets according to the IP protocol rules and UDP protocol rules and sends them to the ARP layer control module; (3.5) The ARP layer control module detects whether there is a MAC address matching the destination IP address in the ARP table cache. If yes, go to step (3.7), otherwise go to step (3.6); (3.6) The ARP data sending module sends an ARP request packet and waits for a response packet. If a response packet is received within the specified time, go to step (3.7), otherwise go to step (3.8); (3.7) The MAC layer data transmission module encapsulates the data packets sent by the upper layer protocol into MAC frames, adds frame headers, adjusts the output bit width according to the lower layer MAC controller, and finally sends the MAC frames; (3.8) The data transmission timeout occurs, the ARP layer related modules are reset, and the process ends; 4. Receive data frame: (4.1) Wait for the data valid signal from the MAC controller; (4.2) Unpack the received MAC frame data, extract the destination address, source address and frame type, and send it to the ARP layer control module if the destination address matches the local address, otherwise discard the data packet and end the process; (4.3) The ARP layer control module, based on the parsed frame type, goes to step (4.4) if the protocol type is ARP type, and goes to step (4.5) if it is IP type; (4.4) The ARP receiving module decompresses the packet according to the protocol. If the packet is a request packet, the ARP data sending module sends an ARP reply packet. Otherwise, the valid address information is extracted and stored in the ARP table cache, and the process ends. (4.5) The UDP / IP layer receiving module unpacks the received data packet according to the IP protocol rules and the UDP protocol rules. If the IP address of the data packet is a local address, go to step (4.6); otherwise, the data packet is discarded and the process ends; (4.6) The UDP / IP layer network arbitration module searches the network member table according to the corresponding destination IP address and destination port. If the corresponding member is found, the remaining data packets are sent. If the destination port is an odd number, go to step (4.7); if it is an even number, go to step (4.8). Otherwise, the process ends. (4.7) The RTCP receiving module unpacks the packet according to the relevant RTCP protocol. If it is a valid packet, it obtains the required data according to different protocol types and updates the relevant parameter data to the RTP session information table module. Otherwise, the process ends; (4.8) The RTP data receiving module unpacks the data according to the RTP rules. If it is a valid packet, it updates the RTP session information table module according to the packet header parameter information, and sends the valid data in the packet to the RTP receiving cache module, waiting for the upper-layer grid / user protocol to receive it; otherwise, the process ends.

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